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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2006 by Magnus Lundin *
  6. * lundin@mlu.mine.nu *
  7. * *
  8. * Copyright (C) 2008 by Spencer Oliver *
  9. * spen@spen-soft.co.uk *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  25. * *
  26. * *
  27. * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
  28. * *
  29. ***************************************************************************/
  30. #ifdef HAVE_CONFIG_H
  31. #include "config.h"
  32. #endif
  33. #include "breakpoints.h"
  34. #include "cortex_m3.h"
  35. #include "target_request.h"
  36. #include "target_type.h"
  37. #include "arm_disassembler.h"
  38. #include "register.h"
  39. #include "arm_opcodes.h"
  40. #include "arm_semihosting.h"
  41. #include <helper/time_support.h>
  42. /* NOTE: most of this should work fine for the Cortex-M1 and
  43. * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  44. * Some differences: M0/M1 doesn't have FBP remapping or the
  45. * DWT tracing/profiling support. (So the cycle counter will
  46. * not be usable; the other stuff isn't currently used here.)
  47. *
  48. * Although there are some workarounds for errata seen only in r0p0
  49. * silicon, such old parts are hard to find and thus not much tested
  50. * any longer.
  51. */
  52. /**
  53. * Returns the type of a break point required by address location
  54. */
  55. #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
  56. /* forward declarations */
  57. static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
  58. static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
  59. static void cortex_m3_enable_watchpoints(struct target *target);
  60. static int cortex_m3_store_core_reg_u32(struct target *target,
  61. enum armv7m_regtype type, uint32_t num, uint32_t value);
  62. static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
  63. uint32_t *value, int regnum)
  64. {
  65. int retval;
  66. uint32_t dcrdr;
  67. /* because the DCB_DCRDR is used for the emulated dcc channel
  68. * we have to save/restore the DCB_DCRDR when used */
  69. retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
  70. if (retval != ERROR_OK)
  71. return retval;
  72. /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
  73. retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
  74. if (retval != ERROR_OK)
  75. return retval;
  76. retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
  77. if (retval != ERROR_OK)
  78. return retval;
  79. /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
  80. retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
  81. if (retval != ERROR_OK)
  82. return retval;
  83. retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
  84. if (retval != ERROR_OK)
  85. return retval;
  86. retval = dap_run(swjdp);
  87. if (retval != ERROR_OK)
  88. return retval;
  89. /* restore DCB_DCRDR - this needs to be in a seperate
  90. * transaction otherwise the emulated DCC channel breaks */
  91. if (retval == ERROR_OK)
  92. retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
  93. return retval;
  94. }
  95. static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
  96. uint32_t value, int regnum)
  97. {
  98. int retval;
  99. uint32_t dcrdr;
  100. /* because the DCB_DCRDR is used for the emulated dcc channel
  101. * we have to save/restore the DCB_DCRDR when used */
  102. retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
  103. if (retval != ERROR_OK)
  104. return retval;
  105. /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
  106. retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
  107. if (retval != ERROR_OK)
  108. return retval;
  109. retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
  110. // XXX check retval
  111. /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
  112. retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
  113. if (retval != ERROR_OK)
  114. return retval;
  115. retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
  116. // XXX check retval
  117. retval = dap_run(swjdp);
  118. /* restore DCB_DCRDR - this needs to be in a seperate
  119. * transaction otherwise the emulated DCC channel breaks */
  120. if (retval == ERROR_OK)
  121. retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
  122. return retval;
  123. }
  124. static int cortex_m3_write_debug_halt_mask(struct target *target,
  125. uint32_t mask_on, uint32_t mask_off)
  126. {
  127. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  128. struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
  129. /* mask off status bits */
  130. cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
  131. /* create new register mask */
  132. cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
  133. return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
  134. }
  135. static int cortex_m3_clear_halt(struct target *target)
  136. {
  137. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  138. struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
  139. int retval;
  140. /* clear step if any */
  141. cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
  142. /* Read Debug Fault Status Register */
  143. retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
  144. if (retval != ERROR_OK)
  145. return retval;
  146. /* Clear Debug Fault Status */
  147. retval = mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
  148. if (retval != ERROR_OK)
  149. return retval;
  150. LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
  151. return ERROR_OK;
  152. }
  153. static int cortex_m3_single_step_core(struct target *target)
  154. {
  155. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  156. struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
  157. uint32_t dhcsr_save;
  158. int retval;
  159. /* backup dhcsr reg */
  160. dhcsr_save = cortex_m3->dcb_dhcsr;
  161. /* Mask interrupts before clearing halt, if done already. This avoids
  162. * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
  163. * HALT can put the core into an unknown state.
  164. */
  165. if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
  166. {
  167. retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
  168. DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
  169. if (retval != ERROR_OK)
  170. return retval;
  171. }
  172. retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
  173. DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
  174. if (retval != ERROR_OK)
  175. return retval;
  176. LOG_DEBUG(" ");
  177. /* restore dhcsr reg */
  178. cortex_m3->dcb_dhcsr = dhcsr_save;
  179. cortex_m3_clear_halt(target);
  180. return ERROR_OK;
  181. }
  182. static int cortex_m3_endreset_event(struct target *target)
  183. {
  184. int i;
  185. int retval;
  186. uint32_t dcb_demcr;
  187. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  188. struct armv7m_common *armv7m = &cortex_m3->armv7m;
  189. struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
  190. struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
  191. struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
  192. /* REVISIT The four debug monitor bits are currently ignored... */
  193. retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
  194. if (retval != ERROR_OK)
  195. return retval;
  196. LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
  197. /* this register is used for emulated dcc channel */
  198. retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
  199. if (retval != ERROR_OK)
  200. return retval;
  201. /* Enable debug requests */
  202. retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  203. if (retval != ERROR_OK)
  204. return retval;
  205. if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
  206. {
  207. retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
  208. if (retval != ERROR_OK)
  209. return retval;
  210. }
  211. /* clear any interrupt masking */
  212. cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
  213. /* Enable features controlled by ITM and DWT blocks, and catch only
  214. * the vectors we were told to pay attention to.
  215. *
  216. * Target firmware is responsible for all fault handling policy
  217. * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
  218. * or manual updates to the NVIC SHCSR and CCR registers.
  219. */
  220. retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
  221. if (retval != ERROR_OK)
  222. return retval;
  223. /* Paranoia: evidently some (early?) chips don't preserve all the
  224. * debug state (including FBP, DWT, etc) across reset...
  225. */
  226. /* Enable FPB */
  227. retval = target_write_u32(target, FP_CTRL, 3);
  228. if (retval != ERROR_OK)
  229. return retval;
  230. cortex_m3->fpb_enabled = 1;
  231. /* Restore FPB registers */
  232. for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
  233. {
  234. retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
  235. if (retval != ERROR_OK)
  236. return retval;
  237. }
  238. /* Restore DWT registers */
  239. for (i = 0; i < cortex_m3->dwt_num_comp; i++)
  240. {
  241. retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
  242. dwt_list[i].comp);
  243. if (retval != ERROR_OK)
  244. return retval;
  245. retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
  246. dwt_list[i].mask);
  247. if (retval != ERROR_OK)
  248. return retval;
  249. retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
  250. dwt_list[i].function);
  251. if (retval != ERROR_OK)
  252. return retval;
  253. }
  254. retval = dap_run(swjdp);
  255. if (retval != ERROR_OK)
  256. return retval;
  257. register_cache_invalidate(cortex_m3->armv7m.core_cache);
  258. /* make sure we have latest dhcsr flags */
  259. retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  260. return retval;
  261. }
  262. static int cortex_m3_examine_debug_reason(struct target *target)
  263. {
  264. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  265. /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
  266. /* only check the debug reason if we don't know it already */
  267. if ((target->debug_reason != DBG_REASON_DBGRQ)
  268. && (target->debug_reason != DBG_REASON_SINGLESTEP))
  269. {
  270. if (cortex_m3->nvic_dfsr & DFSR_BKPT)
  271. {
  272. target->debug_reason = DBG_REASON_BREAKPOINT;
  273. if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
  274. target->debug_reason = DBG_REASON_WPTANDBKPT;
  275. }
  276. else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
  277. target->debug_reason = DBG_REASON_WATCHPOINT;
  278. else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
  279. target->debug_reason = DBG_REASON_BREAKPOINT;
  280. else /* EXTERNAL, HALTED */
  281. target->debug_reason = DBG_REASON_UNDEFINED;
  282. }
  283. return ERROR_OK;
  284. }
  285. static int cortex_m3_examine_exception_reason(struct target *target)
  286. {
  287. uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
  288. struct armv7m_common *armv7m = target_to_armv7m(target);
  289. struct adiv5_dap *swjdp = &armv7m->dap;
  290. int retval;
  291. retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
  292. if (retval != ERROR_OK)
  293. return retval;
  294. switch (armv7m->exception_number)
  295. {
  296. case 2: /* NMI */
  297. break;
  298. case 3: /* Hard Fault */
  299. retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
  300. if (retval != ERROR_OK)
  301. return retval;
  302. if (except_sr & 0x40000000)
  303. {
  304. retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
  305. if (retval != ERROR_OK)
  306. return retval;
  307. }
  308. break;
  309. case 4: /* Memory Management */
  310. retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
  311. if (retval != ERROR_OK)
  312. return retval;
  313. retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
  314. if (retval != ERROR_OK)
  315. return retval;
  316. break;
  317. case 5: /* Bus Fault */
  318. retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
  319. if (retval != ERROR_OK)
  320. return retval;
  321. retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
  322. if (retval != ERROR_OK)
  323. return retval;
  324. break;
  325. case 6: /* Usage Fault */
  326. retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
  327. if (retval != ERROR_OK)
  328. return retval;
  329. break;
  330. case 11: /* SVCall */
  331. break;
  332. case 12: /* Debug Monitor */
  333. retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
  334. if (retval != ERROR_OK)
  335. return retval;
  336. break;
  337. case 14: /* PendSV */
  338. break;
  339. case 15: /* SysTick */
  340. break;
  341. default:
  342. except_sr = 0;
  343. break;
  344. }
  345. retval = dap_run(swjdp);
  346. if (retval == ERROR_OK)
  347. LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
  348. ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
  349. armv7m_exception_string(armv7m->exception_number),
  350. shcsr, except_sr, cfsr, except_ar);
  351. return retval;
  352. }
  353. /* PSP is used in some thread modes */
  354. static const int armv7m_psp_reg_map[17] = {
  355. ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
  356. ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
  357. ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
  358. ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
  359. ARMV7M_xPSR,
  360. };
  361. /* MSP is used in handler and some thread modes */
  362. static const int armv7m_msp_reg_map[17] = {
  363. ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
  364. ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
  365. ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
  366. ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
  367. ARMV7M_xPSR,
  368. };
  369. static int cortex_m3_debug_entry(struct target *target)
  370. {
  371. int i;
  372. uint32_t xPSR;
  373. int retval;
  374. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  375. struct armv7m_common *armv7m = &cortex_m3->armv7m;
  376. struct arm *arm = &armv7m->arm;
  377. struct adiv5_dap *swjdp = &armv7m->dap;
  378. struct reg *r;
  379. LOG_DEBUG(" ");
  380. cortex_m3_clear_halt(target);
  381. retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  382. if (retval != ERROR_OK)
  383. return retval;
  384. if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
  385. return retval;
  386. /* Examine target state and mode */
  387. /* First load register acessible through core debug port*/
  388. int num_regs = armv7m->core_cache->num_regs;
  389. for (i = 0; i < num_regs; i++)
  390. {
  391. if (!armv7m->core_cache->reg_list[i].valid)
  392. armv7m->read_core_reg(target, i);
  393. }
  394. r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
  395. xPSR = buf_get_u32(r->value, 0, 32);
  396. #ifdef ARMV7_GDB_HACKS
  397. /* FIXME this breaks on scan chains with more than one Cortex-M3.
  398. * Instead, each CM3 should have its own dummy value...
  399. */
  400. /* copy real xpsr reg for gdb, setting thumb bit */
  401. buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
  402. buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
  403. armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
  404. armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
  405. #endif
  406. /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
  407. if (xPSR & 0xf00)
  408. {
  409. r->dirty = r->valid;
  410. cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
  411. }
  412. /* Are we in an exception handler */
  413. if (xPSR & 0x1FF)
  414. {
  415. armv7m->core_mode = ARMV7M_MODE_HANDLER;
  416. armv7m->exception_number = (xPSR & 0x1FF);
  417. arm->core_mode = ARM_MODE_HANDLER;
  418. arm->map = armv7m_msp_reg_map;
  419. }
  420. else
  421. {
  422. unsigned control = buf_get_u32(armv7m->core_cache
  423. ->reg_list[ARMV7M_CONTROL].value, 0, 2);
  424. /* is this thread privileged? */
  425. armv7m->core_mode = control & 1;
  426. arm->core_mode = armv7m->core_mode
  427. ? ARM_MODE_USER_THREAD
  428. : ARM_MODE_THREAD;
  429. /* which stack is it using? */
  430. if (control & 2)
  431. arm->map = armv7m_psp_reg_map;
  432. else
  433. arm->map = armv7m_msp_reg_map;
  434. armv7m->exception_number = 0;
  435. }
  436. if (armv7m->exception_number)
  437. {
  438. cortex_m3_examine_exception_reason(target);
  439. }
  440. LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
  441. armv7m_mode_strings[armv7m->core_mode],
  442. *(uint32_t*)(arm->pc->value),
  443. target_state_name(target));
  444. if (armv7m->post_debug_entry)
  445. {
  446. retval = armv7m->post_debug_entry(target);
  447. if (retval != ERROR_OK)
  448. return retval;
  449. }
  450. return ERROR_OK;
  451. }
  452. static int cortex_m3_poll(struct target *target)
  453. {
  454. int detected_failure = ERROR_OK;
  455. int retval = ERROR_OK;
  456. enum target_state prev_target_state = target->state;
  457. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  458. struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
  459. /* Read from Debug Halting Control and Status Register */
  460. retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  461. if (retval != ERROR_OK)
  462. {
  463. target->state = TARGET_UNKNOWN;
  464. return retval;
  465. }
  466. /* Recover from lockup. See ARMv7-M architecture spec,
  467. * section B1.5.15 "Unrecoverable exception cases".
  468. */
  469. if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
  470. LOG_ERROR("%s -- clearing lockup after double fault",
  471. target_name(target));
  472. cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
  473. target->debug_reason = DBG_REASON_DBGRQ;
  474. /* We have to execute the rest (the "finally" equivalent, but
  475. * still throw this exception again).
  476. */
  477. detected_failure = ERROR_FAIL;
  478. /* refresh status bits */
  479. retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  480. if (retval != ERROR_OK)
  481. return retval;
  482. }
  483. if (cortex_m3->dcb_dhcsr & S_RESET_ST)
  484. {
  485. /* check if still in reset */
  486. retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  487. if (retval != ERROR_OK)
  488. return retval;
  489. if (cortex_m3->dcb_dhcsr & S_RESET_ST)
  490. {
  491. target->state = TARGET_RESET;
  492. return ERROR_OK;
  493. }
  494. }
  495. if (target->state == TARGET_RESET)
  496. {
  497. /* Cannot switch context while running so endreset is
  498. * called with target->state == TARGET_RESET
  499. */
  500. LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
  501. cortex_m3->dcb_dhcsr);
  502. cortex_m3_endreset_event(target);
  503. target->state = TARGET_RUNNING;
  504. prev_target_state = TARGET_RUNNING;
  505. }
  506. if (cortex_m3->dcb_dhcsr & S_HALT)
  507. {
  508. target->state = TARGET_HALTED;
  509. if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
  510. {
  511. if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
  512. return retval;
  513. if (arm_semihosting(target, &retval) != 0)
  514. return retval;
  515. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  516. }
  517. if (prev_target_state == TARGET_DEBUG_RUNNING)
  518. {
  519. LOG_DEBUG(" ");
  520. if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
  521. return retval;
  522. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
  523. }
  524. }
  525. /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
  526. * How best to model low power modes?
  527. */
  528. if (target->state == TARGET_UNKNOWN)
  529. {
  530. /* check if processor is retiring instructions */
  531. if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
  532. {
  533. target->state = TARGET_RUNNING;
  534. retval = ERROR_OK;
  535. }
  536. }
  537. /* Did we detect a failure condition that we cleared? */
  538. if (detected_failure != ERROR_OK)
  539. retval = detected_failure;
  540. return retval;
  541. }
  542. static int cortex_m3_halt(struct target *target)
  543. {
  544. LOG_DEBUG("target->state: %s",
  545. target_state_name(target));
  546. if (target->state == TARGET_HALTED)
  547. {
  548. LOG_DEBUG("target was already halted");
  549. return ERROR_OK;
  550. }
  551. if (target->state == TARGET_UNKNOWN)
  552. {
  553. LOG_WARNING("target was in unknown state when halt was requested");
  554. }
  555. if (target->state == TARGET_RESET)
  556. {
  557. if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
  558. {
  559. LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
  560. return ERROR_TARGET_FAILURE;
  561. }
  562. else
  563. {
  564. /* we came here in a reset_halt or reset_init sequence
  565. * debug entry was already prepared in cortex_m3_prepare_reset_halt()
  566. */
  567. target->debug_reason = DBG_REASON_DBGRQ;
  568. return ERROR_OK;
  569. }
  570. }
  571. /* Write to Debug Halting Control and Status Register */
  572. cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
  573. target->debug_reason = DBG_REASON_DBGRQ;
  574. return ERROR_OK;
  575. }
  576. static int cortex_m3_soft_reset_halt(struct target *target)
  577. {
  578. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  579. struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
  580. uint32_t dcb_dhcsr = 0;
  581. int retval, timeout = 0;
  582. /* Enter debug state on reset; restore DEMCR in endreset_event() */
  583. retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
  584. TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
  585. if (retval != ERROR_OK)
  586. return retval;
  587. /* Request a core-only reset */
  588. retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
  589. AIRCR_VECTKEY | AIRCR_VECTRESET);
  590. if (retval != ERROR_OK)
  591. return retval;
  592. target->state = TARGET_RESET;
  593. /* registers are now invalid */
  594. register_cache_invalidate(cortex_m3->armv7m.core_cache);
  595. while (timeout < 100)
  596. {
  597. retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
  598. if (retval == ERROR_OK)
  599. {
  600. retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
  601. &cortex_m3->nvic_dfsr);
  602. if (retval != ERROR_OK)
  603. return retval;
  604. if ((dcb_dhcsr & S_HALT)
  605. && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
  606. {
  607. LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
  608. "DFSR 0x%08x",
  609. (unsigned) dcb_dhcsr,
  610. (unsigned) cortex_m3->nvic_dfsr);
  611. cortex_m3_poll(target);
  612. /* FIXME restore user's vector catch config */
  613. return ERROR_OK;
  614. }
  615. else
  616. LOG_DEBUG("waiting for system reset-halt, "
  617. "DHCSR 0x%08x, %d ms",
  618. (unsigned) dcb_dhcsr, timeout);
  619. }
  620. timeout++;
  621. alive_sleep(1);
  622. }
  623. return ERROR_OK;
  624. }
  625. static void cortex_m3_enable_breakpoints(struct target *target)
  626. {
  627. struct breakpoint *breakpoint = target->breakpoints;
  628. /* set any pending breakpoints */
  629. while (breakpoint)
  630. {
  631. if (!breakpoint->set)
  632. cortex_m3_set_breakpoint(target, breakpoint);
  633. breakpoint = breakpoint->next;
  634. }
  635. }
  636. static int cortex_m3_resume(struct target *target, int current,
  637. uint32_t address, int handle_breakpoints, int debug_execution)
  638. {
  639. struct armv7m_common *armv7m = target_to_armv7m(target);
  640. struct breakpoint *breakpoint = NULL;
  641. uint32_t resume_pc;
  642. struct reg *r;
  643. if (target->state != TARGET_HALTED)
  644. {
  645. LOG_WARNING("target not halted");
  646. return ERROR_TARGET_NOT_HALTED;
  647. }
  648. if (!debug_execution)
  649. {
  650. target_free_all_working_areas(target);
  651. cortex_m3_enable_breakpoints(target);
  652. cortex_m3_enable_watchpoints(target);
  653. }
  654. if (debug_execution)
  655. {
  656. r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
  657. /* Disable interrupts */
  658. /* We disable interrupts in the PRIMASK register instead of
  659. * masking with C_MASKINTS. This is probably the same issue
  660. * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
  661. * in parallel with disabled interrupts can cause local faults
  662. * to not be taken.
  663. *
  664. * REVISIT this clearly breaks non-debug execution, since the
  665. * PRIMASK register state isn't saved/restored... workaround
  666. * by never resuming app code after debug execution.
  667. */
  668. buf_set_u32(r->value, 0, 1, 1);
  669. r->dirty = true;
  670. r->valid = true;
  671. /* Make sure we are in Thumb mode */
  672. r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
  673. buf_set_u32(r->value, 24, 1, 1);
  674. r->dirty = true;
  675. r->valid = true;
  676. }
  677. /* current = 1: continue on current pc, otherwise continue at <address> */
  678. r = armv7m->arm.pc;
  679. if (!current)
  680. {
  681. buf_set_u32(r->value, 0, 32, address);
  682. r->dirty = true;
  683. r->valid = true;
  684. }
  685. /* if we halted last time due to a bkpt instruction
  686. * then we have to manually step over it, otherwise
  687. * the core will break again */
  688. if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
  689. && !debug_execution)
  690. {
  691. armv7m_maybe_skip_bkpt_inst(target, NULL);
  692. }
  693. resume_pc = buf_get_u32(r->value, 0, 32);
  694. armv7m_restore_context(target);
  695. /* the front-end may request us not to handle breakpoints */
  696. if (handle_breakpoints)
  697. {
  698. /* Single step past breakpoint at current address */
  699. if ((breakpoint = breakpoint_find(target, resume_pc)))
  700. {
  701. LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
  702. breakpoint->address,
  703. breakpoint->unique_id);
  704. cortex_m3_unset_breakpoint(target, breakpoint);
  705. cortex_m3_single_step_core(target);
  706. cortex_m3_set_breakpoint(target, breakpoint);
  707. }
  708. }
  709. /* Restart core */
  710. cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
  711. target->debug_reason = DBG_REASON_NOTHALTED;
  712. /* registers are now invalid */
  713. register_cache_invalidate(armv7m->core_cache);
  714. if (!debug_execution)
  715. {
  716. target->state = TARGET_RUNNING;
  717. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  718. LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
  719. }
  720. else
  721. {
  722. target->state = TARGET_DEBUG_RUNNING;
  723. target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
  724. LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
  725. }
  726. return ERROR_OK;
  727. }
  728. /* int irqstepcount = 0; */
  729. static int cortex_m3_step(struct target *target, int current,
  730. uint32_t address, int handle_breakpoints)
  731. {
  732. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  733. struct armv7m_common *armv7m = &cortex_m3->armv7m;
  734. struct adiv5_dap *swjdp = &armv7m->dap;
  735. struct breakpoint *breakpoint = NULL;
  736. struct reg *pc = armv7m->arm.pc;
  737. bool bkpt_inst_found = false;
  738. int retval;
  739. bool isr_timed_out = false;
  740. if (target->state != TARGET_HALTED)
  741. {
  742. LOG_WARNING("target not halted");
  743. return ERROR_TARGET_NOT_HALTED;
  744. }
  745. /* current = 1: continue on current pc, otherwise continue at <address> */
  746. if (!current)
  747. buf_set_u32(pc->value, 0, 32, address);
  748. uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
  749. /* the front-end may request us not to handle breakpoints */
  750. if (handle_breakpoints) {
  751. breakpoint = breakpoint_find(target, pc_value);
  752. if (breakpoint)
  753. cortex_m3_unset_breakpoint(target, breakpoint);
  754. }
  755. armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
  756. target->debug_reason = DBG_REASON_SINGLESTEP;
  757. armv7m_restore_context(target);
  758. target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
  759. /* if no bkpt instruction is found at pc then we can perform
  760. * a normal step, otherwise we have to manually step over the bkpt
  761. * instruction - as such simulate a step */
  762. if (bkpt_inst_found == false)
  763. {
  764. /* Automatic ISR masking mode off: Just step over the next instruction */
  765. if ((cortex_m3->isrmasking_mode != CORTEX_M3_ISRMASK_AUTO))
  766. {
  767. cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
  768. }
  769. else
  770. {
  771. /* Process interrupts during stepping in a way they don't interfere
  772. * debugging.
  773. *
  774. * Principle:
  775. *
  776. * Set a temporary break point at the current pc and let the core run
  777. * with interrupts enabled. Pending interrupts get served and we run
  778. * into the breakpoint again afterwards. Then we step over the next
  779. * instruction with interrupts disabled.
  780. *
  781. * If the pending interrupts don't complete within time, we leave the
  782. * core running. This may happen if the interrupts trigger faster
  783. * than the core can process them or the handler doesn't return.
  784. *
  785. * If no more breakpoints are available we simply do a step with
  786. * interrupts enabled.
  787. *
  788. */
  789. /* Set a temporary break point */
  790. retval = breakpoint_add(target, pc_value , 2, BKPT_TYPE_BY_ADDR(pc_value));
  791. bool tmp_bp_set = (retval == ERROR_OK);
  792. /* No more breakpoints left, just do a step */
  793. if (!tmp_bp_set)
  794. {
  795. cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
  796. }
  797. else
  798. {
  799. /* Start the core */
  800. LOG_DEBUG("Starting core to serve pending interrupts");
  801. int64_t t_start = timeval_ms();
  802. cortex_m3_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
  803. /* Wait for pending handlers to complete or timeout */
  804. do {
  805. retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  806. if (retval != ERROR_OK)
  807. {
  808. target->state = TARGET_UNKNOWN;
  809. return retval;
  810. }
  811. isr_timed_out = ((timeval_ms() - t_start) > 500);
  812. } while (!((cortex_m3->dcb_dhcsr & S_HALT) || isr_timed_out));
  813. /* Remove the temporary breakpoint */
  814. breakpoint_remove(target, pc_value);
  815. if (isr_timed_out)
  816. {
  817. LOG_DEBUG("Interrupt handlers didn't complete within time, "
  818. "leaving target running");
  819. }
  820. else
  821. {
  822. /* Step over next instruction with interrupts disabled */
  823. cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
  824. cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
  825. /* Re-enable interrupts */
  826. cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
  827. }
  828. }
  829. }
  830. }
  831. retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  832. if (retval != ERROR_OK)
  833. return retval;
  834. /* registers are now invalid */
  835. register_cache_invalidate(cortex_m3->armv7m.core_cache);
  836. if (breakpoint)
  837. cortex_m3_set_breakpoint(target, breakpoint);
  838. if (isr_timed_out) {
  839. /* Leave the core running. The user has to stop execution manually. */
  840. target->debug_reason = DBG_REASON_NOTHALTED;
  841. target->state = TARGET_RUNNING;
  842. return ERROR_OK;
  843. }
  844. LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
  845. " nvic_icsr = 0x%" PRIx32,
  846. cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
  847. retval = cortex_m3_debug_entry(target);
  848. if (retval != ERROR_OK)
  849. return retval;
  850. target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  851. LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
  852. " nvic_icsr = 0x%" PRIx32,
  853. cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
  854. return ERROR_OK;
  855. }
  856. static int cortex_m3_assert_reset(struct target *target)
  857. {
  858. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  859. struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
  860. enum cortex_m3_soft_reset_config reset_config = cortex_m3->soft_reset_config;
  861. LOG_DEBUG("target->state: %s",
  862. target_state_name(target));
  863. enum reset_types jtag_reset_config = jtag_get_reset_config();
  864. if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
  865. /* allow scripts to override the reset event */
  866. target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
  867. register_cache_invalidate(cortex_m3->armv7m.core_cache);
  868. target->state = TARGET_RESET;
  869. return ERROR_OK;
  870. }
  871. /* Enable debug requests */
  872. int retval;
  873. retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
  874. if (retval != ERROR_OK)
  875. return retval;
  876. if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
  877. {
  878. retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
  879. if (retval != ERROR_OK)
  880. return retval;
  881. }
  882. retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
  883. if (retval != ERROR_OK)
  884. return retval;
  885. if (!target->reset_halt)
  886. {
  887. /* Set/Clear C_MASKINTS in a separate operation */
  888. if (cortex_m3->dcb_dhcsr & C_MASKINTS)
  889. {
  890. retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
  891. DBGKEY | C_DEBUGEN | C_HALT);
  892. if (retval != ERROR_OK)
  893. return retval;
  894. }
  895. /* clear any debug flags before resuming */
  896. cortex_m3_clear_halt(target);
  897. /* clear C_HALT in dhcsr reg */
  898. cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
  899. }
  900. else
  901. {
  902. /* Halt in debug on reset; endreset_event() restores DEMCR.
  903. *
  904. * REVISIT catching BUSERR presumably helps to defend against
  905. * bad vector table entries. Should this include MMERR or
  906. * other flags too?
  907. */
  908. retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
  909. TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
  910. if (retval != ERROR_OK)
  911. return retval;
  912. }
  913. if (jtag_reset_config & RESET_HAS_SRST)
  914. {
  915. /* default to asserting srst */
  916. if (jtag_reset_config & RESET_SRST_PULLS_TRST)
  917. {
  918. jtag_add_reset(1, 1);
  919. }
  920. else
  921. {
  922. jtag_add_reset(0, 1);
  923. }
  924. }
  925. else
  926. {
  927. /* Use a standard Cortex-M3 software reset mechanism.
  928. * We default to using VECRESET as it is supported on all current cores.
  929. * This has the disadvantage of not resetting the peripherals, so a
  930. * reset-init event handler is needed to perform any peripheral resets.
  931. */
  932. retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
  933. AIRCR_VECTKEY | ((reset_config == CORTEX_M3_RESET_SYSRESETREQ)
  934. ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
  935. if (retval != ERROR_OK)
  936. return retval;
  937. LOG_DEBUG("Using Cortex-M3 %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ)
  938. ? "SYSRESETREQ" : "VECTRESET");
  939. if (reset_config == CORTEX_M3_RESET_VECTRESET) {
  940. LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
  941. "handler to reset any peripherals");
  942. }
  943. {
  944. /* I do not know why this is necessary, but it
  945. * fixes strange effects (step/resume cause NMI
  946. * after reset) on LM3S6918 -- Michael Schwingen
  947. */
  948. uint32_t tmp;
  949. retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
  950. if (retval != ERROR_OK)
  951. return retval;
  952. }
  953. }
  954. target->state = TARGET_RESET;
  955. jtag_add_sleep(50000);
  956. register_cache_invalidate(cortex_m3->armv7m.core_cache);
  957. if (target->reset_halt)
  958. {
  959. if ((retval = target_halt(target)) != ERROR_OK)
  960. return retval;
  961. }
  962. return ERROR_OK;
  963. }
  964. static int cortex_m3_deassert_reset(struct target *target)
  965. {
  966. LOG_DEBUG("target->state: %s",
  967. target_state_name(target));
  968. /* deassert reset lines */
  969. jtag_add_reset(0, 0);
  970. return ERROR_OK;
  971. }
  972. static int
  973. cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
  974. {
  975. int retval;
  976. int fp_num = 0;
  977. uint32_t hilo;
  978. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  979. struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
  980. if (breakpoint->set)
  981. {
  982. LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
  983. return ERROR_OK;
  984. }
  985. if (cortex_m3->auto_bp_type)
  986. {
  987. breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
  988. }
  989. if (breakpoint->type == BKPT_HARD)
  990. {
  991. while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
  992. fp_num++;
  993. if (fp_num >= cortex_m3->fp_num_code)
  994. {
  995. LOG_ERROR("Can not find free FPB Comparator!");
  996. return ERROR_FAIL;
  997. }
  998. breakpoint->set = fp_num + 1;
  999. hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
  1000. comparator_list[fp_num].used = 1;
  1001. comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
  1002. target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
  1003. LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
  1004. if (!cortex_m3->fpb_enabled)
  1005. {
  1006. LOG_DEBUG("FPB wasn't enabled, do it now");
  1007. target_write_u32(target, FP_CTRL, 3);
  1008. }
  1009. }
  1010. else if (breakpoint->type == BKPT_SOFT)
  1011. {
  1012. uint8_t code[4];
  1013. /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
  1014. * semihosting; don't use that. Otherwise the BKPT
  1015. * parameter is arbitrary.
  1016. */
  1017. buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
  1018. retval = target_read_memory(target,
  1019. breakpoint->address & 0xFFFFFFFE,
  1020. breakpoint->length, 1,
  1021. breakpoint->orig_instr);
  1022. if (retval != ERROR_OK)
  1023. return retval;
  1024. retval = target_write_memory(target,
  1025. breakpoint->address & 0xFFFFFFFE,
  1026. breakpoint->length, 1,
  1027. code);
  1028. if (retval != ERROR_OK)
  1029. return retval;
  1030. breakpoint->set = true;
  1031. }
  1032. LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
  1033. breakpoint->unique_id,
  1034. (int)(breakpoint->type),
  1035. breakpoint->address,
  1036. breakpoint->length,
  1037. breakpoint->set);
  1038. return ERROR_OK;
  1039. }
  1040. static int
  1041. cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
  1042. {
  1043. int retval;
  1044. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  1045. struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
  1046. if (!breakpoint->set)
  1047. {
  1048. LOG_WARNING("breakpoint not set");
  1049. return ERROR_OK;
  1050. }
  1051. LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
  1052. breakpoint->unique_id,
  1053. (int)(breakpoint->type),
  1054. breakpoint->address,
  1055. breakpoint->length,
  1056. breakpoint->set);
  1057. if (breakpoint->type == BKPT_HARD)
  1058. {
  1059. int fp_num = breakpoint->set - 1;
  1060. if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
  1061. {
  1062. LOG_DEBUG("Invalid FP Comparator number in breakpoint");
  1063. return ERROR_OK;
  1064. }
  1065. comparator_list[fp_num].used = 0;
  1066. comparator_list[fp_num].fpcr_value = 0;
  1067. target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
  1068. }
  1069. else
  1070. {
  1071. /* restore original instruction (kept in target endianness) */
  1072. if (breakpoint->length == 4)
  1073. {
  1074. if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
  1075. {
  1076. return retval;
  1077. }
  1078. }
  1079. else
  1080. {
  1081. if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
  1082. {
  1083. return retval;
  1084. }
  1085. }
  1086. }
  1087. breakpoint->set = false;
  1088. return ERROR_OK;
  1089. }
  1090. static int
  1091. cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
  1092. {
  1093. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  1094. if (cortex_m3->auto_bp_type)
  1095. {
  1096. breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
  1097. #ifdef ARMV7_GDB_HACKS
  1098. if (breakpoint->length != 2) {
  1099. /* XXX Hack: Replace all breakpoints with length != 2 with
  1100. * a hardware breakpoint. */
  1101. breakpoint->type = BKPT_HARD;
  1102. breakpoint->length = 2;
  1103. }
  1104. #endif
  1105. }
  1106. if(breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
  1107. if (breakpoint->type == BKPT_HARD)
  1108. {
  1109. LOG_INFO("flash patch comparator requested outside code memory region");
  1110. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1111. }
  1112. if (breakpoint->type == BKPT_SOFT)
  1113. {
  1114. LOG_INFO("soft breakpoint requested in code (flash) memory region");
  1115. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1116. }
  1117. }
  1118. if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
  1119. {
  1120. LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
  1121. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1122. }
  1123. if ((breakpoint->length != 2))
  1124. {
  1125. LOG_INFO("only breakpoints of two bytes length supported");
  1126. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1127. }
  1128. if (breakpoint->type == BKPT_HARD)
  1129. cortex_m3->fp_code_available--;
  1130. return cortex_m3_set_breakpoint(target, breakpoint);
  1131. }
  1132. static int
  1133. cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
  1134. {
  1135. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  1136. /* REVISIT why check? FBP can be updated with core running ... */
  1137. if (target->state != TARGET_HALTED)
  1138. {
  1139. LOG_WARNING("target not halted");
  1140. return ERROR_TARGET_NOT_HALTED;
  1141. }
  1142. if (cortex_m3->auto_bp_type)
  1143. {
  1144. breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
  1145. }
  1146. if (breakpoint->set)
  1147. {
  1148. cortex_m3_unset_breakpoint(target, breakpoint);
  1149. }
  1150. if (breakpoint->type == BKPT_HARD)
  1151. cortex_m3->fp_code_available++;
  1152. return ERROR_OK;
  1153. }
  1154. static int
  1155. cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
  1156. {
  1157. int dwt_num = 0;
  1158. uint32_t mask, temp;
  1159. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  1160. /* watchpoint params were validated earlier */
  1161. mask = 0;
  1162. temp = watchpoint->length;
  1163. while (temp) {
  1164. temp >>= 1;
  1165. mask++;
  1166. }
  1167. mask--;
  1168. /* REVISIT Don't fully trust these "not used" records ... users
  1169. * may set up breakpoints by hand, e.g. dual-address data value
  1170. * watchpoint using comparator #1; comparator #0 matching cycle
  1171. * count; send data trace info through ITM and TPIU; etc
  1172. */
  1173. struct cortex_m3_dwt_comparator *comparator;
  1174. for (comparator = cortex_m3->dwt_comparator_list;
  1175. comparator->used && dwt_num < cortex_m3->dwt_num_comp;
  1176. comparator++, dwt_num++)
  1177. continue;
  1178. if (dwt_num >= cortex_m3->dwt_num_comp)
  1179. {
  1180. LOG_ERROR("Can not find free DWT Comparator");
  1181. return ERROR_FAIL;
  1182. }
  1183. comparator->used = 1;
  1184. watchpoint->set = dwt_num + 1;
  1185. comparator->comp = watchpoint->address;
  1186. target_write_u32(target, comparator->dwt_comparator_address + 0,
  1187. comparator->comp);
  1188. comparator->mask = mask;
  1189. target_write_u32(target, comparator->dwt_comparator_address + 4,
  1190. comparator->mask);
  1191. switch (watchpoint->rw) {
  1192. case WPT_READ:
  1193. comparator->function = 5;
  1194. break;
  1195. case WPT_WRITE:
  1196. comparator->function = 6;
  1197. break;
  1198. case WPT_ACCESS:
  1199. comparator->function = 7;
  1200. break;
  1201. }
  1202. target_write_u32(target, comparator->dwt_comparator_address + 8,
  1203. comparator->function);
  1204. LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
  1205. watchpoint->unique_id, dwt_num,
  1206. (unsigned) comparator->comp,
  1207. (unsigned) comparator->mask,
  1208. (unsigned) comparator->function);
  1209. return ERROR_OK;
  1210. }
  1211. static int
  1212. cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
  1213. {
  1214. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  1215. struct cortex_m3_dwt_comparator *comparator;
  1216. int dwt_num;
  1217. if (!watchpoint->set)
  1218. {
  1219. LOG_WARNING("watchpoint (wpid: %d) not set",
  1220. watchpoint->unique_id);
  1221. return ERROR_OK;
  1222. }
  1223. dwt_num = watchpoint->set - 1;
  1224. LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
  1225. watchpoint->unique_id, dwt_num,
  1226. (unsigned) watchpoint->address);
  1227. if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
  1228. {
  1229. LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
  1230. return ERROR_OK;
  1231. }
  1232. comparator = cortex_m3->dwt_comparator_list + dwt_num;
  1233. comparator->used = 0;
  1234. comparator->function = 0;
  1235. target_write_u32(target, comparator->dwt_comparator_address + 8,
  1236. comparator->function);
  1237. watchpoint->set = false;
  1238. return ERROR_OK;
  1239. }
  1240. static int
  1241. cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
  1242. {
  1243. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  1244. if (cortex_m3->dwt_comp_available < 1)
  1245. {
  1246. LOG_DEBUG("no comparators?");
  1247. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1248. }
  1249. /* hardware doesn't support data value masking */
  1250. if (watchpoint->mask != ~(uint32_t)0) {
  1251. LOG_DEBUG("watchpoint value masks not supported");
  1252. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1253. }
  1254. /* hardware allows address masks of up to 32K */
  1255. unsigned mask;
  1256. for (mask = 0; mask < 16; mask++) {
  1257. if ((1u << mask) == watchpoint->length)
  1258. break;
  1259. }
  1260. if (mask == 16) {
  1261. LOG_DEBUG("unsupported watchpoint length");
  1262. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1263. }
  1264. if (watchpoint->address & ((1 << mask) - 1)) {
  1265. LOG_DEBUG("watchpoint address is unaligned");
  1266. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1267. }
  1268. /* Caller doesn't seem to be able to describe watching for data
  1269. * values of zero; that flags "no value".
  1270. *
  1271. * REVISIT This DWT may well be able to watch for specific data
  1272. * values. Requires comparator #1 to set DATAVMATCH and match
  1273. * the data, and another comparator (DATAVADDR0) matching addr.
  1274. */
  1275. if (watchpoint->value) {
  1276. LOG_DEBUG("data value watchpoint not YET supported");
  1277. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  1278. }
  1279. cortex_m3->dwt_comp_available--;
  1280. LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
  1281. return ERROR_OK;
  1282. }
  1283. static int
  1284. cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
  1285. {
  1286. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  1287. /* REVISIT why check? DWT can be updated with core running ... */
  1288. if (target->state != TARGET_HALTED)
  1289. {
  1290. LOG_WARNING("target not halted");
  1291. return ERROR_TARGET_NOT_HALTED;
  1292. }
  1293. if (watchpoint->set)
  1294. {
  1295. cortex_m3_unset_watchpoint(target, watchpoint);
  1296. }
  1297. cortex_m3->dwt_comp_available++;
  1298. LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
  1299. return ERROR_OK;
  1300. }
  1301. static void cortex_m3_enable_watchpoints(struct target *target)
  1302. {
  1303. struct watchpoint *watchpoint = target->watchpoints;
  1304. /* set any pending watchpoints */
  1305. while (watchpoint)
  1306. {
  1307. if (!watchpoint->set)
  1308. cortex_m3_set_watchpoint(target, watchpoint);
  1309. watchpoint = watchpoint->next;
  1310. }
  1311. }
  1312. static int cortex_m3_load_core_reg_u32(struct target *target,
  1313. enum armv7m_regtype type, uint32_t num, uint32_t * value)
  1314. {
  1315. int retval;
  1316. struct armv7m_common *armv7m = target_to_armv7m(target);
  1317. struct adiv5_dap *swjdp = &armv7m->dap;
  1318. /* NOTE: we "know" here that the register identifiers used
  1319. * in the v7m header match the Cortex-M3 Debug Core Register
  1320. * Selector values for R0..R15, xPSR, MSP, and PSP.
  1321. */
  1322. switch (num) {
  1323. case 0 ... 18:
  1324. /* read a normal core register */
  1325. retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
  1326. if (retval != ERROR_OK)
  1327. {
  1328. LOG_ERROR("JTAG failure %i",retval);
  1329. return ERROR_JTAG_DEVICE_ERROR;
  1330. }
  1331. LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value);
  1332. break;
  1333. case ARMV7M_PRIMASK:
  1334. case ARMV7M_BASEPRI:
  1335. case ARMV7M_FAULTMASK:
  1336. case ARMV7M_CONTROL:
  1337. /* Cortex-M3 packages these four registers as bitfields
  1338. * in one Debug Core register. So say r0 and r2 docs;
  1339. * it was removed from r1 docs, but still works.
  1340. */
  1341. cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
  1342. switch (num)
  1343. {
  1344. case ARMV7M_PRIMASK:
  1345. *value = buf_get_u32((uint8_t*)value, 0, 1);
  1346. break;
  1347. case ARMV7M_BASEPRI:
  1348. *value = buf_get_u32((uint8_t*)value, 8, 8);
  1349. break;
  1350. case ARMV7M_FAULTMASK:
  1351. *value = buf_get_u32((uint8_t*)value, 16, 1);
  1352. break;
  1353. case ARMV7M_CONTROL:
  1354. *value = buf_get_u32((uint8_t*)value, 24, 2);
  1355. break;
  1356. }
  1357. LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
  1358. break;
  1359. default:
  1360. return ERROR_INVALID_ARGUMENTS;
  1361. }
  1362. return ERROR_OK;
  1363. }
  1364. static int cortex_m3_store_core_reg_u32(struct target *target,
  1365. enum armv7m_regtype type, uint32_t num, uint32_t value)
  1366. {
  1367. int retval;
  1368. uint32_t reg;
  1369. struct armv7m_common *armv7m = target_to_armv7m(target);
  1370. struct adiv5_dap *swjdp = &armv7m->dap;
  1371. #ifdef ARMV7_GDB_HACKS
  1372. /* If the LR register is being modified, make sure it will put us
  1373. * in "thumb" mode, or an INVSTATE exception will occur. This is a
  1374. * hack to deal with the fact that gdb will sometimes "forge"
  1375. * return addresses, and doesn't set the LSB correctly (i.e., when
  1376. * printing expressions containing function calls, it sets LR = 0.)
  1377. * Valid exception return codes have bit 0 set too.
  1378. */
  1379. if (num == ARMV7M_R14)
  1380. value |= 0x01;
  1381. #endif
  1382. /* NOTE: we "know" here that the register identifiers used
  1383. * in the v7m header match the Cortex-M3 Debug Core Register
  1384. * Selector values for R0..R15, xPSR, MSP, and PSP.
  1385. */
  1386. switch (num) {
  1387. case 0 ... 18:
  1388. retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
  1389. if (retval != ERROR_OK)
  1390. {
  1391. struct reg *r;
  1392. LOG_ERROR("JTAG failure");
  1393. r = armv7m->core_cache->reg_list + num;
  1394. r->dirty = r->valid;
  1395. return ERROR_JTAG_DEVICE_ERROR;
  1396. }
  1397. LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
  1398. break;
  1399. case ARMV7M_PRIMASK:
  1400. case ARMV7M_BASEPRI:
  1401. case ARMV7M_FAULTMASK:
  1402. case ARMV7M_CONTROL:
  1403. /* Cortex-M3 packages these four registers as bitfields
  1404. * in one Debug Core register. So say r0 and r2 docs;
  1405. * it was removed from r1 docs, but still works.
  1406. */
  1407. cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
  1408. switch (num)
  1409. {
  1410. case ARMV7M_PRIMASK:
  1411. buf_set_u32((uint8_t*)&reg, 0, 1, value);
  1412. break;
  1413. case ARMV7M_BASEPRI:
  1414. buf_set_u32((uint8_t*)&reg, 8, 8, value);
  1415. break;
  1416. case ARMV7M_FAULTMASK:
  1417. buf_set_u32((uint8_t*)&reg, 16, 1, value);
  1418. break;
  1419. case ARMV7M_CONTROL:
  1420. buf_set_u32((uint8_t*)&reg, 24, 2, value);
  1421. break;
  1422. }
  1423. cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
  1424. LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
  1425. break;
  1426. default:
  1427. return ERROR_INVALID_ARGUMENTS;
  1428. }
  1429. return ERROR_OK;
  1430. }
  1431. static int cortex_m3_read_memory(struct target *target, uint32_t address,
  1432. uint32_t size, uint32_t count, uint8_t *buffer)
  1433. {
  1434. struct armv7m_common *armv7m = target_to_armv7m(target);
  1435. struct adiv5_dap *swjdp = &armv7m->dap;
  1436. int retval = ERROR_INVALID_ARGUMENTS;
  1437. /* cortex_m3 handles unaligned memory access */
  1438. if (count && buffer) {
  1439. switch (size) {
  1440. case 4:
  1441. retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
  1442. break;
  1443. case 2:
  1444. retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
  1445. break;
  1446. case 1:
  1447. retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
  1448. break;
  1449. }
  1450. }
  1451. return retval;
  1452. }
  1453. static int cortex_m3_write_memory(struct target *target, uint32_t address,
  1454. uint32_t size, uint32_t count, const uint8_t *buffer)
  1455. {
  1456. struct armv7m_common *armv7m = target_to_armv7m(target);
  1457. struct adiv5_dap *swjdp = &armv7m->dap;
  1458. int retval = ERROR_INVALID_ARGUMENTS;
  1459. if (count && buffer) {
  1460. switch (size) {
  1461. case 4:
  1462. retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
  1463. break;
  1464. case 2:
  1465. retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
  1466. break;
  1467. case 1:
  1468. retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
  1469. break;
  1470. }
  1471. }
  1472. return retval;
  1473. }
  1474. static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
  1475. uint32_t count, const uint8_t *buffer)
  1476. {
  1477. return cortex_m3_write_memory(target, address, 4, count, buffer);
  1478. }
  1479. static int cortex_m3_init_target(struct command_context *cmd_ctx,
  1480. struct target *target)
  1481. {
  1482. armv7m_build_reg_cache(target);
  1483. return ERROR_OK;
  1484. }
  1485. /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
  1486. * on r/w if the core is not running, and clear on resume or reset ... or
  1487. * at least, in a post_restore_context() method.
  1488. */
  1489. struct dwt_reg_state {
  1490. struct target *target;
  1491. uint32_t addr;
  1492. uint32_t value; /* scratch/cache */
  1493. };
  1494. static int cortex_m3_dwt_get_reg(struct reg *reg)
  1495. {
  1496. struct dwt_reg_state *state = reg->arch_info;
  1497. return target_read_u32(state->target, state->addr, &state->value);
  1498. }
  1499. static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
  1500. {
  1501. struct dwt_reg_state *state = reg->arch_info;
  1502. return target_write_u32(state->target, state->addr,
  1503. buf_get_u32(buf, 0, reg->size));
  1504. }
  1505. struct dwt_reg {
  1506. uint32_t addr;
  1507. char *name;
  1508. unsigned size;
  1509. };
  1510. static struct dwt_reg dwt_base_regs[] = {
  1511. { DWT_CTRL, "dwt_ctrl", 32, },
  1512. /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
  1513. * increments while the core is asleep.
  1514. */
  1515. { DWT_CYCCNT, "dwt_cyccnt", 32, },
  1516. /* plus some 8 bit counters, useful for profiling with TPIU */
  1517. };
  1518. static struct dwt_reg dwt_comp[] = {
  1519. #define DWT_COMPARATOR(i) \
  1520. { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
  1521. { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
  1522. { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
  1523. DWT_COMPARATOR(0),
  1524. DWT_COMPARATOR(1),
  1525. DWT_COMPARATOR(2),
  1526. DWT_COMPARATOR(3),
  1527. #undef DWT_COMPARATOR
  1528. };
  1529. static const struct reg_arch_type dwt_reg_type = {
  1530. .get = cortex_m3_dwt_get_reg,
  1531. .set = cortex_m3_dwt_set_reg,
  1532. };
  1533. static void
  1534. cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
  1535. {
  1536. struct dwt_reg_state *state;
  1537. state = calloc(1, sizeof *state);
  1538. if (!state)
  1539. return;
  1540. state->addr = d->addr;
  1541. state->target = t;
  1542. r->name = d->name;
  1543. r->size = d->size;
  1544. r->value = &state->value;
  1545. r->arch_info = state;
  1546. r->type = &dwt_reg_type;
  1547. }
  1548. static void
  1549. cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
  1550. {
  1551. uint32_t dwtcr;
  1552. struct reg_cache *cache;
  1553. struct cortex_m3_dwt_comparator *comparator;
  1554. int reg, i;
  1555. target_read_u32(target, DWT_CTRL, &dwtcr);
  1556. if (!dwtcr) {
  1557. LOG_DEBUG("no DWT");
  1558. return;
  1559. }
  1560. cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
  1561. cm3->dwt_comp_available = cm3->dwt_num_comp;
  1562. cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
  1563. sizeof(struct cortex_m3_dwt_comparator));
  1564. if (!cm3->dwt_comparator_list) {
  1565. fail0:
  1566. cm3->dwt_num_comp = 0;
  1567. LOG_ERROR("out of mem");
  1568. return;
  1569. }
  1570. cache = calloc(1, sizeof *cache);
  1571. if (!cache) {
  1572. fail1:
  1573. free(cm3->dwt_comparator_list);
  1574. goto fail0;
  1575. }
  1576. cache->name = "cortex-m3 dwt registers";
  1577. cache->num_regs = 2 + cm3->dwt_num_comp * 3;
  1578. cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
  1579. if (!cache->reg_list) {
  1580. free(cache);
  1581. goto fail1;
  1582. }
  1583. for (reg = 0; reg < 2; reg++)
  1584. cortex_m3_dwt_addreg(target, cache->reg_list + reg,
  1585. dwt_base_regs + reg);
  1586. comparator = cm3->dwt_comparator_list;
  1587. for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
  1588. int j;
  1589. comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
  1590. for (j = 0; j < 3; j++, reg++)
  1591. cortex_m3_dwt_addreg(target, cache->reg_list + reg,
  1592. dwt_comp + 3 * i + j);
  1593. }
  1594. *register_get_last_cache_p(&target->reg_cache) = cache;
  1595. cm3->dwt_cache = cache;
  1596. LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
  1597. dwtcr, cm3->dwt_num_comp,
  1598. (dwtcr & (0xf << 24)) ? " only" : "/trigger");
  1599. /* REVISIT: if num_comp > 1, check whether comparator #1 can
  1600. * implement single-address data value watchpoints ... so we
  1601. * won't need to check it later, when asked to set one up.
  1602. */
  1603. }
  1604. static int cortex_m3_examine(struct target *target)
  1605. {
  1606. int retval;
  1607. uint32_t cpuid, fpcr;
  1608. int i;
  1609. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  1610. struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
  1611. if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
  1612. return retval;
  1613. if (!target_was_examined(target))
  1614. {
  1615. target_set_examined(target);
  1616. /* Read from Device Identification Registers */
  1617. retval = target_read_u32(target, CPUID, &cpuid);
  1618. if (retval != ERROR_OK)
  1619. return retval;
  1620. if (((cpuid >> 4) & 0xc3f) == 0xc23)
  1621. LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
  1622. (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
  1623. LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
  1624. /* NOTE: FPB and DWT are both optional. */
  1625. /* Setup FPB */
  1626. target_read_u32(target, FP_CTRL, &fpcr);
  1627. cortex_m3->auto_bp_type = 1;
  1628. cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
  1629. cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
  1630. cortex_m3->fp_code_available = cortex_m3->fp_num_code;
  1631. cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
  1632. cortex_m3->fpb_enabled = fpcr & 1;
  1633. for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
  1634. {
  1635. cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
  1636. cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
  1637. }
  1638. LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
  1639. /* Setup DWT */
  1640. cortex_m3_dwt_setup(cortex_m3, target);
  1641. /* These hardware breakpoints only work for code in flash! */
  1642. LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
  1643. target_name(target),
  1644. cortex_m3->fp_num_code,
  1645. cortex_m3->dwt_num_comp);
  1646. }
  1647. return ERROR_OK;
  1648. }
  1649. static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
  1650. {
  1651. uint16_t dcrdr;
  1652. int retval;
  1653. mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
  1654. *ctrl = (uint8_t)dcrdr;
  1655. *value = (uint8_t)(dcrdr >> 8);
  1656. LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
  1657. /* write ack back to software dcc register
  1658. * signify we have read data */
  1659. if (dcrdr & (1 << 0))
  1660. {
  1661. dcrdr = 0;
  1662. retval = mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
  1663. if (retval != ERROR_OK)
  1664. return retval;
  1665. }
  1666. return ERROR_OK;
  1667. }
  1668. static int cortex_m3_target_request_data(struct target *target,
  1669. uint32_t size, uint8_t *buffer)
  1670. {
  1671. struct armv7m_common *armv7m = target_to_armv7m(target);
  1672. struct adiv5_dap *swjdp = &armv7m->dap;
  1673. uint8_t data;
  1674. uint8_t ctrl;
  1675. uint32_t i;
  1676. for (i = 0; i < (size * 4); i++)
  1677. {
  1678. cortex_m3_dcc_read(swjdp, &data, &ctrl);
  1679. buffer[i] = data;
  1680. }
  1681. return ERROR_OK;
  1682. }
  1683. static int cortex_m3_handle_target_request(void *priv)
  1684. {
  1685. struct target *target = priv;
  1686. if (!target_was_examined(target))
  1687. return ERROR_OK;
  1688. struct armv7m_common *armv7m = target_to_armv7m(target);
  1689. struct adiv5_dap *swjdp = &armv7m->dap;
  1690. if (!target->dbg_msg_enabled)
  1691. return ERROR_OK;
  1692. if (target->state == TARGET_RUNNING)
  1693. {
  1694. uint8_t data;
  1695. uint8_t ctrl;
  1696. cortex_m3_dcc_read(swjdp, &data, &ctrl);
  1697. /* check if we have data */
  1698. if (ctrl & (1 << 0))
  1699. {
  1700. uint32_t request;
  1701. /* we assume target is quick enough */
  1702. request = data;
  1703. cortex_m3_dcc_read(swjdp, &data, &ctrl);
  1704. request |= (data << 8);
  1705. cortex_m3_dcc_read(swjdp, &data, &ctrl);
  1706. request |= (data << 16);
  1707. cortex_m3_dcc_read(swjdp, &data, &ctrl);
  1708. request |= (data << 24);
  1709. target_request(target, request);
  1710. }
  1711. }
  1712. return ERROR_OK;
  1713. }
  1714. static int cortex_m3_init_arch_info(struct target *target,
  1715. struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
  1716. {
  1717. int retval;
  1718. struct armv7m_common *armv7m = &cortex_m3->armv7m;
  1719. armv7m_init_arch_info(target, armv7m);
  1720. /* prepare JTAG information for the new target */
  1721. cortex_m3->jtag_info.tap = tap;
  1722. cortex_m3->jtag_info.scann_size = 4;
  1723. /* default reset mode is to use srst if fitted
  1724. * if not it will use CORTEX_M3_RESET_VECTRESET */
  1725. cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
  1726. armv7m->arm.dap = &armv7m->dap;
  1727. /* Leave (only) generic DAP stuff for debugport_init(); */
  1728. armv7m->dap.jtag_info = &cortex_m3->jtag_info;
  1729. armv7m->dap.memaccess_tck = 8;
  1730. /* Cortex-M3 has 4096 bytes autoincrement range */
  1731. armv7m->dap.tar_autoincr_block = (1 << 12);
  1732. /* register arch-specific functions */
  1733. armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
  1734. armv7m->post_debug_entry = NULL;
  1735. armv7m->pre_restore_context = NULL;
  1736. armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
  1737. armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
  1738. target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
  1739. if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
  1740. {
  1741. return retval;
  1742. }
  1743. return ERROR_OK;
  1744. }
  1745. static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
  1746. {
  1747. struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
  1748. cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
  1749. cortex_m3_init_arch_info(target, cortex_m3, target->tap);
  1750. return ERROR_OK;
  1751. }
  1752. /*--------------------------------------------------------------------------*/
  1753. static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
  1754. struct cortex_m3_common *cm3)
  1755. {
  1756. if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
  1757. command_print(cmd_ctx, "target is not a Cortex-M3");
  1758. return ERROR_TARGET_INVALID;
  1759. }
  1760. return ERROR_OK;
  1761. }
  1762. /*
  1763. * Only stuff below this line should need to verify that its target
  1764. * is a Cortex-M3. Everything else should have indirected through the
  1765. * cortexm3_target structure, which is only used with CM3 targets.
  1766. */
  1767. static const struct {
  1768. char name[10];
  1769. unsigned mask;
  1770. } vec_ids[] = {
  1771. { "hard_err", VC_HARDERR, },
  1772. { "int_err", VC_INTERR, },
  1773. { "bus_err", VC_BUSERR, },
  1774. { "state_err", VC_STATERR, },
  1775. { "chk_err", VC_CHKERR, },
  1776. { "nocp_err", VC_NOCPERR, },
  1777. { "mm_err", VC_MMERR, },
  1778. { "reset", VC_CORERESET, },
  1779. };
  1780. COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
  1781. {
  1782. struct target *target = get_current_target(CMD_CTX);
  1783. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  1784. struct armv7m_common *armv7m = &cortex_m3->armv7m;
  1785. struct adiv5_dap *swjdp = &armv7m->dap;
  1786. uint32_t demcr = 0;
  1787. int retval;
  1788. retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
  1789. if (retval != ERROR_OK)
  1790. return retval;
  1791. retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
  1792. if (retval != ERROR_OK)
  1793. return retval;
  1794. if (CMD_ARGC > 0) {
  1795. unsigned catch = 0;
  1796. if (CMD_ARGC == 1) {
  1797. if (strcmp(CMD_ARGV[0], "all") == 0) {
  1798. catch = VC_HARDERR | VC_INTERR | VC_BUSERR
  1799. | VC_STATERR | VC_CHKERR | VC_NOCPERR
  1800. | VC_MMERR | VC_CORERESET;
  1801. goto write;
  1802. } else if (strcmp(CMD_ARGV[0], "none") == 0) {
  1803. goto write;
  1804. }
  1805. }
  1806. while (CMD_ARGC-- > 0) {
  1807. unsigned i;
  1808. for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
  1809. if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
  1810. continue;
  1811. catch |= vec_ids[i].mask;
  1812. break;
  1813. }
  1814. if (i == ARRAY_SIZE(vec_ids)) {
  1815. LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
  1816. return ERROR_INVALID_ARGUMENTS;
  1817. }
  1818. }
  1819. write:
  1820. /* For now, armv7m->demcr only stores vector catch flags. */
  1821. armv7m->demcr = catch;
  1822. demcr &= ~0xffff;
  1823. demcr |= catch;
  1824. /* write, but don't assume it stuck (why not??) */
  1825. retval = mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
  1826. if (retval != ERROR_OK)
  1827. return retval;
  1828. retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
  1829. if (retval != ERROR_OK)
  1830. return retval;
  1831. /* FIXME be sure to clear DEMCR on clean server shutdown.
  1832. * Otherwise the vector catch hardware could fire when there's
  1833. * no debugger hooked up, causing much confusion...
  1834. */
  1835. }
  1836. for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
  1837. {
  1838. command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
  1839. (demcr & vec_ids[i].mask) ? "catch" : "ignore");
  1840. }
  1841. return ERROR_OK;
  1842. }
  1843. COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
  1844. {
  1845. struct target *target = get_current_target(CMD_CTX);
  1846. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  1847. int retval;
  1848. static const Jim_Nvp nvp_maskisr_modes[] = {
  1849. { .name = "auto", .value = CORTEX_M3_ISRMASK_AUTO },
  1850. { .name = "off" , .value = CORTEX_M3_ISRMASK_OFF },
  1851. { .name = "on" , .value = CORTEX_M3_ISRMASK_ON },
  1852. { .name = NULL , .value = -1 },
  1853. };
  1854. const Jim_Nvp *n;
  1855. retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
  1856. if (retval != ERROR_OK)
  1857. return retval;
  1858. if (target->state != TARGET_HALTED)
  1859. {
  1860. command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
  1861. return ERROR_OK;
  1862. }
  1863. if (CMD_ARGC > 0)
  1864. {
  1865. n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
  1866. if (n->name == NULL)
  1867. {
  1868. return ERROR_COMMAND_SYNTAX_ERROR;
  1869. }
  1870. cortex_m3->isrmasking_mode = n->value;
  1871. if(cortex_m3->isrmasking_mode == CORTEX_M3_ISRMASK_ON)
  1872. {
  1873. cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
  1874. }
  1875. else
  1876. {
  1877. cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
  1878. }
  1879. }
  1880. n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m3->isrmasking_mode);
  1881. command_print(CMD_CTX, "cortex_m3 interrupt mask %s", n->name);
  1882. return ERROR_OK;
  1883. }
  1884. COMMAND_HANDLER(handle_cortex_m3_reset_config_command)
  1885. {
  1886. struct target *target = get_current_target(CMD_CTX);
  1887. struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
  1888. int retval;
  1889. char *reset_config;
  1890. retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
  1891. if (retval != ERROR_OK)
  1892. return retval;
  1893. if (CMD_ARGC > 0)
  1894. {
  1895. if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
  1896. cortex_m3->soft_reset_config = CORTEX_M3_RESET_SYSRESETREQ;
  1897. else if (strcmp(*CMD_ARGV, "vectreset") == 0)
  1898. cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
  1899. }
  1900. switch (cortex_m3->soft_reset_config)
  1901. {
  1902. case CORTEX_M3_RESET_SYSRESETREQ:
  1903. reset_config = "sysresetreq";
  1904. break;
  1905. case CORTEX_M3_RESET_VECTRESET:
  1906. reset_config = "vectreset";
  1907. break;
  1908. default:
  1909. reset_config = "unknown";
  1910. break;
  1911. }
  1912. command_print(CMD_CTX, "cortex_m3 reset_config %s", reset_config);
  1913. return ERROR_OK;
  1914. }
  1915. static const struct command_registration cortex_m3_exec_command_handlers[] = {
  1916. {
  1917. .name = "maskisr",
  1918. .handler = handle_cortex_m3_mask_interrupts_command,
  1919. .mode = COMMAND_EXEC,
  1920. .help = "mask cortex_m3 interrupts",
  1921. .usage = "['auto'|'on'|'off']",
  1922. },
  1923. {
  1924. .name = "vector_catch",
  1925. .handler = handle_cortex_m3_vector_catch_command,
  1926. .mode = COMMAND_EXEC,
  1927. .help = "configure hardware vectors to trigger debug entry",
  1928. .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
  1929. },
  1930. {
  1931. .name = "reset_config",
  1932. .handler = handle_cortex_m3_reset_config_command,
  1933. .mode = COMMAND_ANY,
  1934. .help = "configure software reset handling",
  1935. .usage = "['srst'|'sysresetreq'|'vectreset']",
  1936. },
  1937. COMMAND_REGISTRATION_DONE
  1938. };
  1939. static const struct command_registration cortex_m3_command_handlers[] = {
  1940. {
  1941. .chain = armv7m_command_handlers,
  1942. },
  1943. {
  1944. .name = "cortex_m3",
  1945. .mode = COMMAND_EXEC,
  1946. .help = "Cortex-M3 command group",
  1947. .chain = cortex_m3_exec_command_handlers,
  1948. },
  1949. COMMAND_REGISTRATION_DONE
  1950. };
  1951. struct target_type cortexm3_target =
  1952. {
  1953. .name = "cortex_m3",
  1954. .poll = cortex_m3_poll,
  1955. .arch_state = armv7m_arch_state,
  1956. .target_request_data = cortex_m3_target_request_data,
  1957. .halt = cortex_m3_halt,
  1958. .resume = cortex_m3_resume,
  1959. .step = cortex_m3_step,
  1960. .assert_reset = cortex_m3_assert_reset,
  1961. .deassert_reset = cortex_m3_deassert_reset,
  1962. .soft_reset_halt = cortex_m3_soft_reset_halt,
  1963. .get_gdb_reg_list = armv7m_get_gdb_reg_list,
  1964. .read_memory = cortex_m3_read_memory,
  1965. .write_memory = cortex_m3_write_memory,
  1966. .bulk_write_memory = cortex_m3_bulk_write_memory,
  1967. .checksum_memory = armv7m_checksum_memory,
  1968. .blank_check_memory = armv7m_blank_check_memory,
  1969. .run_algorithm = armv7m_run_algorithm,
  1970. .add_breakpoint = cortex_m3_add_breakpoint,
  1971. .remove_breakpoint = cortex_m3_remove_breakpoint,
  1972. .add_watchpoint = cortex_m3_add_watchpoint,
  1973. .remove_watchpoint = cortex_m3_remove_watchpoint,
  1974. .commands = cortex_m3_command_handlers,
  1975. .target_create = cortex_m3_target_create,
  1976. .init_target = cortex_m3_init_target,
  1977. .examine = cortex_m3_examine,
  1978. };