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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. #ifdef HAVE_CONFIG_H
  21. #include "config.h"
  22. #endif
  23. #include "arm720t.h"
  24. #include "time_support.h"
  25. #include "target_type.h"
  26. #if 0
  27. #define _DEBUG_INSTRUCTION_EXECUTION_
  28. #endif
  29. /* cli handling */
  30. int arm720t_register_commands(struct command_context_s *cmd_ctx);
  31. int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  32. int arm720t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  33. int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  34. int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  35. /* forward declarations */
  36. int arm720t_target_create(struct target_s *target,Jim_Interp *interp);
  37. int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  38. int arm720t_quit(void);
  39. int arm720t_arch_state(struct target_s *target);
  40. int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  41. int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  42. int arm720t_soft_reset_halt(struct target_s *target);
  43. target_type_t arm720t_target =
  44. {
  45. .name = "arm720t",
  46. .poll = arm7_9_poll,
  47. .arch_state = arm720t_arch_state,
  48. .halt = arm7_9_halt,
  49. .resume = arm7_9_resume,
  50. .step = arm7_9_step,
  51. .assert_reset = arm7_9_assert_reset,
  52. .deassert_reset = arm7_9_deassert_reset,
  53. .soft_reset_halt = arm720t_soft_reset_halt,
  54. .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  55. .read_memory = arm720t_read_memory,
  56. .write_memory = arm720t_write_memory,
  57. .bulk_write_memory = arm7_9_bulk_write_memory,
  58. .checksum_memory = arm7_9_checksum_memory,
  59. .blank_check_memory = arm7_9_blank_check_memory,
  60. .run_algorithm = armv4_5_run_algorithm,
  61. .add_breakpoint = arm7_9_add_breakpoint,
  62. .remove_breakpoint = arm7_9_remove_breakpoint,
  63. .add_watchpoint = arm7_9_add_watchpoint,
  64. .remove_watchpoint = arm7_9_remove_watchpoint,
  65. .register_commands = arm720t_register_commands,
  66. .target_create = arm720t_target_create,
  67. .init_target = arm720t_init_target,
  68. .examine = arm7tdmi_examine,
  69. .quit = arm720t_quit
  70. };
  71. int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock)
  72. {
  73. int retval = ERROR_OK;
  74. armv4_5_common_t *armv4_5 = target->arch_info;
  75. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  76. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  77. scan_field_t fields[2];
  78. u8 out_buf[4];
  79. u8 instruction_buf = instruction;
  80. buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
  81. jtag_set_end_state(TAP_DRPAUSE);
  82. if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
  83. {
  84. return retval;
  85. }
  86. if((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
  87. {
  88. return retval;
  89. }
  90. fields[0].tap = jtag_info->tap;
  91. fields[0].num_bits = 1;
  92. fields[0].out_value = &instruction_buf;
  93. fields[0].in_value = NULL;
  94. fields[1].tap = jtag_info->tap;
  95. fields[1].num_bits = 32;
  96. fields[1].out_value = out_buf;
  97. fields[1].in_value = NULL;
  98. if (in)
  99. {
  100. fields[1].in_value = (u8 *)in;
  101. jtag_add_dr_scan(2, fields, jtag_get_end_state());
  102. jtag_add_callback(arm7flip32, (u8 *)in);
  103. } else
  104. {
  105. jtag_add_dr_scan(2, fields, jtag_get_end_state());
  106. }
  107. if (clock)
  108. jtag_add_runtest(0, jtag_get_end_state());
  109. #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  110. if((retval = jtag_execute_queue()) != ERROR_OK)
  111. {
  112. return retval;
  113. }
  114. if (in)
  115. LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
  116. else
  117. LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
  118. #else
  119. LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
  120. #endif
  121. return ERROR_OK;
  122. }
  123. int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value)
  124. {
  125. /* fetch CP15 opcode */
  126. arm720t_scan_cp15(target, opcode, NULL, 1, 1);
  127. /* "DECODE" stage */
  128. arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
  129. /* "EXECUTE" stage (1) */
  130. arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
  131. arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
  132. /* "EXECUTE" stage (2) */
  133. arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
  134. /* "EXECUTE" stage (3), CDATA is read */
  135. arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
  136. return ERROR_OK;
  137. }
  138. int arm720t_write_cp15(target_t *target, u32 opcode, u32 value)
  139. {
  140. /* fetch CP15 opcode */
  141. arm720t_scan_cp15(target, opcode, NULL, 1, 1);
  142. /* "DECODE" stage */
  143. arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
  144. /* "EXECUTE" stage (1) */
  145. arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
  146. arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
  147. /* "EXECUTE" stage (2) */
  148. arm720t_scan_cp15(target, value, NULL, 0, 1);
  149. arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
  150. return ERROR_OK;
  151. }
  152. u32 arm720t_get_ttb(target_t *target)
  153. {
  154. u32 ttb = 0x0;
  155. arm720t_read_cp15(target, 0xee120f10, &ttb);
  156. jtag_execute_queue();
  157. ttb &= 0xffffc000;
  158. return ttb;
  159. }
  160. void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
  161. {
  162. u32 cp15_control;
  163. /* read cp15 control register */
  164. arm720t_read_cp15(target, 0xee110f10, &cp15_control);
  165. jtag_execute_queue();
  166. if (mmu)
  167. cp15_control &= ~0x1U;
  168. if (d_u_cache || i_cache)
  169. cp15_control &= ~0x4U;
  170. arm720t_write_cp15(target, 0xee010f10, cp15_control);
  171. }
  172. void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
  173. {
  174. u32 cp15_control;
  175. /* read cp15 control register */
  176. arm720t_read_cp15(target, 0xee110f10, &cp15_control);
  177. jtag_execute_queue();
  178. if (mmu)
  179. cp15_control |= 0x1U;
  180. if (d_u_cache || i_cache)
  181. cp15_control |= 0x4U;
  182. arm720t_write_cp15(target, 0xee010f10, cp15_control);
  183. }
  184. void arm720t_post_debug_entry(target_t *target)
  185. {
  186. armv4_5_common_t *armv4_5 = target->arch_info;
  187. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  188. arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
  189. arm720t_common_t *arm720t = arm7tdmi->arch_info;
  190. /* examine cp15 control reg */
  191. arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
  192. jtag_execute_queue();
  193. LOG_DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);
  194. arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
  195. arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
  196. arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
  197. /* save i/d fault status and address register */
  198. arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
  199. arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
  200. jtag_execute_queue();
  201. }
  202. void arm720t_pre_restore_context(target_t *target)
  203. {
  204. armv4_5_common_t *armv4_5 = target->arch_info;
  205. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  206. arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
  207. arm720t_common_t *arm720t = arm7tdmi->arch_info;
  208. /* restore i/d fault status and address register */
  209. arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
  210. arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
  211. }
  212. int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
  213. {
  214. armv4_5_common_t *armv4_5 = target->arch_info;
  215. arm7_9_common_t *arm7_9;
  216. arm7tdmi_common_t *arm7tdmi;
  217. arm720t_common_t *arm720t;
  218. if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
  219. {
  220. return -1;
  221. }
  222. arm7_9 = armv4_5->arch_info;
  223. if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
  224. {
  225. return -1;
  226. }
  227. arm7tdmi = arm7_9->arch_info;
  228. if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)
  229. {
  230. return -1;
  231. }
  232. arm720t = arm7tdmi->arch_info;
  233. if (arm720t->common_magic != ARM720T_COMMON_MAGIC)
  234. {
  235. return -1;
  236. }
  237. *armv4_5_p = armv4_5;
  238. *arm7_9_p = arm7_9;
  239. *arm7tdmi_p = arm7tdmi;
  240. *arm720t_p = arm720t;
  241. return ERROR_OK;
  242. }
  243. int arm720t_arch_state(struct target_s *target)
  244. {
  245. armv4_5_common_t *armv4_5 = target->arch_info;
  246. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  247. arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
  248. arm720t_common_t *arm720t = arm7tdmi->arch_info;
  249. char *state[] =
  250. {
  251. "disabled", "enabled"
  252. };
  253. if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
  254. {
  255. LOG_ERROR("BUG: called for a non-ARMv4/5 target");
  256. exit(-1);
  257. }
  258. LOG_USER("target halted in %s state due to %s, current mode: %s\n"
  259. "cpsr: 0x%8.8x pc: 0x%8.8x\n"
  260. "MMU: %s, Cache: %s",
  261. armv4_5_state_strings[armv4_5->core_state],
  262. Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
  263. armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
  264. buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
  265. buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
  266. state[arm720t->armv4_5_mmu.mmu_enabled],
  267. state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
  268. return ERROR_OK;
  269. }
  270. int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
  271. {
  272. int retval;
  273. armv4_5_common_t *armv4_5 = target->arch_info;
  274. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  275. arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
  276. arm720t_common_t *arm720t = arm7tdmi->arch_info;
  277. /* disable cache, but leave MMU enabled */
  278. if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
  279. arm720t_disable_mmu_caches(target, 0, 1, 0);
  280. retval = arm7_9_read_memory(target, address, size, count, buffer);
  281. if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
  282. arm720t_enable_mmu_caches(target, 0, 1, 0);
  283. return retval;
  284. }
  285. int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
  286. {
  287. int retval;
  288. if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
  289. return retval;
  290. return retval;
  291. }
  292. int arm720t_soft_reset_halt(struct target_s *target)
  293. {
  294. int retval = ERROR_OK;
  295. armv4_5_common_t *armv4_5 = target->arch_info;
  296. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  297. arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
  298. arm720t_common_t *arm720t = arm7tdmi->arch_info;
  299. reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  300. if ((retval = target_halt(target)) != ERROR_OK)
  301. {
  302. return retval;
  303. }
  304. long long then=timeval_ms();
  305. int timeout;
  306. while (!(timeout=((timeval_ms()-then)>1000)))
  307. {
  308. if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
  309. {
  310. embeddedice_read_reg(dbg_stat);
  311. if ((retval = jtag_execute_queue()) != ERROR_OK)
  312. {
  313. return retval;
  314. }
  315. } else
  316. {
  317. break;
  318. }
  319. if (debug_level>=3)
  320. {
  321. alive_sleep(100);
  322. } else
  323. {
  324. keep_alive();
  325. }
  326. }
  327. if (timeout)
  328. {
  329. LOG_ERROR("Failed to halt CPU after 1 sec");
  330. return ERROR_TARGET_TIMEOUT;
  331. }
  332. target->state = TARGET_HALTED;
  333. /* SVC, ARM state, IRQ and FIQ disabled */
  334. buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
  335. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
  336. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
  337. /* start fetching from 0x0 */
  338. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
  339. armv4_5->core_cache->reg_list[15].dirty = 1;
  340. armv4_5->core_cache->reg_list[15].valid = 1;
  341. armv4_5->core_mode = ARMV4_5_MODE_SVC;
  342. armv4_5->core_state = ARMV4_5_STATE_ARM;
  343. arm720t_disable_mmu_caches(target, 1, 1, 1);
  344. arm720t->armv4_5_mmu.mmu_enabled = 0;
  345. arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
  346. arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
  347. if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
  348. {
  349. return retval;
  350. }
  351. return ERROR_OK;
  352. }
  353. int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
  354. {
  355. arm7tdmi_init_target(cmd_ctx, target);
  356. return ERROR_OK;
  357. }
  358. int arm720t_quit(void)
  359. {
  360. return ERROR_OK;
  361. }
  362. int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap)
  363. {
  364. arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
  365. arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
  366. arm7tdmi_init_arch_info(target, arm7tdmi, tap);
  367. arm7tdmi->arch_info = arm720t;
  368. arm720t->common_magic = ARM720T_COMMON_MAGIC;
  369. arm7_9->post_debug_entry = arm720t_post_debug_entry;
  370. arm7_9->pre_restore_context = arm720t_pre_restore_context;
  371. arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
  372. arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
  373. arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
  374. arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
  375. arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
  376. arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
  377. arm720t->armv4_5_mmu.has_tiny_pages = 0;
  378. arm720t->armv4_5_mmu.mmu_enabled = 0;
  379. return ERROR_OK;
  380. }
  381. int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
  382. {
  383. arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t));
  384. arm720t_init_arch_info(target, arm720t, target->tap);
  385. return ERROR_OK;
  386. }
  387. int arm720t_register_commands(struct command_context_s *cmd_ctx)
  388. {
  389. int retval;
  390. command_t *arm720t_cmd;
  391. retval = arm7tdmi_register_commands(cmd_ctx);
  392. arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");
  393. register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
  394. register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
  395. register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
  396. register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
  397. register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
  398. register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
  399. register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
  400. register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
  401. return ERROR_OK;
  402. }
  403. int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  404. {
  405. int retval;
  406. target_t *target = get_current_target(cmd_ctx);
  407. armv4_5_common_t *armv4_5;
  408. arm7_9_common_t *arm7_9;
  409. arm7tdmi_common_t *arm7tdmi;
  410. arm720t_common_t *arm720t;
  411. arm_jtag_t *jtag_info;
  412. if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
  413. {
  414. command_print(cmd_ctx, "current target isn't an ARM720t target");
  415. return ERROR_OK;
  416. }
  417. jtag_info = &arm7_9->jtag_info;
  418. if (target->state != TARGET_HALTED)
  419. {
  420. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  421. return ERROR_OK;
  422. }
  423. /* one or more argument, access a single register (write if second argument is given */
  424. if (argc >= 1)
  425. {
  426. u32 opcode = strtoul(args[0], NULL, 0);
  427. if (argc == 1)
  428. {
  429. u32 value;
  430. if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
  431. {
  432. command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
  433. return ERROR_OK;
  434. }
  435. if ((retval = jtag_execute_queue()) != ERROR_OK)
  436. {
  437. return retval;
  438. }
  439. command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
  440. }
  441. else if (argc == 2)
  442. {
  443. u32 value = strtoul(args[1], NULL, 0);
  444. if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
  445. {
  446. command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
  447. return ERROR_OK;
  448. }
  449. command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
  450. }
  451. }
  452. return ERROR_OK;
  453. }
  454. int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
  455. {
  456. target_t *target = get_current_target(cmd_ctx);
  457. armv4_5_common_t *armv4_5;
  458. arm7_9_common_t *arm7_9;
  459. arm7tdmi_common_t *arm7tdmi;
  460. arm720t_common_t *arm720t;
  461. arm_jtag_t *jtag_info;
  462. if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
  463. {
  464. command_print(cmd_ctx, "current target isn't an ARM720t target");
  465. return ERROR_OK;
  466. }
  467. jtag_info = &arm7_9->jtag_info;
  468. if (target->state != TARGET_HALTED)
  469. {
  470. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  471. return ERROR_OK;
  472. }
  473. return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
  474. }
  475. int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
  476. {
  477. target_t *target = get_current_target(cmd_ctx);
  478. armv4_5_common_t *armv4_5;
  479. arm7_9_common_t *arm7_9;
  480. arm7tdmi_common_t *arm7tdmi;
  481. arm720t_common_t *arm720t;
  482. arm_jtag_t *jtag_info;
  483. if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
  484. {
  485. command_print(cmd_ctx, "current target isn't an ARM720t target");
  486. return ERROR_OK;
  487. }
  488. jtag_info = &arm7_9->jtag_info;
  489. if (target->state != TARGET_HALTED)
  490. {
  491. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  492. return ERROR_OK;
  493. }
  494. return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
  495. }
  496. int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
  497. {
  498. target_t *target = get_current_target(cmd_ctx);
  499. armv4_5_common_t *armv4_5;
  500. arm7_9_common_t *arm7_9;
  501. arm7tdmi_common_t *arm7tdmi;
  502. arm720t_common_t *arm720t;
  503. arm_jtag_t *jtag_info;
  504. if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
  505. {
  506. command_print(cmd_ctx, "current target isn't an ARM720t target");
  507. return ERROR_OK;
  508. }
  509. jtag_info = &arm7_9->jtag_info;
  510. if (target->state != TARGET_HALTED)
  511. {
  512. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  513. return ERROR_OK;
  514. }
  515. return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
  516. }