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  1. #
  2. # Copyright (C) 2010-2011 by Karl Kurbjun
  3. # Copyright (C) 2009-2011 by Øyvind Harboe
  4. # Copyright (C) 2009 by David Brownell
  5. # Copyright (C) 2009 by Magnus Lundin
  6. #
  7. # TI AM/DM37x
  8. # http://www.ti.com/litv/pdf/sprugn4b
  9. #
  10. # This script is based on the AM3517 initialization. It should be considered
  11. # preliminary since it needs more complete testing and only the basic
  12. # operations work.
  13. #
  14. ###############################################################################
  15. # User modifiable parameters
  16. ###############################################################################
  17. # This script uses the variable CHIPTYPE to determine whether this is an AM35x
  18. # or DM37x target. If CHIPTYPE is not set it will error out.
  19. if { [info exists CHIPTYPE] } {
  20. if { [info exists CHIPNAME] } {
  21. set _CHIPNAME $CHIPNAME
  22. } else {
  23. set _CHIPNAME $CHIPTYPE
  24. }
  25. switch $CHIPTYPE {
  26. dm37x {
  27. # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
  28. set _JRC_TAPID "-expected-id 0x2b89102f -expected-id 0x1b89102f -expected-id 0x0b89102f"
  29. }
  30. am35x {
  31. # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
  32. set _JRC_TAPID "-expected-id 0x0b7ae02f"
  33. }
  34. default {
  35. error "ERROR: CHIPTYPE was set, but it was not set to a valid value. Acceptable values are \"dm37x\" or \"am35x\"."
  36. }
  37. }
  38. } else {
  39. error "ERROR: CHIPTYPE was not defined. Please set CHIPTYPE to \"am35x\" for the AM35x or \"dm37x\" for the DM37x series in the board configuration."
  40. }
  41. # Run the adapter at the fastest acceptable speed with the slowest possible
  42. # core clock.
  43. adapter_khz 10
  44. ###############################################################################
  45. # JTAG setup
  46. # The OpenOCD commands are described in the TAP Declaration section
  47. # http://openocd.berlios.de/doc/html/TAP-Declaration.html
  48. ###############################################################################
  49. # The AM/DM37x has an ICEpick module in it like many of TI's other devices. More
  50. # can be read about this module in sprugn4b under chapter 27: "Debug and
  51. # Emulation". The module is used to route the JTAG chain to the various
  52. # subsystems in the chip.
  53. source [find target/icepick.cfg]
  54. # The TAP order should be described from the TDO connection in OpenOCD to the
  55. # TDI pin. The OpenOCD FAQ describes this in more detail:
  56. # http://openocd.berlios.de/doc/html/FAQ.html
  57. # From SPRUGN4B CH27 the available secondary TAPs are in this order from TDO:
  58. #
  59. # Device | TAP number
  60. # ---------|------------
  61. # DAP | 3
  62. # Sequencer| 2 Note: The sequencer is an ARM968
  63. # DSP | 1
  64. # D2D | 0
  65. #
  66. # Right now the only secondary tap enabled is the DAP so the rest are left
  67. # undescribed.
  68. ######
  69. # Start of Chain Description
  70. # The Secondary TAPs all have enable functions defined for use with the ICEpick
  71. # Only the DAP is enabled. The AM37xx does not have the Sequencer or DSP but
  72. # the TAP numbers for ICEpick do not change.
  73. #
  74. # TODO: A disable function should also be added.
  75. ######
  76. # Secondary TAP: DAP is closest to the TDO output
  77. # The TAP enable event also needs to be described
  78. jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -disable
  79. jtag configure $_CHIPNAME.dap -event tap-enable \
  80. "icepick_c_tapenable $_CHIPNAME.jrc 3"
  81. # These taps are only present in the DM37x series.
  82. if { $CHIPTYPE == "dm37x" } {
  83. # Secondary TAP: Sequencer (ARM968) it is not in the chain by default
  84. # The ICEpick can be used to enable it in the chain.
  85. jtag newtap $_CHIPNAME arm2 -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
  86. jtag configure $_CHIPNAME.arm2 -event tap-enable \
  87. "icepick_c_tapenable $_CHIPNAME.jrc 2"
  88. # Secondary TAP: C64x+ DSP - it is not in the chain by default (-disable)
  89. # The ICEpick can be used to enable it in the chain.
  90. jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
  91. jtag configure $_CHIPNAME.dsp -event tap-enable \
  92. "icepick_c_tapenable $_CHIPNAME.jrc 1"
  93. }
  94. # Secondary TAP: D2D it is not in the chain by default (-disable)
  95. # The ICEpick can be used to enable it in the chain.
  96. # This IRLEN is probably incorrect - not sure where the documentation is.
  97. jtag newtap $_CHIPNAME d2d -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
  98. jtag configure $_CHIPNAME.d2d -event tap-enable \
  99. "icepick_c_tapenable $_CHIPNAME.jrc 0"
  100. # Primary TAP: ICEpick - it is closest to TDI so last in the chain
  101. eval "jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID"
  102. ######
  103. # End of Chain Description
  104. ######
  105. ######
  106. # Start JTAG TAP events
  107. ######
  108. # some TCK tycles are required to activate the DEBUG power domain
  109. jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
  110. # Enable the DAP TAP
  111. jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
  112. ######
  113. # End JTAG TAP events
  114. ######
  115. ###############################################################################
  116. # Target Setup:
  117. # This section is described in the OpenOCD documentation under CPU Configuration
  118. # http://openocd.berlios.de/doc/html/CPU-Configuration.html
  119. ###############################################################################
  120. # Create the CPU target to be used with GDB: Cortex-A8, using DAP
  121. set _TARGETNAME $_CHIPNAME.cpu
  122. target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
  123. # The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first
  124. # 16K to be used as a scratchpad for OpenOCD.
  125. $_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
  126. ######
  127. # Start Target Reset Event Setup:
  128. ######
  129. # Set the JTAG clock down to 10 kHz to be sure that it will work with the
  130. # slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
  131. # *after* PLL and clock tree setup.
  132. $_TARGETNAME configure -event "reset-start" { adapter_khz 10 }
  133. # Describe the reset assert process for openocd - this is asserted with the
  134. # ICEPick
  135. $_TARGETNAME configure -event "reset-assert" {
  136. global _CHIPNAME
  137. # assert warm system reset through ICEPick
  138. icepick_c_wreset $_CHIPNAME.jrc
  139. }
  140. # After the reset is asserted we need to re-initialize debugging and speed up
  141. # the JTAG clock.
  142. $_TARGETNAME configure -event reset-assert-post {
  143. global _TARGETNAME
  144. amdm37x_dbginit $_TARGETNAME
  145. adapter_khz 1000
  146. }
  147. $_TARGETNAME configure -event gdb-attach {
  148. global _TARGETNAME
  149. amdm37x_dbginit $_TARGETNAME
  150. echo "Halting target"
  151. halt
  152. }
  153. ######
  154. # End Target Reset Event Setup:
  155. ######
  156. ###############################################################################
  157. # Target Functions
  158. # Add any functions needed for the target here
  159. ###############################################################################
  160. # Run this to enable invasive debugging. This is run automatically in the
  161. # reset sequence.
  162. proc amdm37x_dbginit {target} {
  163. # General Cortex A8 debug initialisation
  164. cortex_a dbginit
  165. # Enable DBGEN signal. This signal is described in the ARM v7 TRM, but
  166. # access to the signal appears to be implementation specific. TI does not
  167. # describe this register much except a quick line that states DBGEM (sic) is
  168. # at this address and this bit.
  169. $target mww phys 0x5401d030 0x00002000
  170. }