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52 lines
1.3 KiB

  1. # Freescale i.MX53
  2. if { [info exists CHIPNAME] } {
  3. set _CHIPNAME $CHIPNAME
  4. } else {
  5. set _CHIPNAME imx53
  6. }
  7. # CoreSight Debug Access Port
  8. if { [info exists DAP_TAPID] } {
  9. set _DAP_TAPID $DAP_TAPID
  10. } else {
  11. set _DAP_TAPID 0x1ba00477
  12. }
  13. jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \
  14. -expected-id $_DAP_TAPID
  15. # SDMA / no IDCODE
  16. jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf
  17. # SJC
  18. if { [info exists SJC_TAPID] } {
  19. set _SJC_TAPID SJC_TAPID
  20. } else {
  21. set _SJC_TAPID 0x0190d01d
  22. }
  23. jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
  24. -expected-id $_SJC_TAPID -ignore-version
  25. # GDB target: Cortex-A8, using DAP
  26. set _TARGETNAME $_CHIPNAME.cpu
  27. target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP
  28. # some TCK tycles are required to activate the DEBUG power domain
  29. jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
  30. # have the DAP "always" be active
  31. jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
  32. proc imx53_dbginit {target} {
  33. # General Cortex A8 debug initialisation
  34. cortex_a dbginit
  35. }
  36. # Slow speed to be sure it will work
  37. jtag_rclk 1000
  38. $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
  39. $_TARGETNAME configure -event reset-assert-post "imx53_dbginit $_TARGETNAME"