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  1. # str910-eval eval board
  2. #
  3. # Need reset scripts
  4. reset_config trst_and_srst
  5. if { [info exists CHIPNAME] } {
  6. set _CHIPNAME $CHIPNAME
  7. } else {
  8. set _CHIPNAME str912
  9. }
  10. if { [info exists ENDIAN] } {
  11. set _ENDIAN $ENDIAN
  12. } else {
  13. set _ENDIAN little
  14. }
  15. if { [info exists FLASHTAPID ] } {
  16. set _FLASHTAPID $FLASHTAPID
  17. } else {
  18. set _FLASHTAPID 0x04570041
  19. }
  20. jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
  21. if { [info exists CPUTAPID ] } {
  22. set _CPUTAPID $CPUTAPID
  23. } else {
  24. set _CPUTAPID 0x25966041
  25. }
  26. jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  27. if { [info exists BSTAPID ] } {
  28. set _BSTAPID $BSTAPID
  29. } else {
  30. set _BSTAPID 0x1457f041
  31. }
  32. jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
  33. set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
  34. target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
  35. $_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000 -work-area-size 16384 -work-area-backup 1
  36. $_TARGETNAME configure -event reset-init {
  37. # We can increase speed now that we know the target is halted.
  38. #jtag_rclk 3000
  39. # -- Enable 96K RAM
  40. # PFQBC enabled / DTCM & AHB wait-states disabled
  41. mww 0x5C002034 0x0191
  42. str9x flash_config 0 4 2 0 0x80000
  43. flash protect 0 0 7 off
  44. }
  45. #flash bank str9x <base> <size> 0 0 <target#> <variant>
  46. flash bank str9x 0x00000000 0x00080000 0 0 0
  47. flash bank str9x 0x00080000 0x00008000 0 0 0
  48. # For more information about the configuration files, take a look at:
  49. # openocd.texi