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  1. /***************************************************************************
  2. * Copyright (C) 2013 by Andrey Yurovsky *
  3. * Andrey Yurovsky <yurovsky@gmail.com> *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program. If not, see <http://www.gnu.org/licenses/>. *
  17. ***************************************************************************/
  18. #ifdef HAVE_CONFIG_H
  19. #include "config.h"
  20. #endif
  21. #include "imp.h"
  22. #include "helper/binarybuffer.h"
  23. #include <target/cortex_m.h>
  24. #define SAMD_NUM_PROT_BLOCKS 16
  25. #define SAMD_PAGE_SIZE_MAX 1024
  26. #define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */
  27. #define SAMD_USER_ROW ((uint32_t)0x00804000) /* User Row of Flash */
  28. #define SAMD_PAC1 0x41000000 /* Peripheral Access Control 1 */
  29. #define SAMD_DSU 0x41002000 /* Device Service Unit */
  30. #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
  31. #define SAMD_DSU_STATUSA 1 /* DSU status register */
  32. #define SAMD_DSU_DID 0x18 /* Device ID register */
  33. #define SAMD_DSU_CTRL_EXT 0x100 /* CTRL register, external access */
  34. #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
  35. #define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
  36. #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
  37. #define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interrupt Flag Status & Clear */
  38. #define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
  39. #define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
  40. #define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
  41. #define SAMD_CMDEX_KEY 0xA5UL
  42. #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
  43. /* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
  44. #define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
  45. #define SAMD_NVM_CMD_WP 0x04 /* Write Page */
  46. #define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxiliary Row */
  47. #define SAMD_NVM_CMD_WAP 0x06 /* Write Auxiliary Page */
  48. #define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
  49. #define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
  50. #define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
  51. #define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */
  52. #define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */
  53. #define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
  54. #define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
  55. /* NVMCTRL bits */
  56. #define SAMD_NVM_CTRLB_MANW 0x80
  57. /* Known identifiers */
  58. #define SAMD_PROCESSOR_M0 0x01
  59. #define SAMD_FAMILY_D 0x00
  60. #define SAMD_FAMILY_L 0x01
  61. #define SAMD_FAMILY_C 0x02
  62. #define SAMD_SERIES_20 0x00
  63. #define SAMD_SERIES_21 0x01
  64. #define SAMD_SERIES_22 0x02
  65. #define SAMD_SERIES_10 0x02
  66. #define SAMD_SERIES_11 0x03
  67. #define SAMD_SERIES_09 0x04
  68. /* Device ID macros */
  69. #define SAMD_GET_PROCESSOR(id) (id >> 28)
  70. #define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
  71. #define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
  72. #define SAMD_GET_DEVSEL(id) (id & 0xFF)
  73. /* Bits to mask out lockbits in user row */
  74. #define NVMUSERROW_LOCKBIT_MASK ((uint64_t)0x0000FFFFFFFFFFFF)
  75. struct samd_part {
  76. uint8_t id;
  77. const char *name;
  78. uint32_t flash_kb;
  79. uint32_t ram_kb;
  80. };
  81. /* Known SAMD09 parts. DID reset values missing in RM, see
  82. * https://github.com/avrxml/asf/blob/master/sam0/utils/cmsis/samd09/include/ */
  83. static const struct samd_part samd09_parts[] = {
  84. { 0x0, "SAMD09D14A", 16, 4 },
  85. { 0x7, "SAMD09C13A", 8, 4 },
  86. };
  87. /* Known SAMD10 parts */
  88. static const struct samd_part samd10_parts[] = {
  89. { 0x0, "SAMD10D14AMU", 16, 4 },
  90. { 0x1, "SAMD10D13AMU", 8, 4 },
  91. { 0x2, "SAMD10D12AMU", 4, 4 },
  92. { 0x3, "SAMD10D14ASU", 16, 4 },
  93. { 0x4, "SAMD10D13ASU", 8, 4 },
  94. { 0x5, "SAMD10D12ASU", 4, 4 },
  95. { 0x6, "SAMD10C14A", 16, 4 },
  96. { 0x7, "SAMD10C13A", 8, 4 },
  97. { 0x8, "SAMD10C12A", 4, 4 },
  98. };
  99. /* Known SAMD11 parts */
  100. static const struct samd_part samd11_parts[] = {
  101. { 0x0, "SAMD11D14AM", 16, 4 },
  102. { 0x1, "SAMD11D13AMU", 8, 4 },
  103. { 0x2, "SAMD11D12AMU", 4, 4 },
  104. { 0x3, "SAMD11D14ASS", 16, 4 },
  105. { 0x4, "SAMD11D13ASU", 8, 4 },
  106. { 0x5, "SAMD11D12ASU", 4, 4 },
  107. { 0x6, "SAMD11C14A", 16, 4 },
  108. { 0x7, "SAMD11C13A", 8, 4 },
  109. { 0x8, "SAMD11C12A", 4, 4 },
  110. { 0x9, "SAMD11D14AU", 16, 4 },
  111. };
  112. /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
  113. static const struct samd_part samd20_parts[] = {
  114. { 0x0, "SAMD20J18A", 256, 32 },
  115. { 0x1, "SAMD20J17A", 128, 16 },
  116. { 0x2, "SAMD20J16A", 64, 8 },
  117. { 0x3, "SAMD20J15A", 32, 4 },
  118. { 0x4, "SAMD20J14A", 16, 2 },
  119. { 0x5, "SAMD20G18A", 256, 32 },
  120. { 0x6, "SAMD20G17A", 128, 16 },
  121. { 0x7, "SAMD20G16A", 64, 8 },
  122. { 0x8, "SAMD20G15A", 32, 4 },
  123. { 0x9, "SAMD20G14A", 16, 2 },
  124. { 0xA, "SAMD20E18A", 256, 32 },
  125. { 0xB, "SAMD20E17A", 128, 16 },
  126. { 0xC, "SAMD20E16A", 64, 8 },
  127. { 0xD, "SAMD20E15A", 32, 4 },
  128. { 0xE, "SAMD20E14A", 16, 2 },
  129. };
  130. /* Known SAMD21 parts. */
  131. static const struct samd_part samd21_parts[] = {
  132. { 0x0, "SAMD21J18A", 256, 32 },
  133. { 0x1, "SAMD21J17A", 128, 16 },
  134. { 0x2, "SAMD21J16A", 64, 8 },
  135. { 0x3, "SAMD21J15A", 32, 4 },
  136. { 0x4, "SAMD21J14A", 16, 2 },
  137. { 0x5, "SAMD21G18A", 256, 32 },
  138. { 0x6, "SAMD21G17A", 128, 16 },
  139. { 0x7, "SAMD21G16A", 64, 8 },
  140. { 0x8, "SAMD21G15A", 32, 4 },
  141. { 0x9, "SAMD21G14A", 16, 2 },
  142. { 0xA, "SAMD21E18A", 256, 32 },
  143. { 0xB, "SAMD21E17A", 128, 16 },
  144. { 0xC, "SAMD21E16A", 64, 8 },
  145. { 0xD, "SAMD21E15A", 32, 4 },
  146. { 0xE, "SAMD21E14A", 16, 2 },
  147. /* SAMR21 parts have integrated SAMD21 with a radio */
  148. { 0x18, "SAMR21G19A", 256, 32 }, /* with 512k of serial flash */
  149. { 0x19, "SAMR21G18A", 256, 32 },
  150. { 0x1A, "SAMR21G17A", 128, 32 },
  151. { 0x1B, "SAMR21G16A", 64, 16 },
  152. { 0x1C, "SAMR21E18A", 256, 32 },
  153. { 0x1D, "SAMR21E17A", 128, 32 },
  154. { 0x1E, "SAMR21E16A", 64, 16 },
  155. /* SAMD21 B Variants (Table 3-7 from rev I of datasheet) */
  156. { 0x20, "SAMD21J16B", 64, 8 },
  157. { 0x21, "SAMD21J15B", 32, 4 },
  158. { 0x23, "SAMD21G16B", 64, 8 },
  159. { 0x24, "SAMD21G15B", 32, 4 },
  160. { 0x26, "SAMD21E16B", 64, 8 },
  161. { 0x27, "SAMD21E15B", 32, 4 },
  162. /* SAMD21 D and L Variants (from Errata)
  163. http://ww1.microchip.com/downloads/en/DeviceDoc/
  164. SAM-D21-Family-Silicon-Errata-and-DataSheet-Clarification-DS80000760D.pdf */
  165. { 0x55, "SAMD21E16BU", 64, 8 },
  166. { 0x56, "SAMD21E15BU", 32, 4 },
  167. { 0x57, "SAMD21G16L", 64, 8 },
  168. { 0x3E, "SAMD21E16L", 64, 8 },
  169. { 0x3F, "SAMD21E15L", 32, 4 },
  170. { 0x62, "SAMD21E16CU", 64, 8 },
  171. { 0x63, "SAMD21E15CU", 32, 4 },
  172. { 0x92, "SAMD21J17D", 128, 16 },
  173. { 0x93, "SAMD21G17D", 128, 16 },
  174. { 0x94, "SAMD21E17D", 128, 16 },
  175. { 0x95, "SAMD21E17DU", 128, 16 },
  176. { 0x96, "SAMD21G17L", 128, 16 },
  177. { 0x97, "SAMD21E17L", 128, 16 },
  178. /* Known SAMDA1 parts.
  179. SAMD-A1 series uses the same series identifier like the SAMD21
  180. taken from http://ww1.microchip.com/downloads/en/DeviceDoc/40001895A.pdf (pages 14-17) */
  181. { 0x29, "SAMDA1J16A", 64, 8 },
  182. { 0x2A, "SAMDA1J15A", 32, 4 },
  183. { 0x2B, "SAMDA1J14A", 16, 4 },
  184. { 0x2C, "SAMDA1G16A", 64, 8 },
  185. { 0x2D, "SAMDA1G15A", 32, 4 },
  186. { 0x2E, "SAMDA1G14A", 16, 4 },
  187. { 0x2F, "SAMDA1E16A", 64, 8 },
  188. { 0x30, "SAMDA1E15A", 32, 4 },
  189. { 0x31, "SAMDA1E14A", 16, 4 },
  190. { 0x64, "SAMDA1J16B", 64, 8 },
  191. { 0x65, "SAMDA1J15B", 32, 4 },
  192. { 0x66, "SAMDA1J14B", 16, 4 },
  193. { 0x67, "SAMDA1G16B", 64, 8 },
  194. { 0x68, "SAMDA1G15B", 32, 4 },
  195. { 0x69, "SAMDA1G14B", 16, 4 },
  196. { 0x6A, "SAMDA1E16B", 64, 8 },
  197. { 0x6B, "SAMDA1E15B", 32, 4 },
  198. { 0x6C, "SAMDA1E14B", 16, 4 },
  199. };
  200. /* Known SAML21 parts. */
  201. static const struct samd_part saml21_parts[] = {
  202. { 0x00, "SAML21J18A", 256, 32 },
  203. { 0x01, "SAML21J17A", 128, 16 },
  204. { 0x02, "SAML21J16A", 64, 8 },
  205. { 0x05, "SAML21G18A", 256, 32 },
  206. { 0x06, "SAML21G17A", 128, 16 },
  207. { 0x07, "SAML21G16A", 64, 8 },
  208. { 0x0A, "SAML21E18A", 256, 32 },
  209. { 0x0B, "SAML21E17A", 128, 16 },
  210. { 0x0C, "SAML21E16A", 64, 8 },
  211. { 0x0D, "SAML21E15A", 32, 4 },
  212. { 0x0F, "SAML21J18B", 256, 32 },
  213. { 0x10, "SAML21J17B", 128, 16 },
  214. { 0x11, "SAML21J16B", 64, 8 },
  215. { 0x14, "SAML21G18B", 256, 32 },
  216. { 0x15, "SAML21G17B", 128, 16 },
  217. { 0x16, "SAML21G16B", 64, 8 },
  218. { 0x19, "SAML21E18B", 256, 32 },
  219. { 0x1A, "SAML21E17B", 128, 16 },
  220. { 0x1B, "SAML21E16B", 64, 8 },
  221. { 0x1C, "SAML21E15B", 32, 4 },
  222. /* SAMR30 parts have integrated SAML21 with a radio */
  223. { 0x1E, "SAMR30G18A", 256, 32 },
  224. { 0x1F, "SAMR30E18A", 256, 32 },
  225. /* SAMR34/R35 parts have integrated SAML21 with a lora radio */
  226. { 0x28, "SAMR34J18", 256, 32 },
  227. };
  228. /* Known SAML22 parts. */
  229. static const struct samd_part saml22_parts[] = {
  230. { 0x00, "SAML22N18A", 256, 32 },
  231. { 0x01, "SAML22N17A", 128, 16 },
  232. { 0x02, "SAML22N16A", 64, 8 },
  233. { 0x05, "SAML22J18A", 256, 32 },
  234. { 0x06, "SAML22J17A", 128, 16 },
  235. { 0x07, "SAML22J16A", 64, 8 },
  236. { 0x0A, "SAML22G18A", 256, 32 },
  237. { 0x0B, "SAML22G17A", 128, 16 },
  238. { 0x0C, "SAML22G16A", 64, 8 },
  239. };
  240. /* Known SAMC20 parts. */
  241. static const struct samd_part samc20_parts[] = {
  242. { 0x00, "SAMC20J18A", 256, 32 },
  243. { 0x01, "SAMC20J17A", 128, 16 },
  244. { 0x02, "SAMC20J16A", 64, 8 },
  245. { 0x03, "SAMC20J15A", 32, 4 },
  246. { 0x05, "SAMC20G18A", 256, 32 },
  247. { 0x06, "SAMC20G17A", 128, 16 },
  248. { 0x07, "SAMC20G16A", 64, 8 },
  249. { 0x08, "SAMC20G15A", 32, 4 },
  250. { 0x0A, "SAMC20E18A", 256, 32 },
  251. { 0x0B, "SAMC20E17A", 128, 16 },
  252. { 0x0C, "SAMC20E16A", 64, 8 },
  253. { 0x0D, "SAMC20E15A", 32, 4 },
  254. { 0x20, "SAMC20N18A", 256, 32 },
  255. { 0x21, "SAMC20N17A", 128, 16 },
  256. };
  257. /* Known SAMC21 parts. */
  258. static const struct samd_part samc21_parts[] = {
  259. { 0x00, "SAMC21J18A", 256, 32 },
  260. { 0x01, "SAMC21J17A", 128, 16 },
  261. { 0x02, "SAMC21J16A", 64, 8 },
  262. { 0x03, "SAMC21J15A", 32, 4 },
  263. { 0x05, "SAMC21G18A", 256, 32 },
  264. { 0x06, "SAMC21G17A", 128, 16 },
  265. { 0x07, "SAMC21G16A", 64, 8 },
  266. { 0x08, "SAMC21G15A", 32, 4 },
  267. { 0x0A, "SAMC21E18A", 256, 32 },
  268. { 0x0B, "SAMC21E17A", 128, 16 },
  269. { 0x0C, "SAMC21E16A", 64, 8 },
  270. { 0x0D, "SAMC21E15A", 32, 4 },
  271. { 0x20, "SAMC21N18A", 256, 32 },
  272. { 0x21, "SAMC21N17A", 128, 16 },
  273. };
  274. /* Each family of parts contains a parts table in the DEVSEL field of DID. The
  275. * processor ID, family ID, and series ID are used to determine which exact
  276. * family this is and then we can use the corresponding table. */
  277. struct samd_family {
  278. uint8_t processor;
  279. uint8_t family;
  280. uint8_t series;
  281. const struct samd_part *parts;
  282. size_t num_parts;
  283. uint64_t nvm_userrow_res_mask; /* protect bits which are reserved, 0 -> protect */
  284. };
  285. /* Known SAMD families */
  286. static const struct samd_family samd_families[] = {
  287. { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20,
  288. samd20_parts, ARRAY_SIZE(samd20_parts),
  289. (uint64_t)0xFFFF01FFFE01FF77 },
  290. { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
  291. samd21_parts, ARRAY_SIZE(samd21_parts),
  292. (uint64_t)0xFFFF01FFFE01FF77 },
  293. { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_09,
  294. samd09_parts, ARRAY_SIZE(samd09_parts),
  295. (uint64_t)0xFFFF01FFFE01FF77 },
  296. { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_10,
  297. samd10_parts, ARRAY_SIZE(samd10_parts),
  298. (uint64_t)0xFFFF01FFFE01FF77 },
  299. { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11,
  300. samd11_parts, ARRAY_SIZE(samd11_parts),
  301. (uint64_t)0xFFFF01FFFE01FF77 },
  302. { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_21,
  303. saml21_parts, ARRAY_SIZE(saml21_parts),
  304. (uint64_t)0xFFFF03FFFC01FF77 },
  305. { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_22,
  306. saml22_parts, ARRAY_SIZE(saml22_parts),
  307. (uint64_t)0xFFFF03FFFC01FF77 },
  308. { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_20,
  309. samc20_parts, ARRAY_SIZE(samc20_parts),
  310. (uint64_t)0xFFFF03FFFC01FF77 },
  311. { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_21,
  312. samc21_parts, ARRAY_SIZE(samc21_parts),
  313. (uint64_t)0xFFFF03FFFC01FF77 },
  314. };
  315. struct samd_info {
  316. uint32_t page_size;
  317. int num_pages;
  318. int sector_size;
  319. int prot_block_size;
  320. bool probed;
  321. struct target *target;
  322. };
  323. /**
  324. * Gives the family structure to specific device id.
  325. * @param id The id of the device.
  326. * @return On failure NULL, otherwise a pointer to the structure.
  327. */
  328. static const struct samd_family *samd_find_family(uint32_t id)
  329. {
  330. uint8_t processor = SAMD_GET_PROCESSOR(id);
  331. uint8_t family = SAMD_GET_FAMILY(id);
  332. uint8_t series = SAMD_GET_SERIES(id);
  333. for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
  334. if (samd_families[i].processor == processor &&
  335. samd_families[i].series == series &&
  336. samd_families[i].family == family)
  337. return &samd_families[i];
  338. }
  339. return NULL;
  340. }
  341. /**
  342. * Gives the part structure to specific device id.
  343. * @param id The id of the device.
  344. * @return On failure NULL, otherwise a pointer to the structure.
  345. */
  346. static const struct samd_part *samd_find_part(uint32_t id)
  347. {
  348. uint8_t devsel = SAMD_GET_DEVSEL(id);
  349. const struct samd_family *family = samd_find_family(id);
  350. if (!family)
  351. return NULL;
  352. for (unsigned i = 0; i < family->num_parts; i++) {
  353. if (family->parts[i].id == devsel)
  354. return &family->parts[i];
  355. }
  356. return NULL;
  357. }
  358. static int samd_protect_check(struct flash_bank *bank)
  359. {
  360. int res;
  361. uint16_t lock;
  362. res = target_read_u16(bank->target,
  363. SAMD_NVMCTRL + SAMD_NVMCTRL_LOCK, &lock);
  364. if (res != ERROR_OK)
  365. return res;
  366. /* Lock bits are active-low */
  367. for (unsigned int prot_block = 0; prot_block < bank->num_prot_blocks; prot_block++)
  368. bank->prot_blocks[prot_block].is_protected = !(lock & (1u<<prot_block));
  369. return ERROR_OK;
  370. }
  371. static int samd_get_flash_page_info(struct target *target,
  372. uint32_t *sizep, int *nump)
  373. {
  374. int res;
  375. uint32_t param;
  376. res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, &param);
  377. if (res == ERROR_OK) {
  378. /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n)
  379. * so 0 is 8KB and 7 is 1024KB. */
  380. if (sizep)
  381. *sizep = (8 << ((param >> 16) & 0x7));
  382. /* The NVMP field (bits 15:0) indicates the total number of pages */
  383. if (nump)
  384. *nump = param & 0xFFFF;
  385. } else {
  386. LOG_ERROR("Couldn't read NVM Parameters register");
  387. }
  388. return res;
  389. }
  390. static int samd_probe(struct flash_bank *bank)
  391. {
  392. uint32_t id;
  393. int res;
  394. struct samd_info *chip = (struct samd_info *)bank->driver_priv;
  395. const struct samd_part *part;
  396. if (chip->probed)
  397. return ERROR_OK;
  398. res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
  399. if (res != ERROR_OK) {
  400. LOG_ERROR("Couldn't read Device ID register");
  401. return res;
  402. }
  403. part = samd_find_part(id);
  404. if (!part) {
  405. LOG_ERROR("Couldn't find part corresponding to DID %08" PRIx32, id);
  406. return ERROR_FAIL;
  407. }
  408. bank->size = part->flash_kb * 1024;
  409. res = samd_get_flash_page_info(bank->target, &chip->page_size,
  410. &chip->num_pages);
  411. if (res != ERROR_OK) {
  412. LOG_ERROR("Couldn't determine Flash page size");
  413. return res;
  414. }
  415. /* Sanity check: the total flash size in the DSU should match the page size
  416. * multiplied by the number of pages. */
  417. if (bank->size != chip->num_pages * chip->page_size) {
  418. LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
  419. "Identified %" PRIu32 "KB Flash but NVMCTRL reports %u %" PRIu32 "B pages",
  420. part->flash_kb, chip->num_pages, chip->page_size);
  421. }
  422. /* Erase granularity = 1 row = 4 pages */
  423. chip->sector_size = chip->page_size * 4;
  424. /* Allocate the sector table */
  425. bank->num_sectors = chip->num_pages / 4;
  426. bank->sectors = alloc_block_array(0, chip->sector_size, bank->num_sectors);
  427. if (!bank->sectors)
  428. return ERROR_FAIL;
  429. /* 16 protection blocks per device */
  430. chip->prot_block_size = bank->size / SAMD_NUM_PROT_BLOCKS;
  431. /* Allocate the table of protection blocks */
  432. bank->num_prot_blocks = SAMD_NUM_PROT_BLOCKS;
  433. bank->prot_blocks = alloc_block_array(0, chip->prot_block_size, bank->num_prot_blocks);
  434. if (!bank->prot_blocks)
  435. return ERROR_FAIL;
  436. samd_protect_check(bank);
  437. /* Done */
  438. chip->probed = true;
  439. LOG_INFO("SAMD MCU: %s (%" PRIu32 "KB Flash, %" PRIu32 "KB RAM)", part->name,
  440. part->flash_kb, part->ram_kb);
  441. return ERROR_OK;
  442. }
  443. static int samd_check_error(struct target *target)
  444. {
  445. int ret, ret2;
  446. uint16_t status;
  447. ret = target_read_u16(target,
  448. SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status);
  449. if (ret != ERROR_OK) {
  450. LOG_ERROR("Can't read NVM status");
  451. return ret;
  452. }
  453. if ((status & 0x001C) == 0)
  454. return ERROR_OK;
  455. if (status & (1 << 4)) { /* NVME */
  456. LOG_ERROR("SAMD: NVM Error");
  457. ret = ERROR_FLASH_OPERATION_FAILED;
  458. }
  459. if (status & (1 << 3)) { /* LOCKE */
  460. LOG_ERROR("SAMD: NVM lock error");
  461. ret = ERROR_FLASH_PROTECTED;
  462. }
  463. if (status & (1 << 2)) { /* PROGE */
  464. LOG_ERROR("SAMD: NVM programming error");
  465. ret = ERROR_FLASH_OPER_UNSUPPORTED;
  466. }
  467. /* Clear the error conditions by writing a one to them */
  468. ret2 = target_write_u16(target,
  469. SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, status);
  470. if (ret2 != ERROR_OK)
  471. LOG_ERROR("Can't clear NVM error conditions");
  472. return ret;
  473. }
  474. static int samd_issue_nvmctrl_command(struct target *target, uint16_t cmd)
  475. {
  476. int res;
  477. if (target->state != TARGET_HALTED) {
  478. LOG_ERROR("Target not halted");
  479. return ERROR_TARGET_NOT_HALTED;
  480. }
  481. /* Issue the NVM command */
  482. res = target_write_u16(target,
  483. SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, SAMD_NVM_CMD(cmd));
  484. if (res != ERROR_OK)
  485. return res;
  486. /* Check to see if the NVM command resulted in an error condition. */
  487. return samd_check_error(target);
  488. }
  489. /**
  490. * Erases a flash-row at the given address.
  491. * @param target Pointer to the target structure.
  492. * @param address The address of the row.
  493. * @return On success ERROR_OK, on failure an errorcode.
  494. */
  495. static int samd_erase_row(struct target *target, uint32_t address)
  496. {
  497. int res;
  498. /* Set an address contained in the row to be erased */
  499. res = target_write_u32(target,
  500. SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, address >> 1);
  501. /* Issue the Erase Row command to erase that row. */
  502. if (res == ERROR_OK)
  503. res = samd_issue_nvmctrl_command(target,
  504. address == SAMD_USER_ROW ? SAMD_NVM_CMD_EAR : SAMD_NVM_CMD_ER);
  505. if (res != ERROR_OK) {
  506. LOG_ERROR("Failed to erase row containing %08" PRIx32, address);
  507. return ERROR_FAIL;
  508. }
  509. return ERROR_OK;
  510. }
  511. /**
  512. * Returns the bitmask of reserved bits in register.
  513. * @param target Pointer to the target structure.
  514. * @param mask Bitmask, 0 -> value stays untouched.
  515. * @return On success ERROR_OK, on failure an errorcode.
  516. */
  517. static int samd_get_reservedmask(struct target *target, uint64_t *mask)
  518. {
  519. int res;
  520. /* Get the devicetype */
  521. uint32_t id;
  522. res = target_read_u32(target, SAMD_DSU + SAMD_DSU_DID, &id);
  523. if (res != ERROR_OK) {
  524. LOG_ERROR("Couldn't read Device ID register");
  525. return res;
  526. }
  527. const struct samd_family *family;
  528. family = samd_find_family(id);
  529. if (!family) {
  530. LOG_ERROR("Couldn't determine device family");
  531. return ERROR_FAIL;
  532. }
  533. *mask = family->nvm_userrow_res_mask;
  534. return ERROR_OK;
  535. }
  536. static int read_userrow(struct target *target, uint64_t *userrow)
  537. {
  538. int res;
  539. uint8_t buffer[8];
  540. res = target_read_memory(target, SAMD_USER_ROW, 4, 2, buffer);
  541. if (res != ERROR_OK)
  542. return res;
  543. *userrow = target_buffer_get_u64(target, buffer);
  544. return ERROR_OK;
  545. }
  546. /**
  547. * Modify the contents of the User Row in Flash. The User Row itself
  548. * has a size of one page and contains a combination of "fuses" and
  549. * calibration data. Bits which have a value of zero in the mask will
  550. * not be changed. Up to now devices only use the first 64 bits.
  551. * @param target Pointer to the target structure.
  552. * @param value_input The value to write.
  553. * @param value_mask Bitmask, 0 -> value stays untouched.
  554. * @return On success ERROR_OK, on failure an errorcode.
  555. */
  556. static int samd_modify_user_row_masked(struct target *target,
  557. uint64_t value_input, uint64_t value_mask)
  558. {
  559. int res;
  560. uint32_t nvm_ctrlb;
  561. bool manual_wp = true;
  562. /* Retrieve the MCU's page size, in bytes. This is also the size of the
  563. * entire User Row. */
  564. uint32_t page_size;
  565. res = samd_get_flash_page_info(target, &page_size, NULL);
  566. if (res != ERROR_OK) {
  567. LOG_ERROR("Couldn't determine Flash page size");
  568. return res;
  569. }
  570. /* Make sure the size is sane. */
  571. assert(page_size <= SAMD_PAGE_SIZE_MAX &&
  572. page_size >= sizeof(value_input));
  573. uint8_t buf[SAMD_PAGE_SIZE_MAX];
  574. /* Read the user row (comprising one page) by words. */
  575. res = target_read_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
  576. if (res != ERROR_OK)
  577. return res;
  578. uint64_t value_device;
  579. res = read_userrow(target, &value_device);
  580. if (res != ERROR_OK)
  581. return res;
  582. uint64_t value_new = (value_input & value_mask) | (value_device & ~value_mask);
  583. /* We will need to erase before writing if the new value needs a '1' in any
  584. * position for which the current value had a '0'. Otherwise we can avoid
  585. * erasing. */
  586. if ((~value_device) & value_new) {
  587. res = samd_erase_row(target, SAMD_USER_ROW);
  588. if (res != ERROR_OK) {
  589. LOG_ERROR("Couldn't erase user row");
  590. return res;
  591. }
  592. }
  593. /* Modify */
  594. target_buffer_set_u64(target, buf, value_new);
  595. /* Write the page buffer back out to the target. */
  596. res = target_write_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
  597. if (res != ERROR_OK)
  598. return res;
  599. /* Check if we need to do manual page write commands */
  600. res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
  601. if (res == ERROR_OK)
  602. manual_wp = (nvm_ctrlb & SAMD_NVM_CTRLB_MANW) != 0;
  603. else {
  604. LOG_ERROR("Read of NVM register CTRKB failed.");
  605. return ERROR_FAIL;
  606. }
  607. if (manual_wp) {
  608. /* Trigger flash write */
  609. res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_WAP);
  610. } else {
  611. res = samd_check_error(target);
  612. }
  613. return res;
  614. }
  615. /**
  616. * Modifies the user row register to the given value.
  617. * @param target Pointer to the target structure.
  618. * @param value The value to write.
  619. * @param startb The bit-offset by which the given value is shifted.
  620. * @param endb The bit-offset of the last bit in value to write.
  621. * @return On success ERROR_OK, on failure an errorcode.
  622. */
  623. static int samd_modify_user_row(struct target *target, uint64_t value,
  624. uint8_t startb, uint8_t endb)
  625. {
  626. uint64_t mask = 0;
  627. int i;
  628. for (i = startb ; i <= endb ; i++)
  629. mask |= ((uint64_t)1) << i;
  630. return samd_modify_user_row_masked(target, value << startb, mask);
  631. }
  632. static int samd_protect(struct flash_bank *bank, int set,
  633. unsigned int first, unsigned int last)
  634. {
  635. int res = ERROR_OK;
  636. /* We can issue lock/unlock region commands with the target running but
  637. * the settings won't persist unless we're able to modify the LOCK regions
  638. * and that requires the target to be halted. */
  639. if (bank->target->state != TARGET_HALTED) {
  640. LOG_ERROR("Target not halted");
  641. return ERROR_TARGET_NOT_HALTED;
  642. }
  643. for (unsigned int prot_block = first; prot_block <= last; prot_block++) {
  644. if (set != bank->prot_blocks[prot_block].is_protected) {
  645. /* Load an address that is within this protection block (we use offset 0) */
  646. res = target_write_u32(bank->target,
  647. SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR,
  648. bank->prot_blocks[prot_block].offset >> 1);
  649. if (res != ERROR_OK)
  650. goto exit;
  651. /* Tell the controller to lock that block */
  652. res = samd_issue_nvmctrl_command(bank->target,
  653. set ? SAMD_NVM_CMD_LR : SAMD_NVM_CMD_UR);
  654. if (res != ERROR_OK)
  655. goto exit;
  656. }
  657. }
  658. /* We've now applied our changes, however they will be undone by the next
  659. * reset unless we also apply them to the LOCK bits in the User Page. The
  660. * LOCK bits start at bit 48, corresponding to Sector 0 and end with bit 63,
  661. * corresponding to Sector 15. A '1' means unlocked and a '0' means
  662. * locked. See Table 9-3 in the SAMD20 datasheet for more details. */
  663. res = samd_modify_user_row(bank->target,
  664. set ? (uint64_t)0 : (uint64_t)UINT64_MAX,
  665. 48 + first, 48 + last);
  666. if (res != ERROR_OK)
  667. LOG_WARNING("SAMD: protect settings were not made persistent!");
  668. res = ERROR_OK;
  669. exit:
  670. samd_protect_check(bank);
  671. return res;
  672. }
  673. static int samd_erase(struct flash_bank *bank, unsigned int first,
  674. unsigned int last)
  675. {
  676. int res;
  677. struct samd_info *chip = (struct samd_info *)bank->driver_priv;
  678. if (bank->target->state != TARGET_HALTED) {
  679. LOG_ERROR("Target not halted");
  680. return ERROR_TARGET_NOT_HALTED;
  681. }
  682. if (!chip->probed) {
  683. if (samd_probe(bank) != ERROR_OK)
  684. return ERROR_FLASH_BANK_NOT_PROBED;
  685. }
  686. /* For each sector to be erased */
  687. for (unsigned int s = first; s <= last; s++) {
  688. res = samd_erase_row(bank->target, bank->sectors[s].offset);
  689. if (res != ERROR_OK) {
  690. LOG_ERROR("SAMD: failed to erase sector %d at 0x%08" PRIx32, s, bank->sectors[s].offset);
  691. return res;
  692. }
  693. }
  694. return ERROR_OK;
  695. }
  696. static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
  697. uint32_t offset, uint32_t count)
  698. {
  699. int res;
  700. uint32_t nvm_ctrlb;
  701. uint32_t address;
  702. uint32_t pg_offset;
  703. uint32_t nb;
  704. uint32_t nw;
  705. struct samd_info *chip = (struct samd_info *)bank->driver_priv;
  706. uint8_t *pb = NULL;
  707. bool manual_wp;
  708. if (bank->target->state != TARGET_HALTED) {
  709. LOG_ERROR("Target not halted");
  710. return ERROR_TARGET_NOT_HALTED;
  711. }
  712. if (!chip->probed) {
  713. if (samd_probe(bank) != ERROR_OK)
  714. return ERROR_FLASH_BANK_NOT_PROBED;
  715. }
  716. /* Check if we need to do manual page write commands */
  717. res = target_read_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
  718. if (res != ERROR_OK)
  719. return res;
  720. if (nvm_ctrlb & SAMD_NVM_CTRLB_MANW)
  721. manual_wp = true;
  722. else
  723. manual_wp = false;
  724. res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_PBC);
  725. if (res != ERROR_OK) {
  726. LOG_ERROR("%s: %d", __func__, __LINE__);
  727. return res;
  728. }
  729. while (count) {
  730. nb = chip->page_size - offset % chip->page_size;
  731. if (count < nb)
  732. nb = count;
  733. address = bank->base + offset;
  734. pg_offset = offset % chip->page_size;
  735. if (offset % 4 || (offset + nb) % 4) {
  736. /* Either start or end of write is not word aligned */
  737. if (!pb) {
  738. pb = malloc(chip->page_size);
  739. if (!pb)
  740. return ERROR_FAIL;
  741. }
  742. /* Set temporary page buffer to 0xff and overwrite the relevant part */
  743. memset(pb, 0xff, chip->page_size);
  744. memcpy(pb + pg_offset, buffer, nb);
  745. /* Align start address to a word boundary */
  746. address -= offset % 4;
  747. pg_offset -= offset % 4;
  748. assert(pg_offset % 4 == 0);
  749. /* Extend length to whole words */
  750. nw = (nb + offset % 4 + 3) / 4;
  751. assert(pg_offset + 4 * nw <= chip->page_size);
  752. /* Now we have original data extended by 0xff bytes
  753. * to the nearest word boundary on both start and end */
  754. res = target_write_memory(bank->target, address, 4, nw, pb + pg_offset);
  755. } else {
  756. assert(nb % 4 == 0);
  757. nw = nb / 4;
  758. assert(pg_offset + 4 * nw <= chip->page_size);
  759. /* Word aligned data, use direct write from buffer */
  760. res = target_write_memory(bank->target, address, 4, nw, buffer);
  761. }
  762. if (res != ERROR_OK) {
  763. LOG_ERROR("%s: %d", __func__, __LINE__);
  764. goto free_pb;
  765. }
  766. /* Devices with errata 13134 have automatic page write enabled by default
  767. * For other devices issue a write page CMD to the NVM
  768. * If the page has not been written up to the last word
  769. * then issue CMD_WP always */
  770. if (manual_wp || pg_offset + 4 * nw < chip->page_size) {
  771. res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_WP);
  772. } else {
  773. /* Access through AHB is stalled while flash is being programmed */
  774. usleep(200);
  775. res = samd_check_error(bank->target);
  776. }
  777. if (res != ERROR_OK) {
  778. LOG_ERROR("%s: write failed at address 0x%08" PRIx32, __func__, address);
  779. goto free_pb;
  780. }
  781. /* We're done with the page contents */
  782. count -= nb;
  783. offset += nb;
  784. buffer += nb;
  785. }
  786. free_pb:
  787. free(pb);
  788. return res;
  789. }
  790. FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
  791. {
  792. if (bank->base != SAMD_FLASH) {
  793. LOG_ERROR("Address " TARGET_ADDR_FMT
  794. " invalid bank address (try 0x%08" PRIx32
  795. "[at91samd series] )",
  796. bank->base, SAMD_FLASH);
  797. return ERROR_FAIL;
  798. }
  799. struct samd_info *chip;
  800. chip = calloc(1, sizeof(*chip));
  801. if (!chip) {
  802. LOG_ERROR("No memory for flash bank chip info");
  803. return ERROR_FAIL;
  804. }
  805. chip->target = bank->target;
  806. chip->probed = false;
  807. bank->driver_priv = chip;
  808. return ERROR_OK;
  809. }
  810. COMMAND_HANDLER(samd_handle_info_command)
  811. {
  812. return ERROR_OK;
  813. }
  814. COMMAND_HANDLER(samd_handle_chip_erase_command)
  815. {
  816. struct target *target = get_current_target(CMD_CTX);
  817. int res = ERROR_FAIL;
  818. if (target) {
  819. /* Enable access to the DSU by disabling the write protect bit */
  820. target_write_u32(target, SAMD_PAC1, (1<<1));
  821. /* intentionally without error checking - not accessible on secured chip */
  822. /* Tell the DSU to perform a full chip erase. It takes about 240ms to
  823. * perform the erase. */
  824. res = target_write_u8(target, SAMD_DSU + SAMD_DSU_CTRL_EXT, (1<<4));
  825. if (res == ERROR_OK)
  826. command_print(CMD, "chip erase started");
  827. else
  828. command_print(CMD, "write to DSU CTRL failed");
  829. }
  830. return res;
  831. }
  832. COMMAND_HANDLER(samd_handle_set_security_command)
  833. {
  834. int res = ERROR_OK;
  835. struct target *target = get_current_target(CMD_CTX);
  836. if (CMD_ARGC < 1 || (CMD_ARGC >= 1 && (strcmp(CMD_ARGV[0], "enable")))) {
  837. command_print(CMD, "supply the \"enable\" argument to proceed.");
  838. return ERROR_COMMAND_SYNTAX_ERROR;
  839. }
  840. if (target) {
  841. if (target->state != TARGET_HALTED) {
  842. LOG_ERROR("Target not halted");
  843. return ERROR_TARGET_NOT_HALTED;
  844. }
  845. res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_SSB);
  846. /* Check (and clear) error conditions */
  847. if (res == ERROR_OK)
  848. command_print(CMD, "chip secured on next power-cycle");
  849. else
  850. command_print(CMD, "failed to secure chip");
  851. }
  852. return res;
  853. }
  854. COMMAND_HANDLER(samd_handle_eeprom_command)
  855. {
  856. int res = ERROR_OK;
  857. struct target *target = get_current_target(CMD_CTX);
  858. if (target) {
  859. if (target->state != TARGET_HALTED) {
  860. LOG_ERROR("Target not halted");
  861. return ERROR_TARGET_NOT_HALTED;
  862. }
  863. if (CMD_ARGC >= 1) {
  864. int val = atoi(CMD_ARGV[0]);
  865. uint32_t code;
  866. if (val == 0)
  867. code = 7;
  868. else {
  869. /* Try to match size in bytes with corresponding size code */
  870. for (code = 0; code <= 6; code++) {
  871. if (val == (2 << (13 - code)))
  872. break;
  873. }
  874. if (code > 6) {
  875. command_print(CMD, "Invalid EEPROM size. Please see "
  876. "datasheet for a list valid sizes.");
  877. return ERROR_COMMAND_SYNTAX_ERROR;
  878. }
  879. }
  880. res = samd_modify_user_row(target, code, 4, 6);
  881. } else {
  882. uint16_t val;
  883. res = target_read_u16(target, SAMD_USER_ROW, &val);
  884. if (res == ERROR_OK) {
  885. uint32_t size = ((val >> 4) & 0x7); /* grab size code */
  886. if (size == 0x7)
  887. command_print(CMD, "EEPROM is disabled");
  888. else {
  889. /* Otherwise, 6 is 256B, 0 is 16KB */
  890. command_print(CMD, "EEPROM size is %u bytes",
  891. (2 << (13 - size)));
  892. }
  893. }
  894. }
  895. }
  896. return res;
  897. }
  898. COMMAND_HANDLER(samd_handle_nvmuserrow_command)
  899. {
  900. int res = ERROR_OK;
  901. struct target *target = get_current_target(CMD_CTX);
  902. if (target) {
  903. if (CMD_ARGC > 2) {
  904. command_print(CMD, "Too much Arguments given.");
  905. return ERROR_COMMAND_SYNTAX_ERROR;
  906. }
  907. if (CMD_ARGC > 0) {
  908. if (target->state != TARGET_HALTED) {
  909. LOG_ERROR("Target not halted.");
  910. return ERROR_TARGET_NOT_HALTED;
  911. }
  912. uint64_t mask;
  913. res = samd_get_reservedmask(target, &mask);
  914. if (res != ERROR_OK) {
  915. LOG_ERROR("Couldn't determine the mask for reserved bits.");
  916. return ERROR_FAIL;
  917. }
  918. mask &= NVMUSERROW_LOCKBIT_MASK;
  919. uint64_t value;
  920. COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], value);
  921. if (CMD_ARGC == 2) {
  922. uint64_t mask_temp;
  923. COMMAND_PARSE_NUMBER(u64, CMD_ARGV[1], mask_temp);
  924. mask &= mask_temp;
  925. }
  926. res = samd_modify_user_row_masked(target, value, mask);
  927. if (res != ERROR_OK)
  928. return res;
  929. }
  930. /* read register */
  931. uint64_t value;
  932. res = read_userrow(target, &value);
  933. if (res == ERROR_OK)
  934. command_print(CMD, "NVMUSERROW: 0x%016"PRIX64, value);
  935. else
  936. LOG_ERROR("NVMUSERROW could not be read.");
  937. }
  938. return res;
  939. }
  940. COMMAND_HANDLER(samd_handle_bootloader_command)
  941. {
  942. int res = ERROR_OK;
  943. struct target *target = get_current_target(CMD_CTX);
  944. if (target) {
  945. if (target->state != TARGET_HALTED) {
  946. LOG_ERROR("Target not halted");
  947. return ERROR_TARGET_NOT_HALTED;
  948. }
  949. /* Retrieve the MCU's page size, in bytes. */
  950. uint32_t page_size;
  951. res = samd_get_flash_page_info(target, &page_size, NULL);
  952. if (res != ERROR_OK) {
  953. LOG_ERROR("Couldn't determine Flash page size");
  954. return res;
  955. }
  956. if (CMD_ARGC >= 1) {
  957. int val = atoi(CMD_ARGV[0]);
  958. uint32_t code;
  959. if (val == 0)
  960. code = 7;
  961. else {
  962. /* Try to match size in bytes with corresponding size code */
  963. for (code = 0; code <= 6; code++) {
  964. if ((unsigned int)val == (2UL << (8UL - code)) * page_size)
  965. break;
  966. }
  967. if (code > 6) {
  968. command_print(CMD, "Invalid bootloader size. Please "
  969. "see datasheet for a list valid sizes.");
  970. return ERROR_COMMAND_SYNTAX_ERROR;
  971. }
  972. }
  973. res = samd_modify_user_row(target, code, 0, 2);
  974. } else {
  975. uint16_t val;
  976. res = target_read_u16(target, SAMD_USER_ROW, &val);
  977. if (res == ERROR_OK) {
  978. uint32_t size = (val & 0x7); /* grab size code */
  979. uint32_t nb;
  980. if (size == 0x7)
  981. nb = 0;
  982. else
  983. nb = (2 << (8 - size)) * page_size;
  984. /* There are 4 pages per row */
  985. command_print(CMD, "Bootloader size is %" PRIu32 " bytes (%" PRIu32 " rows)",
  986. nb, (uint32_t)(nb / (page_size * 4)));
  987. }
  988. }
  989. }
  990. return res;
  991. }
  992. COMMAND_HANDLER(samd_handle_reset_deassert)
  993. {
  994. struct target *target = get_current_target(CMD_CTX);
  995. int retval = ERROR_OK;
  996. enum reset_types jtag_reset_config = jtag_get_reset_config();
  997. /* If the target has been unresponsive before, try to re-establish
  998. * communication now - CPU is held in reset by DSU, DAP is working */
  999. if (!target_was_examined(target))
  1000. target_examine_one(target);
  1001. target_poll(target);
  1002. /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
  1003. * so we just release reset held by DSU
  1004. *
  1005. * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
  1006. *
  1007. * After vectreset DSU release is not needed however makes no harm
  1008. */
  1009. if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
  1010. retval = target_write_u32(target, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
  1011. if (retval == ERROR_OK)
  1012. retval = target_write_u32(target, DCB_DEMCR,
  1013. TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
  1014. /* do not return on error here, releasing DSU reset is more important */
  1015. }
  1016. /* clear CPU Reset Phase Extension bit */
  1017. int retval2 = target_write_u8(target, SAMD_DSU + SAMD_DSU_STATUSA, (1<<1));
  1018. if (retval2 != ERROR_OK)
  1019. return retval2;
  1020. return retval;
  1021. }
  1022. static const struct command_registration at91samd_exec_command_handlers[] = {
  1023. {
  1024. .name = "dsu_reset_deassert",
  1025. .handler = samd_handle_reset_deassert,
  1026. .mode = COMMAND_EXEC,
  1027. .help = "Deassert internal reset held by DSU.",
  1028. .usage = "",
  1029. },
  1030. {
  1031. .name = "info",
  1032. .handler = samd_handle_info_command,
  1033. .mode = COMMAND_EXEC,
  1034. .help = "Print information about the current at91samd chip "
  1035. "and its flash configuration.",
  1036. .usage = "",
  1037. },
  1038. {
  1039. .name = "chip-erase",
  1040. .handler = samd_handle_chip_erase_command,
  1041. .mode = COMMAND_EXEC,
  1042. .help = "Erase the entire Flash by using the Chip-"
  1043. "Erase feature in the Device Service Unit (DSU).",
  1044. .usage = "",
  1045. },
  1046. {
  1047. .name = "set-security",
  1048. .handler = samd_handle_set_security_command,
  1049. .mode = COMMAND_EXEC,
  1050. .help = "Secure the chip's Flash by setting the Security Bit. "
  1051. "This makes it impossible to read the Flash contents. "
  1052. "The only way to undo this is to issue the chip-erase "
  1053. "command.",
  1054. .usage = "'enable'",
  1055. },
  1056. {
  1057. .name = "eeprom",
  1058. .usage = "[size_in_bytes]",
  1059. .handler = samd_handle_eeprom_command,
  1060. .mode = COMMAND_EXEC,
  1061. .help = "Show or set the EEPROM size setting, stored in the User Row. "
  1062. "Please see Table 20-3 of the SAMD20 datasheet for allowed values. "
  1063. "Changes are stored immediately but take affect after the MCU is "
  1064. "reset.",
  1065. },
  1066. {
  1067. .name = "bootloader",
  1068. .usage = "[size_in_bytes]",
  1069. .handler = samd_handle_bootloader_command,
  1070. .mode = COMMAND_EXEC,
  1071. .help = "Show or set the bootloader size, stored in the User Row. "
  1072. "Please see Table 20-2 of the SAMD20 datasheet for allowed values. "
  1073. "Changes are stored immediately but take affect after the MCU is "
  1074. "reset.",
  1075. },
  1076. {
  1077. .name = "nvmuserrow",
  1078. .usage = "[value] [mask]",
  1079. .handler = samd_handle_nvmuserrow_command,
  1080. .mode = COMMAND_EXEC,
  1081. .help = "Show or set the nvmuserrow register. It is 64 bit wide "
  1082. "and located at address 0x804000. Use the optional mask argument "
  1083. "to prevent changes at positions where the bitvalue is zero. "
  1084. "For security reasons the lock- and reserved-bits are masked out "
  1085. "in background and therefore cannot be changed.",
  1086. },
  1087. COMMAND_REGISTRATION_DONE
  1088. };
  1089. static const struct command_registration at91samd_command_handlers[] = {
  1090. {
  1091. .name = "at91samd",
  1092. .mode = COMMAND_ANY,
  1093. .help = "at91samd flash command group",
  1094. .usage = "",
  1095. .chain = at91samd_exec_command_handlers,
  1096. },
  1097. COMMAND_REGISTRATION_DONE
  1098. };
  1099. const struct flash_driver at91samd_flash = {
  1100. .name = "at91samd",
  1101. .commands = at91samd_command_handlers,
  1102. .flash_bank_command = samd_flash_bank_command,
  1103. .erase = samd_erase,
  1104. .protect = samd_protect,
  1105. .write = samd_write,
  1106. .read = default_flash_read,
  1107. .probe = samd_probe,
  1108. .auto_probe = samd_probe,
  1109. .erase_check = default_flash_blank_check,
  1110. .protect_check = samd_protect_check,
  1111. .free_driver_priv = default_flash_free_driver_priv,
  1112. };