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  1. \input texinfo @c -*-texinfo-*-
  2. @c %**start of header
  3. @setfilename openocd.info
  4. @settitle OpenOCD User's Guide
  5. @dircategory Development
  6. @direntry
  7. * OpenOCD: (openocd). OpenOCD User's Guide
  8. @end direntry
  9. @paragraphindent 0
  10. @c %**end of header
  11. @include version.texi
  12. @copying
  13. This User's Guide documents
  14. release @value{VERSION},
  15. dated @value{UPDATED},
  16. of the Open On-Chip Debugger (OpenOCD).
  17. @itemize @bullet
  18. @item Copyright @copyright{} 2008 The OpenOCD Project
  19. @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
  20. @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
  21. @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
  22. @item Copyright @copyright{} 2009-2010 David Brownell
  23. @end itemize
  24. @quotation
  25. Permission is granted to copy, distribute and/or modify this document
  26. under the terms of the GNU Free Documentation License, Version 1.2 or
  27. any later version published by the Free Software Foundation; with no
  28. Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
  29. Texts. A copy of the license is included in the section entitled ``GNU
  30. Free Documentation License''.
  31. @end quotation
  32. @end copying
  33. @titlepage
  34. @titlefont{@emph{Open On-Chip Debugger:}}
  35. @sp 1
  36. @title OpenOCD User's Guide
  37. @subtitle for release @value{VERSION}
  38. @subtitle @value{UPDATED}
  39. @page
  40. @vskip 0pt plus 1filll
  41. @insertcopying
  42. @end titlepage
  43. @summarycontents
  44. @contents
  45. @ifnottex
  46. @node Top
  47. @top OpenOCD User's Guide
  48. @insertcopying
  49. @end ifnottex
  50. @menu
  51. * About:: About OpenOCD
  52. * Developers:: OpenOCD Developer Resources
  53. * Debug Adapter Hardware:: Debug Adapter Hardware
  54. * About Jim-Tcl:: About Jim-Tcl
  55. * Running:: Running OpenOCD
  56. * OpenOCD Project Setup:: OpenOCD Project Setup
  57. * Config File Guidelines:: Config File Guidelines
  58. * Daemon Configuration:: Daemon Configuration
  59. * Debug Adapter Configuration:: Debug Adapter Configuration
  60. * Reset Configuration:: Reset Configuration
  61. * TAP Declaration:: TAP Declaration
  62. * CPU Configuration:: CPU Configuration
  63. * Flash Commands:: Flash Commands
  64. * Flash Programming:: Flash Programming
  65. * NAND Flash Commands:: NAND Flash Commands
  66. * PLD/FPGA Commands:: PLD/FPGA Commands
  67. * General Commands:: General Commands
  68. * Architecture and Core Commands:: Architecture and Core Commands
  69. * JTAG Commands:: JTAG Commands
  70. * Boundary Scan Commands:: Boundary Scan Commands
  71. * TFTP:: TFTP
  72. * GDB and OpenOCD:: Using GDB and OpenOCD
  73. * Tcl Scripting API:: Tcl Scripting API
  74. * FAQ:: Frequently Asked Questions
  75. * Tcl Crash Course:: Tcl Crash Course
  76. * License:: GNU Free Documentation License
  77. @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
  78. @comment case issue with ``Index.html'' and ``index.html''
  79. @comment Occurs when creating ``--html --no-split'' output
  80. @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
  81. * OpenOCD Concept Index:: Concept Index
  82. * Command and Driver Index:: Command and Driver Index
  83. @end menu
  84. @node About
  85. @unnumbered About
  86. @cindex about
  87. OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
  88. University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
  89. Since that time, the project has grown into an active open-source project,
  90. supported by a diverse community of software and hardware developers from
  91. around the world.
  92. @section What is OpenOCD?
  93. @cindex TAP
  94. @cindex JTAG
  95. The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
  96. in-system programming and boundary-scan testing for embedded target
  97. devices.
  98. It does so with the assistance of a @dfn{debug adapter}, which is
  99. a small hardware module which helps provide the right kind of
  100. electrical signaling to the target being debugged. These are
  101. required since the debug host (on which OpenOCD runs) won't
  102. usually have native support for such signaling, or the connector
  103. needed to hook up to the target.
  104. Such debug adapters support one or more @dfn{transport} protocols,
  105. each of which involves different electrical signaling (and uses
  106. different messaging protocols on top of that signaling). There
  107. are many types of debug adapter, and little uniformity in what
  108. they are called. (There are also product naming differences.)
  109. These adapters are sometimes packaged as discrete dongles, which
  110. may generically be called @dfn{hardware interface dongles}.
  111. Some development boards also integrate them directly, which may
  112. let the development board can be directly connected to the debug
  113. host over USB (and sometimes also to power it over USB).
  114. For example, a @dfn{JTAG Adapter} supports JTAG
  115. signaling, and is used to communicate
  116. with JTAG (IEEE 1149.1) compliant TAPs on your target board.
  117. A @dfn{TAP} is a ``Test Access Port'', a module which processes
  118. special instructions and data. TAPs are daisy-chained within and
  119. between chips and boards. JTAG supports debugging and boundary
  120. scan operations.
  121. There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
  122. signaling to communicate with some newer ARM cores, as well as debug
  123. adapters which support both JTAG and SWD transports. SWD only supports
  124. debugging, whereas JTAG also supports boundary scan operations.
  125. For some chips, there are also @dfn{Programming Adapters} supporting
  126. special transports used only to write code to flash memory, without
  127. support for on-chip debugging or boundary scan.
  128. (At this writing, OpenOCD does not support such non-debug adapters.)
  129. @b{Dongles:} OpenOCD currently supports many types of hardware dongles: USB
  130. based, parallel port based, and other standalone boxes that run
  131. OpenOCD internally. @xref{Debug Adapter Hardware}.
  132. @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
  133. ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
  134. Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be
  135. debugged via the GDB protocol.
  136. @b{Flash Programing:} Flash writing is supported for external CFI
  137. compatible NOR flashes (Intel and AMD/Spansion command set) and several
  138. internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3,
  139. STM32x and EFM32). Preliminary support for various NAND flash controllers
  140. (LPC3180, Orion, S3C24xx, more) controller is included.
  141. @section OpenOCD Web Site
  142. The OpenOCD web site provides the latest public news from the community:
  143. @uref{http://openocd.sourceforge.net/}
  144. @section Latest User's Guide:
  145. The user's guide you are now reading may not be the latest one
  146. available. A version for more recent code may be available.
  147. Its HTML form is published regularly at:
  148. @uref{http://openocd.sourceforge.net/doc/html/index.html}
  149. PDF form is likewise published at:
  150. @uref{http://openocd.sourceforge.net/doc/pdf/openocd.pdf}
  151. @section OpenOCD User's Forum
  152. There is an OpenOCD forum (phpBB) hosted by SparkFun,
  153. which might be helpful to you. Note that if you want
  154. anything to come to the attention of developers, you
  155. should post it to the OpenOCD Developer Mailing List
  156. instead of this forum.
  157. @uref{http://forum.sparkfun.com/viewforum.php?f=18}
  158. @section OpenOCD User's Mailing List
  159. The OpenOCD User Mailing List provides the primary means of
  160. communication between users:
  161. @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
  162. @section OpenOCD IRC
  163. Support can also be found on irc:
  164. @uref{irc://irc.freenode.net/openocd}
  165. @node Developers
  166. @chapter OpenOCD Developer Resources
  167. @cindex developers
  168. If you are interested in improving the state of OpenOCD's debugging and
  169. testing support, new contributions will be welcome. Motivated developers
  170. can produce new target, flash or interface drivers, improve the
  171. documentation, as well as more conventional bug fixes and enhancements.
  172. The resources in this chapter are available for developers wishing to explore
  173. or expand the OpenOCD source code.
  174. @section OpenOCD GIT Repository
  175. During the 0.3.x release cycle, OpenOCD switched from Subversion to
  176. a GIT repository hosted at SourceForge. The repository URL is:
  177. @uref{git://git.code.sf.net/p/openocd/code}
  178. or via http
  179. @uref{http://git.code.sf.net/p/openocd/code}
  180. You may prefer to use a mirror and the HTTP protocol:
  181. @uref{http://repo.or.cz/r/openocd.git}
  182. With standard GIT tools, use @command{git clone} to initialize
  183. a local repository, and @command{git pull} to update it.
  184. There are also gitweb pages letting you browse the repository
  185. with a web browser, or download arbitrary snapshots without
  186. needing a GIT client:
  187. @uref{http://repo.or.cz/w/openocd.git}
  188. The @file{README} file contains the instructions for building the project
  189. from the repository or a snapshot.
  190. Developers that want to contribute patches to the OpenOCD system are
  191. @b{strongly} encouraged to work against mainline.
  192. Patches created against older versions may require additional
  193. work from their submitter in order to be updated for newer releases.
  194. @section Doxygen Developer Manual
  195. During the 0.2.x release cycle, the OpenOCD project began
  196. providing a Doxygen reference manual. This document contains more
  197. technical information about the software internals, development
  198. processes, and similar documentation:
  199. @uref{http://openocd.sourceforge.net/doc/doxygen/html/index.html}
  200. This document is a work-in-progress, but contributions would be welcome
  201. to fill in the gaps. All of the source files are provided in-tree,
  202. listed in the Doxyfile configuration in the top of the source tree.
  203. @section OpenOCD Developer Mailing List
  204. The OpenOCD Developer Mailing List provides the primary means of
  205. communication between developers:
  206. @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
  207. Discuss and submit patches to this list.
  208. The @file{HACKING} file contains basic information about how
  209. to prepare patches.
  210. @section OpenOCD Bug Database
  211. During the 0.4.x release cycle the OpenOCD project team began
  212. using Trac for its bug database:
  213. @uref{https://sourceforge.net/apps/trac/openocd}
  214. @node Debug Adapter Hardware
  215. @chapter Debug Adapter Hardware
  216. @cindex dongles
  217. @cindex FTDI
  218. @cindex wiggler
  219. @cindex zy1000
  220. @cindex printer port
  221. @cindex USB Adapter
  222. @cindex RTCK
  223. Defined: @b{dongle}: A small device that plugins into a computer and serves as
  224. an adapter .... [snip]
  225. In the OpenOCD case, this generally refers to @b{a small adapter} that
  226. attaches to your computer via USB or the Parallel Printer Port. One
  227. exception is the Zylin ZY1000, packaged as a small box you attach via
  228. an ethernet cable. The Zylin ZY1000 has the advantage that it does not
  229. require any drivers to be installed on the developer PC. It also has
  230. a built in web interface. It supports RTCK/RCLK or adaptive clocking
  231. and has a built in relay to power cycle targets remotely.
  232. @section Choosing a Dongle
  233. There are several things you should keep in mind when choosing a dongle.
  234. @enumerate
  235. @item @b{Transport} Does it support the kind of communication that you need?
  236. OpenOCD focusses mostly on JTAG. Your version may also support
  237. other ways to communicate with target devices.
  238. @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
  239. Does your dongle support it? You might need a level converter.
  240. @item @b{Pinout} What pinout does your target board use?
  241. Does your dongle support it? You may be able to use jumper
  242. wires, or an "octopus" connector, to convert pinouts.
  243. @item @b{Connection} Does your computer have the USB, printer, or
  244. Ethernet port needed?
  245. @item @b{RTCK} Do you expect to use it with ARM chips and boards with
  246. RTCK support? Also known as ``adaptive clocking''
  247. @end enumerate
  248. @section Stand alone Systems
  249. @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/33-zylin-zy1000-jtag-probe}
  250. Technically, not a dongle, but a standalone box. The ZY1000 has the advantage that it does
  251. not require any drivers installed on the developer PC. It also has
  252. a built in web interface. It supports RTCK/RCLK or adaptive clocking
  253. and has a built in relay to power cycle targets remotely.
  254. @section USB FT2232 Based
  255. There are many USB JTAG dongles on the market, many of them are based
  256. on a chip from ``Future Technology Devices International'' (FTDI)
  257. known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
  258. See: @url{http://www.ftdichip.com} for more information.
  259. In summer 2009, USB high speed (480 Mbps) versions of these FTDI
  260. chips are starting to become available in JTAG adapters. (Adapters
  261. using those high speed FT2232H chips may support adaptive clocking.)
  262. The FT2232 chips are flexible enough to support some other
  263. transport options, such as SWD or the SPI variants used to
  264. program some chips. They have two communications channels,
  265. and one can be used for a UART adapter at the same time the
  266. other one is used to provide a debug adapter.
  267. Also, some development boards integrate an FT2232 chip to serve as
  268. a built-in low cost debug adapter and usb-to-serial solution.
  269. @itemize @bullet
  270. @item @b{usbjtag}
  271. @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
  272. @item @b{jtagkey}
  273. @* See: @url{http://www.amontec.com/jtagkey.shtml}
  274. @item @b{jtagkey2}
  275. @* See: @url{http://www.amontec.com/jtagkey2.shtml}
  276. @item @b{oocdlink}
  277. @* See: @url{http://www.oocdlink.com} By Joern Kaipf
  278. @item @b{signalyzer}
  279. @* See: @url{http://www.signalyzer.com}
  280. @item @b{Stellaris Eval Boards}
  281. @* See: @url{http://www.ti.com} - The Stellaris eval boards
  282. bundle FT2232-based JTAG and SWD support, which can be used to debug
  283. the Stellaris chips. Using separate JTAG adapters is optional.
  284. These boards can also be used in a "pass through" mode as JTAG adapters
  285. to other target boards, disabling the Stellaris chip.
  286. @item @b{TI/Luminary ICDI}
  287. @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
  288. Interface (ICDI) Boards are included in Stellaris LM3S9B9x
  289. Evaluation Kits. Like the non-detachable FT2232 support on the other
  290. Stellaris eval boards, they can be used to debug other target boards.
  291. @item @b{olimex-jtag}
  292. @* See: @url{http://www.olimex.com}
  293. @item @b{Flyswatter/Flyswatter2}
  294. @* See: @url{http://www.tincantools.com}
  295. @item @b{turtelizer2}
  296. @* See:
  297. @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
  298. @url{http://www.ethernut.de}
  299. @item @b{comstick}
  300. @* Link: @url{http://www.hitex.com/index.php?id=383}
  301. @item @b{stm32stick}
  302. @* Link @url{http://www.hitex.com/stm32-stick}
  303. @item @b{axm0432_jtag}
  304. @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
  305. to be available anymore as of April 2012.
  306. @item @b{cortino}
  307. @* Link @url{http://www.hitex.com/index.php?id=cortino}
  308. @item @b{dlp-usb1232h}
  309. @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
  310. @item @b{digilent-hs1}
  311. @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
  312. @item @b{opendous}
  313. @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
  314. (OpenHardware).
  315. @end itemize
  316. @section USB-JTAG / Altera USB-Blaster compatibles
  317. These devices also show up as FTDI devices, but are not
  318. protocol-compatible with the FT2232 devices. They are, however,
  319. protocol-compatible among themselves. USB-JTAG devices typically consist
  320. of a FT245 followed by a CPLD that understands a particular protocol,
  321. or emulate this protocol using some other hardware.
  322. They may appear under different USB VID/PID depending on the particular
  323. product. The driver can be configured to search for any VID/PID pair
  324. (see the section on driver commands).
  325. @itemize
  326. @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
  327. @* Link: @url{http://ixo-jtag.sourceforge.net/}
  328. @item @b{Altera USB-Blaster}
  329. @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
  330. @end itemize
  331. @section USB JLINK based
  332. There are several OEM versions of the Segger @b{JLINK} adapter. It is
  333. an example of a micro controller based JTAG adapter, it uses an
  334. AT91SAM764 internally.
  335. @itemize @bullet
  336. @item @b{ATMEL SAMICE} Only works with ATMEL chips!
  337. @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
  338. @item @b{SEGGER JLINK}
  339. @* Link: @url{http://www.segger.com/jlink.html}
  340. @item @b{IAR J-Link}
  341. @* Link: @url{http://www.iar.com/en/products/hardware-debug-probes/iar-j-link/}
  342. @end itemize
  343. @section USB RLINK based
  344. Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
  345. permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
  346. SWD and not JTAG, thus not supported.
  347. @itemize @bullet
  348. @item @b{Raisonance RLink}
  349. @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
  350. @item @b{STM32 Primer}
  351. @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
  352. @item @b{STM32 Primer2}
  353. @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
  354. @end itemize
  355. @section USB ST-LINK based
  356. ST Micro has an adapter called @b{ST-LINK}.
  357. They only work with ST Micro chips, notably STM32 and STM8.
  358. @itemize @bullet
  359. @item @b{ST-LINK}
  360. @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
  361. @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
  362. @item @b{ST-LINK/V2}
  363. @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
  364. @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
  365. @end itemize
  366. For info the original ST-LINK enumerates using the mass storage usb class, however
  367. it's implementation is completely broken. The result is this causes issues under linux.
  368. The simplest solution is to get linux to ignore the ST-LINK using one of the following methods:
  369. @itemize @bullet
  370. @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
  371. @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
  372. @end itemize
  373. @section USB TI/Stellaris ICDI based
  374. Texas Instruments has an adapter called @b{ICDI}.
  375. It is not to be confused with the FTDI based adapters that were originally fitted to their
  376. evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
  377. @section USB Other
  378. @itemize @bullet
  379. @item @b{USBprog}
  380. @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
  381. @item @b{USB - Presto}
  382. @* Link: @url{http://tools.asix.net/prg_presto.htm}
  383. @item @b{Versaloon-Link}
  384. @* Link: @url{http://www.versaloon.com}
  385. @item @b{ARM-JTAG-EW}
  386. @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
  387. @item @b{Buspirate}
  388. @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
  389. @item @b{opendous}
  390. @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
  391. @item @b{estick}
  392. @* Link: @url{http://code.google.com/p/estick-jtag/}
  393. @item @b{Keil ULINK v1}
  394. @* Link: @url{http://www.keil.com/ulink1/}
  395. @end itemize
  396. @section IBM PC Parallel Printer Port Based
  397. The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
  398. and the Macraigor Wiggler. There are many clones and variations of
  399. these on the market.
  400. Note that parallel ports are becoming much less common, so if you
  401. have the choice you should probably avoid these adapters in favor
  402. of USB-based ones.
  403. @itemize @bullet
  404. @item @b{Wiggler} - There are many clones of this.
  405. @* Link: @url{http://www.macraigor.com/wiggler.htm}
  406. @item @b{DLC5} - From XILINX - There are many clones of this
  407. @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
  408. produced, PDF schematics are easily found and it is easy to make.
  409. @item @b{Amontec - JTAG Accelerator}
  410. @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
  411. @item @b{GW16402}
  412. @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
  413. @item @b{Wiggler2}
  414. @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
  415. @item @b{Wiggler_ntrst_inverted}
  416. @* Yet another variation - See the source code, src/jtag/parport.c
  417. @item @b{old_amt_wiggler}
  418. @* Unknown - probably not on the market today
  419. @item @b{arm-jtag}
  420. @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
  421. @item @b{chameleon}
  422. @* Link: @url{http://www.amontec.com/chameleon.shtml}
  423. @item @b{Triton}
  424. @* Unknown.
  425. @item @b{Lattice}
  426. @* ispDownload from Lattice Semiconductor
  427. @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
  428. @item @b{flashlink}
  429. @* From ST Microsystems;
  430. @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
  431. @end itemize
  432. @section Other...
  433. @itemize @bullet
  434. @item @b{ep93xx}
  435. @* An EP93xx based Linux machine using the GPIO pins directly.
  436. @item @b{at91rm9200}
  437. @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
  438. @end itemize
  439. @node About Jim-Tcl
  440. @chapter About Jim-Tcl
  441. @cindex Jim-Tcl
  442. @cindex tcl
  443. OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
  444. This programming language provides a simple and extensible
  445. command interpreter.
  446. All commands presented in this Guide are extensions to Jim-Tcl.
  447. You can use them as simple commands, without needing to learn
  448. much of anything about Tcl.
  449. Alternatively, can write Tcl programs with them.
  450. You can learn more about Jim at its website, @url{http://jim.berlios.de}.
  451. There is an active and responsive community, get on the mailing list
  452. if you have any questions. Jim-Tcl maintainers also lurk on the
  453. OpenOCD mailing list.
  454. @itemize @bullet
  455. @item @b{Jim vs. Tcl}
  456. @* Jim-Tcl is a stripped down version of the well known Tcl language,
  457. which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
  458. fewer features. Jim-Tcl is several dozens of .C files and .H files and
  459. implements the basic Tcl command set. In contrast: Tcl 8.6 is a
  460. 4.2 MB .zip file containing 1540 files.
  461. @item @b{Missing Features}
  462. @* Our practice has been: Add/clone the real Tcl feature if/when
  463. needed. We welcome Jim-Tcl improvements, not bloat. Also there
  464. are a large number of optional Jim-Tcl features that are not
  465. enabled in OpenOCD.
  466. @item @b{Scripts}
  467. @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
  468. command interpreter today is a mixture of (newer)
  469. Jim-Tcl commands, and (older) the orginal command interpreter.
  470. @item @b{Commands}
  471. @* At the OpenOCD telnet command line (or via the GDB monitor command) one
  472. can type a Tcl for() loop, set variables, etc.
  473. Some of the commands documented in this guide are implemented
  474. as Tcl scripts, from a @file{startup.tcl} file internal to the server.
  475. @item @b{Historical Note}
  476. @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
  477. before OpenOCD 0.5 release OpenOCD switched to using Jim Tcl
  478. as a git submodule, which greatly simplified upgrading Jim Tcl
  479. to benefit from new features and bugfixes in Jim Tcl.
  480. @item @b{Need a crash course in Tcl?}
  481. @*@xref{Tcl Crash Course}.
  482. @end itemize
  483. @node Running
  484. @chapter Running
  485. @cindex command line options
  486. @cindex logfile
  487. @cindex directory search
  488. Properly installing OpenOCD sets up your operating system to grant it access
  489. to the debug adapters. On Linux, this usually involves installing a file
  490. in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
  491. complex and confusing driver configuration for every peripheral. Such issues
  492. are unique to each operating system, and are not detailed in this User's Guide.
  493. Then later you will invoke the OpenOCD server, with various options to
  494. tell it how each debug session should work.
  495. The @option{--help} option shows:
  496. @verbatim
  497. bash$ openocd --help
  498. --help | -h display this help
  499. --version | -v display OpenOCD version
  500. --file | -f use configuration file <name>
  501. --search | -s dir to search for config files and scripts
  502. --debug | -d set debug level <0-3>
  503. --log_output | -l redirect log output to file <name>
  504. --command | -c run <command>
  505. @end verbatim
  506. If you don't give any @option{-f} or @option{-c} options,
  507. OpenOCD tries to read the configuration file @file{openocd.cfg}.
  508. To specify one or more different
  509. configuration files, use @option{-f} options. For example:
  510. @example
  511. openocd -f config1.cfg -f config2.cfg -f config3.cfg
  512. @end example
  513. Configuration files and scripts are searched for in
  514. @enumerate
  515. @item the current directory,
  516. @item any search dir specified on the command line using the @option{-s} option,
  517. @item any search dir specified using the @command{add_script_search_dir} command,
  518. @item @file{$HOME/.openocd} (not on Windows),
  519. @item the site wide script library @file{$pkgdatadir/site} and
  520. @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
  521. @end enumerate
  522. The first found file with a matching file name will be used.
  523. @quotation Note
  524. Don't try to use configuration script names or paths which
  525. include the "#" character. That character begins Tcl comments.
  526. @end quotation
  527. @section Simple setup, no customization
  528. In the best case, you can use two scripts from one of the script
  529. libraries, hook up your JTAG adapter, and start the server ... and
  530. your JTAG setup will just work "out of the box". Always try to
  531. start by reusing those scripts, but assume you'll need more
  532. customization even if this works. @xref{OpenOCD Project Setup}.
  533. If you find a script for your JTAG adapter, and for your board or
  534. target, you may be able to hook up your JTAG adapter then start
  535. the server like:
  536. @example
  537. openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
  538. @end example
  539. You might also need to configure which reset signals are present,
  540. using @option{-c 'reset_config trst_and_srst'} or something similar.
  541. If all goes well you'll see output something like
  542. @example
  543. Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
  544. For bug reports, read
  545. http://openocd.sourceforge.net/doc/doxygen/bugs.html
  546. Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
  547. (mfg: 0x23b, part: 0xba00, ver: 0x3)
  548. @end example
  549. Seeing that "tap/device found" message, and no warnings, means
  550. the JTAG communication is working. That's a key milestone, but
  551. you'll probably need more project-specific setup.
  552. @section What OpenOCD does as it starts
  553. OpenOCD starts by processing the configuration commands provided
  554. on the command line or, if there were no @option{-c command} or
  555. @option{-f file.cfg} options given, in @file{openocd.cfg}.
  556. @xref{configurationstage,,Configuration Stage}.
  557. At the end of the configuration stage it verifies the JTAG scan
  558. chain defined using those commands; your configuration should
  559. ensure that this always succeeds.
  560. Normally, OpenOCD then starts running as a daemon.
  561. Alternatively, commands may be used to terminate the configuration
  562. stage early, perform work (such as updating some flash memory),
  563. and then shut down without acting as a daemon.
  564. Once OpenOCD starts running as a daemon, it waits for connections from
  565. clients (Telnet, GDB, Other) and processes the commands issued through
  566. those channels.
  567. If you are having problems, you can enable internal debug messages via
  568. the @option{-d} option.
  569. Also it is possible to interleave Jim-Tcl commands w/config scripts using the
  570. @option{-c} command line switch.
  571. To enable debug output (when reporting problems or working on OpenOCD
  572. itself), use the @option{-d} command line switch. This sets the
  573. @option{debug_level} to "3", outputting the most information,
  574. including debug messages. The default setting is "2", outputting only
  575. informational messages, warnings and errors. You can also change this
  576. setting from within a telnet or gdb session using @command{debug_level<n>}
  577. (@pxref{debuglevel,,debug_level}).
  578. You can redirect all output from the daemon to a file using the
  579. @option{-l <logfile>} switch.
  580. Note! OpenOCD will launch the GDB & telnet server even if it can not
  581. establish a connection with the target. In general, it is possible for
  582. the JTAG controller to be unresponsive until the target is set up
  583. correctly via e.g. GDB monitor commands in a GDB init script.
  584. @node OpenOCD Project Setup
  585. @chapter OpenOCD Project Setup
  586. To use OpenOCD with your development projects, you need to do more than
  587. just connecting the JTAG adapter hardware (dongle) to your development board
  588. and then starting the OpenOCD server.
  589. You also need to configure that server so that it knows
  590. about that adapter and board, and helps your work.
  591. You may also want to connect OpenOCD to GDB, possibly
  592. using Eclipse or some other GUI.
  593. @section Hooking up the JTAG Adapter
  594. Today's most common case is a dongle with a JTAG cable on one side
  595. (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
  596. and a USB cable on the other.
  597. Instead of USB, some cables use Ethernet;
  598. older ones may use a PC parallel port, or even a serial port.
  599. @enumerate
  600. @item @emph{Start with power to your target board turned off},
  601. and nothing connected to your JTAG adapter.
  602. If you're particularly paranoid, unplug power to the board.
  603. It's important to have the ground signal properly set up,
  604. unless you are using a JTAG adapter which provides
  605. galvanic isolation between the target board and the
  606. debugging host.
  607. @item @emph{Be sure it's the right kind of JTAG connector.}
  608. If your dongle has a 20-pin ARM connector, you need some kind
  609. of adapter (or octopus, see below) to hook it up to
  610. boards using 14-pin or 10-pin connectors ... or to 20-pin
  611. connectors which don't use ARM's pinout.
  612. In the same vein, make sure the voltage levels are compatible.
  613. Not all JTAG adapters have the level shifters needed to work
  614. with 1.2 Volt boards.
  615. @item @emph{Be certain the cable is properly oriented} or you might
  616. damage your board. In most cases there are only two possible
  617. ways to connect the cable.
  618. Connect the JTAG cable from your adapter to the board.
  619. Be sure it's firmly connected.
  620. In the best case, the connector is keyed to physically
  621. prevent you from inserting it wrong.
  622. This is most often done using a slot on the board's male connector
  623. housing, which must match a key on the JTAG cable's female connector.
  624. If there's no housing, then you must look carefully and
  625. make sure pin 1 on the cable hooks up to pin 1 on the board.
  626. Ribbon cables are frequently all grey except for a wire on one
  627. edge, which is red. The red wire is pin 1.
  628. Sometimes dongles provide cables where one end is an ``octopus'' of
  629. color coded single-wire connectors, instead of a connector block.
  630. These are great when converting from one JTAG pinout to another,
  631. but are tedious to set up.
  632. Use these with connector pinout diagrams to help you match up the
  633. adapter signals to the right board pins.
  634. @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
  635. A USB, parallel, or serial port connector will go to the host which
  636. you are using to run OpenOCD.
  637. For Ethernet, consult the documentation and your network administrator.
  638. For USB based JTAG adapters you have an easy sanity check at this point:
  639. does the host operating system see the JTAG adapter? If that host is an
  640. MS-Windows host, you'll need to install a driver before OpenOCD works.
  641. @item @emph{Connect the adapter's power supply, if needed.}
  642. This step is primarily for non-USB adapters,
  643. but sometimes USB adapters need extra power.
  644. @item @emph{Power up the target board.}
  645. Unless you just let the magic smoke escape,
  646. you're now ready to set up the OpenOCD server
  647. so you can use JTAG to work with that board.
  648. @end enumerate
  649. Talk with the OpenOCD server using
  650. telnet (@code{telnet localhost 4444} on many systems) or GDB.
  651. @xref{GDB and OpenOCD}.
  652. @section Project Directory
  653. There are many ways you can configure OpenOCD and start it up.
  654. A simple way to organize them all involves keeping a
  655. single directory for your work with a given board.
  656. When you start OpenOCD from that directory,
  657. it searches there first for configuration files, scripts,
  658. files accessed through semihosting,
  659. and for code you upload to the target board.
  660. It is also the natural place to write files,
  661. such as log files and data you download from the board.
  662. @section Configuration Basics
  663. There are two basic ways of configuring OpenOCD, and
  664. a variety of ways you can mix them.
  665. Think of the difference as just being how you start the server:
  666. @itemize
  667. @item Many @option{-f file} or @option{-c command} options on the command line
  668. @item No options, but a @dfn{user config file}
  669. in the current directory named @file{openocd.cfg}
  670. @end itemize
  671. Here is an example @file{openocd.cfg} file for a setup
  672. using a Signalyzer FT2232-based JTAG adapter to talk to
  673. a board with an Atmel AT91SAM7X256 microcontroller:
  674. @example
  675. source [find interface/signalyzer.cfg]
  676. # GDB can also flash my flash!
  677. gdb_memory_map enable
  678. gdb_flash_program enable
  679. source [find target/sam7x256.cfg]
  680. @end example
  681. Here is the command line equivalent of that configuration:
  682. @example
  683. openocd -f interface/signalyzer.cfg \
  684. -c "gdb_memory_map enable" \
  685. -c "gdb_flash_program enable" \
  686. -f target/sam7x256.cfg
  687. @end example
  688. You could wrap such long command lines in shell scripts,
  689. each supporting a different development task.
  690. One might re-flash the board with a specific firmware version.
  691. Another might set up a particular debugging or run-time environment.
  692. @quotation Important
  693. At this writing (October 2009) the command line method has
  694. problems with how it treats variables.
  695. For example, after @option{-c "set VAR value"}, or doing the
  696. same in a script, the variable @var{VAR} will have no value
  697. that can be tested in a later script.
  698. @end quotation
  699. Here we will focus on the simpler solution: one user config
  700. file, including basic configuration plus any TCL procedures
  701. to simplify your work.
  702. @section User Config Files
  703. @cindex config file, user
  704. @cindex user config file
  705. @cindex config file, overview
  706. A user configuration file ties together all the parts of a project
  707. in one place.
  708. One of the following will match your situation best:
  709. @itemize
  710. @item Ideally almost everything comes from configuration files
  711. provided by someone else.
  712. For example, OpenOCD distributes a @file{scripts} directory
  713. (probably in @file{/usr/share/openocd/scripts} on Linux).
  714. Board and tool vendors can provide these too, as can individual
  715. user sites; the @option{-s} command line option lets you say
  716. where to find these files. (@xref{Running}.)
  717. The AT91SAM7X256 example above works this way.
  718. Three main types of non-user configuration file each have their
  719. own subdirectory in the @file{scripts} directory:
  720. @enumerate
  721. @item @b{interface} -- one for each different debug adapter;
  722. @item @b{board} -- one for each different board
  723. @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
  724. @end enumerate
  725. Best case: include just two files, and they handle everything else.
  726. The first is an interface config file.
  727. The second is board-specific, and it sets up the JTAG TAPs and
  728. their GDB targets (by deferring to some @file{target.cfg} file),
  729. declares all flash memory, and leaves you nothing to do except
  730. meet your deadline:
  731. @example
  732. source [find interface/olimex-jtag-tiny.cfg]
  733. source [find board/csb337.cfg]
  734. @end example
  735. Boards with a single microcontroller often won't need more
  736. than the target config file, as in the AT91SAM7X256 example.
  737. That's because there is no external memory (flash, DDR RAM), and
  738. the board differences are encapsulated by application code.
  739. @item Maybe you don't know yet what your board looks like to JTAG.
  740. Once you know the @file{interface.cfg} file to use, you may
  741. need help from OpenOCD to discover what's on the board.
  742. Once you find the JTAG TAPs, you can just search for appropriate
  743. target and board
  744. configuration files ... or write your own, from the bottom up.
  745. @xref{autoprobing,,Autoprobing}.
  746. @item You can often reuse some standard config files but
  747. need to write a few new ones, probably a @file{board.cfg} file.
  748. You will be using commands described later in this User's Guide,
  749. and working with the guidelines in the next chapter.
  750. For example, there may be configuration files for your JTAG adapter
  751. and target chip, but you need a new board-specific config file
  752. giving access to your particular flash chips.
  753. Or you might need to write another target chip configuration file
  754. for a new chip built around the Cortex M3 core.
  755. @quotation Note
  756. When you write new configuration files, please submit
  757. them for inclusion in the next OpenOCD release.
  758. For example, a @file{board/newboard.cfg} file will help the
  759. next users of that board, and a @file{target/newcpu.cfg}
  760. will help support users of any board using that chip.
  761. @end quotation
  762. @item
  763. You may may need to write some C code.
  764. It may be as simple as a supporting a new ft2232 or parport
  765. based adapter; a bit more involved, like a NAND or NOR flash
  766. controller driver; or a big piece of work like supporting
  767. a new chip architecture.
  768. @end itemize
  769. Reuse the existing config files when you can.
  770. Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
  771. You may find a board configuration that's a good example to follow.
  772. When you write config files, separate the reusable parts
  773. (things every user of that interface, chip, or board needs)
  774. from ones specific to your environment and debugging approach.
  775. @itemize
  776. @item
  777. For example, a @code{gdb-attach} event handler that invokes
  778. the @command{reset init} command will interfere with debugging
  779. early boot code, which performs some of the same actions
  780. that the @code{reset-init} event handler does.
  781. @item
  782. Likewise, the @command{arm9 vector_catch} command (or
  783. @cindex vector_catch
  784. its siblings @command{xscale vector_catch}
  785. and @command{cortex_m3 vector_catch}) can be a timesaver
  786. during some debug sessions, but don't make everyone use that either.
  787. Keep those kinds of debugging aids in your user config file,
  788. along with messaging and tracing setup.
  789. (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
  790. @item
  791. You might need to override some defaults.
  792. For example, you might need to move, shrink, or back up the target's
  793. work area if your application needs much SRAM.
  794. @item
  795. TCP/IP port configuration is another example of something which
  796. is environment-specific, and should only appear in
  797. a user config file. @xref{tcpipports,,TCP/IP Ports}.
  798. @end itemize
  799. @section Project-Specific Utilities
  800. A few project-specific utility
  801. routines may well speed up your work.
  802. Write them, and keep them in your project's user config file.
  803. For example, if you are making a boot loader work on a
  804. board, it's nice to be able to debug the ``after it's
  805. loaded to RAM'' parts separately from the finicky early
  806. code which sets up the DDR RAM controller and clocks.
  807. A script like this one, or a more GDB-aware sibling,
  808. may help:
  809. @example
  810. proc ramboot @{ @} @{
  811. # Reset, running the target's "reset-init" scripts
  812. # to initialize clocks and the DDR RAM controller.
  813. # Leave the CPU halted.
  814. reset init
  815. # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
  816. load_image u-boot.bin 0x20000000
  817. # Start running.
  818. resume 0x20000000
  819. @}
  820. @end example
  821. Then once that code is working you will need to make it
  822. boot from NOR flash; a different utility would help.
  823. Alternatively, some developers write to flash using GDB.
  824. (You might use a similar script if you're working with a flash
  825. based microcontroller application instead of a boot loader.)
  826. @example
  827. proc newboot @{ @} @{
  828. # Reset, leaving the CPU halted. The "reset-init" event
  829. # proc gives faster access to the CPU and to NOR flash;
  830. # "reset halt" would be slower.
  831. reset init
  832. # Write standard version of U-Boot into the first two
  833. # sectors of NOR flash ... the standard version should
  834. # do the same lowlevel init as "reset-init".
  835. flash protect 0 0 1 off
  836. flash erase_sector 0 0 1
  837. flash write_bank 0 u-boot.bin 0x0
  838. flash protect 0 0 1 on
  839. # Reboot from scratch using that new boot loader.
  840. reset run
  841. @}
  842. @end example
  843. You may need more complicated utility procedures when booting
  844. from NAND.
  845. That often involves an extra bootloader stage,
  846. running from on-chip SRAM to perform DDR RAM setup so it can load
  847. the main bootloader code (which won't fit into that SRAM).
  848. Other helper scripts might be used to write production system images,
  849. involving considerably more than just a three stage bootloader.
  850. @section Target Software Changes
  851. Sometimes you may want to make some small changes to the software
  852. you're developing, to help make JTAG debugging work better.
  853. For example, in C or assembly language code you might
  854. use @code{#ifdef JTAG_DEBUG} (or its converse) around code
  855. handling issues like:
  856. @itemize @bullet
  857. @item @b{Watchdog Timers}...
  858. Watchog timers are typically used to automatically reset systems if
  859. some application task doesn't periodically reset the timer. (The
  860. assumption is that the system has locked up if the task can't run.)
  861. When a JTAG debugger halts the system, that task won't be able to run
  862. and reset the timer ... potentially causing resets in the middle of
  863. your debug sessions.
  864. It's rarely a good idea to disable such watchdogs, since their usage
  865. needs to be debugged just like all other parts of your firmware.
  866. That might however be your only option.
  867. Look instead for chip-specific ways to stop the watchdog from counting
  868. while the system is in a debug halt state. It may be simplest to set
  869. that non-counting mode in your debugger startup scripts. You may however
  870. need a different approach when, for example, a motor could be physically
  871. damaged by firmware remaining inactive in a debug halt state. That might
  872. involve a type of firmware mode where that "non-counting" mode is disabled
  873. at the beginning then re-enabled at the end; a watchdog reset might fire
  874. and complicate the debug session, but hardware (or people) would be
  875. protected.@footnote{Note that many systems support a "monitor mode" debug
  876. that is a somewhat cleaner way to address such issues. You can think of
  877. it as only halting part of the system, maybe just one task,
  878. instead of the whole thing.
  879. At this writing, January 2010, OpenOCD based debugging does not support
  880. monitor mode debug, only "halt mode" debug.}
  881. @item @b{ARM Semihosting}...
  882. @cindex ARM semihosting
  883. When linked with a special runtime library provided with many
  884. toolchains@footnote{See chapter 8 "Semihosting" in
  885. @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
  886. ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
  887. The CodeSourcery EABI toolchain also includes a semihosting library.},
  888. your target code can use I/O facilities on the debug host. That library
  889. provides a small set of system calls which are handled by OpenOCD.
  890. It can let the debugger provide your system console and a file system,
  891. helping with early debugging or providing a more capable environment
  892. for sometimes-complex tasks like installing system firmware onto
  893. NAND or SPI flash.
  894. @item @b{ARM Wait-For-Interrupt}...
  895. Many ARM chips synchronize the JTAG clock using the core clock.
  896. Low power states which stop that core clock thus prevent JTAG access.
  897. Idle loops in tasking environments often enter those low power states
  898. via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
  899. You may want to @emph{disable that instruction} in source code,
  900. or otherwise prevent using that state,
  901. to ensure you can get JTAG access at any time.@footnote{As a more
  902. polite alternative, some processors have special debug-oriented
  903. registers which can be used to change various features including
  904. how the low power states are clocked while debugging.
  905. The STM32 DBGMCU_CR register is an example; at the cost of extra
  906. power consumption, JTAG can be used during low power states.}
  907. For example, the OpenOCD @command{halt} command may not
  908. work for an idle processor otherwise.
  909. @item @b{Delay after reset}...
  910. Not all chips have good support for debugger access
  911. right after reset; many LPC2xxx chips have issues here.
  912. Similarly, applications that reconfigure pins used for
  913. JTAG access as they start will also block debugger access.
  914. To work with boards like this, @emph{enable a short delay loop}
  915. the first thing after reset, before "real" startup activities.
  916. For example, one second's delay is usually more than enough
  917. time for a JTAG debugger to attach, so that
  918. early code execution can be debugged
  919. or firmware can be replaced.
  920. @item @b{Debug Communications Channel (DCC)}...
  921. Some processors include mechanisms to send messages over JTAG.
  922. Many ARM cores support these, as do some cores from other vendors.
  923. (OpenOCD may be able to use this DCC internally, speeding up some
  924. operations like writing to memory.)
  925. Your application may want to deliver various debugging messages
  926. over JTAG, by @emph{linking with a small library of code}
  927. provided with OpenOCD and using the utilities there to send
  928. various kinds of message.
  929. @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
  930. @end itemize
  931. @section Target Hardware Setup
  932. Chip vendors often provide software development boards which
  933. are highly configurable, so that they can support all options
  934. that product boards may require. @emph{Make sure that any
  935. jumpers or switches match the system configuration you are
  936. working with.}
  937. Common issues include:
  938. @itemize @bullet
  939. @item @b{JTAG setup} ...
  940. Boards may support more than one JTAG configuration.
  941. Examples include jumpers controlling pullups versus pulldowns
  942. on the nTRST and/or nSRST signals, and choice of connectors
  943. (e.g. which of two headers on the base board,
  944. or one from a daughtercard).
  945. For some Texas Instruments boards, you may need to jumper the
  946. EMU0 and EMU1 signals (which OpenOCD won't currently control).
  947. @item @b{Boot Modes} ...
  948. Complex chips often support multiple boot modes, controlled
  949. by external jumpers. Make sure this is set up correctly.
  950. For example many i.MX boards from NXP need to be jumpered
  951. to "ATX mode" to start booting using the on-chip ROM, when
  952. using second stage bootloader code stored in a NAND flash chip.
  953. Such explicit configuration is common, and not limited to
  954. booting from NAND. You might also need to set jumpers to
  955. start booting using code loaded from an MMC/SD card; external
  956. SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
  957. flash; some external host; or various other sources.
  958. @item @b{Memory Addressing} ...
  959. Boards which support multiple boot modes may also have jumpers
  960. to configure memory addressing. One board, for example, jumpers
  961. external chipselect 0 (used for booting) to address either
  962. a large SRAM (which must be pre-loaded via JTAG), NOR flash,
  963. or NAND flash. When it's jumpered to address NAND flash, that
  964. board must also be told to start booting from on-chip ROM.
  965. Your @file{board.cfg} file may also need to be told this jumper
  966. configuration, so that it can know whether to declare NOR flash
  967. using @command{flash bank} or instead declare NAND flash with
  968. @command{nand device}; and likewise which probe to perform in
  969. its @code{reset-init} handler.
  970. A closely related issue is bus width. Jumpers might need to
  971. distinguish between 8 bit or 16 bit bus access for the flash
  972. used to start booting.
  973. @item @b{Peripheral Access} ...
  974. Development boards generally provide access to every peripheral
  975. on the chip, sometimes in multiple modes (such as by providing
  976. multiple audio codec chips).
  977. This interacts with software
  978. configuration of pin multiplexing, where for example a
  979. given pin may be routed either to the MMC/SD controller
  980. or the GPIO controller. It also often interacts with
  981. configuration jumpers. One jumper may be used to route
  982. signals to an MMC/SD card slot or an expansion bus (which
  983. might in turn affect booting); others might control which
  984. audio or video codecs are used.
  985. @end itemize
  986. Plus you should of course have @code{reset-init} event handlers
  987. which set up the hardware to match that jumper configuration.
  988. That includes in particular any oscillator or PLL used to clock
  989. the CPU, and any memory controllers needed to access external
  990. memory and peripherals. Without such handlers, you won't be
  991. able to access those resources without working target firmware
  992. which can do that setup ... this can be awkward when you're
  993. trying to debug that target firmware. Even if there's a ROM
  994. bootloader which handles a few issues, it rarely provides full
  995. access to all board-specific capabilities.
  996. @node Config File Guidelines
  997. @chapter Config File Guidelines
  998. This chapter is aimed at any user who needs to write a config file,
  999. including developers and integrators of OpenOCD and any user who
  1000. needs to get a new board working smoothly.
  1001. It provides guidelines for creating those files.
  1002. You should find the following directories under @t{$(INSTALLDIR)/scripts},
  1003. with files including the ones listed here.
  1004. Use them as-is where you can; or as models for new files.
  1005. @itemize @bullet
  1006. @item @file{interface} ...
  1007. These are for debug adapters.
  1008. Files that configure JTAG adapters go here.
  1009. @example
  1010. $ ls interface
  1011. altera-usb-blaster.cfg hilscher_nxhx50_etm.cfg openrd.cfg
  1012. arm-jtag-ew.cfg hilscher_nxhx50_re.cfg osbdm.cfg
  1013. arm-usb-ocd.cfg hitex_str9-comstick.cfg parport.cfg
  1014. at91rm9200.cfg icebear.cfg parport_dlc5.cfg
  1015. axm0432.cfg jlink.cfg redbee-econotag.cfg
  1016. busblaster.cfg jtagkey2.cfg redbee-usb.cfg
  1017. buspirate.cfg jtagkey2p.cfg rlink.cfg
  1018. calao-usb-a9260-c01.cfg jtagkey.cfg sheevaplug.cfg
  1019. calao-usb-a9260-c02.cfg jtagkey-tiny.cfg signalyzer.cfg
  1020. calao-usb-a9260.cfg kt-link.cfg signalyzer-h2.cfg
  1021. chameleon.cfg lisa-l.cfg signalyzer-h4.cfg
  1022. cortino.cfg luminary.cfg signalyzer-lite.cfg
  1023. digilent-hs1.cfg luminary-icdi.cfg stlink-v1.cfg
  1024. dlp-usb1232h.cfg luminary-lm3s811.cfg stlink-v2.cfg
  1025. dummy.cfg minimodule.cfg stm32-stick.cfg
  1026. estick.cfg neodb.cfg turtelizer2.cfg
  1027. flashlink.cfg ngxtech.cfg ulink.cfg
  1028. flossjtag.cfg olimex-arm-usb-ocd.cfg usb-jtag.cfg
  1029. flossjtag-noeeprom.cfg olimex-arm-usb-ocd-h.cfg usbprog.cfg
  1030. flyswatter2.cfg olimex-arm-usb-tiny-h.cfg vpaclink.cfg
  1031. flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
  1032. hilscher_nxhx10_etm.cfg oocdlink.cfg xds100v2.cfg
  1033. hilscher_nxhx500_etm.cfg opendous.cfg
  1034. hilscher_nxhx500_re.cfg openocd-usb.cfg
  1035. $
  1036. @end example
  1037. @item @file{board} ...
  1038. think Circuit Board, PWA, PCB, they go by many names. Board files
  1039. contain initialization items that are specific to a board.
  1040. They reuse target configuration files, since the same
  1041. microprocessor chips are used on many boards,
  1042. but support for external parts varies widely. For
  1043. example, the SDRAM initialization sequence for the board, or the type
  1044. of external flash and what address it uses. Any initialization
  1045. sequence to enable that external flash or SDRAM should be found in the
  1046. board file. Boards may also contain multiple targets: two CPUs; or
  1047. a CPU and an FPGA.
  1048. @example
  1049. $ ls board
  1050. actux3.cfg logicpd_imx27.cfg
  1051. am3517evm.cfg lubbock.cfg
  1052. arm_evaluator7t.cfg mcb1700.cfg
  1053. at91cap7a-stk-sdram.cfg microchip_explorer16.cfg
  1054. at91eb40a.cfg mini2440.cfg
  1055. at91rm9200-dk.cfg mini6410.cfg
  1056. at91rm9200-ek.cfg olimex_LPC2378STK.cfg
  1057. at91sam9261-ek.cfg olimex_lpc_h2148.cfg
  1058. at91sam9263-ek.cfg olimex_sam7_ex256.cfg
  1059. at91sam9g20-ek.cfg olimex_sam9_l9260.cfg
  1060. atmel_at91sam7s-ek.cfg olimex_stm32_h103.cfg
  1061. atmel_at91sam9260-ek.cfg olimex_stm32_h107.cfg
  1062. atmel_at91sam9rl-ek.cfg olimex_stm32_p107.cfg
  1063. atmel_sam3n_ek.cfg omap2420_h4.cfg
  1064. atmel_sam3s_ek.cfg open-bldc.cfg
  1065. atmel_sam3u_ek.cfg openrd.cfg
  1066. atmel_sam3x_ek.cfg osk5912.cfg
  1067. atmel_sam4s_ek.cfg phytec_lpc3250.cfg
  1068. balloon3-cpu.cfg pic-p32mx.cfg
  1069. colibri.cfg propox_mmnet1001.cfg
  1070. crossbow_tech_imote2.cfg pxa255_sst.cfg
  1071. csb337.cfg redbee.cfg
  1072. csb732.cfg rsc-w910.cfg
  1073. da850evm.cfg sheevaplug.cfg
  1074. digi_connectcore_wi-9c.cfg smdk6410.cfg
  1075. diolan_lpc4350-db1.cfg spear300evb.cfg
  1076. dm355evm.cfg spear300evb_mod.cfg
  1077. dm365evm.cfg spear310evb20.cfg
  1078. dm6446evm.cfg spear310evb20_mod.cfg
  1079. efikamx.cfg spear320cpu.cfg
  1080. eir.cfg spear320cpu_mod.cfg
  1081. ek-lm3s1968.cfg steval_pcc010.cfg
  1082. ek-lm3s3748.cfg stm320518_eval_stlink.cfg
  1083. ek-lm3s6965.cfg stm32100b_eval.cfg
  1084. ek-lm3s811.cfg stm3210b_eval.cfg
  1085. ek-lm3s811-revb.cfg stm3210c_eval.cfg
  1086. ek-lm3s9b9x.cfg stm3210e_eval.cfg
  1087. ek-lm4f232.cfg stm3220g_eval.cfg
  1088. embedded-artists_lpc2478-32.cfg stm3220g_eval_stlink.cfg
  1089. ethernut3.cfg stm3241g_eval.cfg
  1090. glyn_tonga2.cfg stm3241g_eval_stlink.cfg
  1091. hammer.cfg stm32f0discovery.cfg
  1092. hilscher_nxdb500sys.cfg stm32f4discovery.cfg
  1093. hilscher_nxeb500hmi.cfg stm32ldiscovery.cfg
  1094. hilscher_nxhx10.cfg stm32vldiscovery.cfg
  1095. hilscher_nxhx500.cfg str910-eval.cfg
  1096. hilscher_nxhx50.cfg telo.cfg
  1097. hilscher_nxsb100.cfg ti_beagleboard.cfg
  1098. hitex_lpc2929.cfg ti_beagleboard_xm.cfg
  1099. hitex_stm32-performancestick.cfg ti_beaglebone.cfg
  1100. hitex_str9-comstick.cfg ti_blaze.cfg
  1101. iar_lpc1768.cfg ti_pandaboard.cfg
  1102. iar_str912_sk.cfg ti_pandaboard_es.cfg
  1103. icnova_imx53_sodimm.cfg topas910.cfg
  1104. icnova_sam9g45_sodimm.cfg topasa900.cfg
  1105. imx27ads.cfg twr-k60n512.cfg
  1106. imx27lnst.cfg tx25_stk5.cfg
  1107. imx28evk.cfg tx27_stk5.cfg
  1108. imx31pdk.cfg unknown_at91sam9260.cfg
  1109. imx35pdk.cfg uptech_2410.cfg
  1110. imx53loco.cfg verdex.cfg
  1111. keil_mcb1700.cfg voipac.cfg
  1112. keil_mcb2140.cfg voltcraft_dso-3062c.cfg
  1113. kwikstik.cfg x300t.cfg
  1114. linksys_nslu2.cfg zy1000.cfg
  1115. lisa-l.cfg
  1116. $
  1117. @end example
  1118. @item @file{target} ...
  1119. think chip. The ``target'' directory represents the JTAG TAPs
  1120. on a chip
  1121. which OpenOCD should control, not a board. Two common types of targets
  1122. are ARM chips and FPGA or CPLD chips.
  1123. When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
  1124. the target config file defines all of them.
  1125. @example
  1126. $ ls target
  1127. $duc702x.cfg ixp42x.cfg
  1128. am335x.cfg k40.cfg
  1129. amdm37x.cfg k60.cfg
  1130. ar71xx.cfg lpc1768.cfg
  1131. at32ap7000.cfg lpc2103.cfg
  1132. at91r40008.cfg lpc2124.cfg
  1133. at91rm9200.cfg lpc2129.cfg
  1134. at91sam3ax_4x.cfg lpc2148.cfg
  1135. at91sam3ax_8x.cfg lpc2294.cfg
  1136. at91sam3ax_xx.cfg lpc2378.cfg
  1137. at91sam3nXX.cfg lpc2460.cfg
  1138. at91sam3sXX.cfg lpc2478.cfg
  1139. at91sam3u1c.cfg lpc2900.cfg
  1140. at91sam3u1e.cfg lpc2xxx.cfg
  1141. at91sam3u2c.cfg lpc3131.cfg
  1142. at91sam3u2e.cfg lpc3250.cfg
  1143. at91sam3u4c.cfg lpc4350.cfg
  1144. at91sam3u4e.cfg mc13224v.cfg
  1145. at91sam3uxx.cfg nuc910.cfg
  1146. at91sam3XXX.cfg omap2420.cfg
  1147. at91sam4sXX.cfg omap3530.cfg
  1148. at91sam4XXX.cfg omap4430.cfg
  1149. at91sam7se512.cfg omap4460.cfg
  1150. at91sam7sx.cfg omap5912.cfg
  1151. at91sam7x256.cfg omapl138.cfg
  1152. at91sam7x512.cfg pic32mx.cfg
  1153. at91sam9260.cfg pxa255.cfg
  1154. at91sam9260_ext_RAM_ext_flash.cfg pxa270.cfg
  1155. at91sam9261.cfg pxa3xx.cfg
  1156. at91sam9263.cfg readme.txt
  1157. at91sam9.cfg samsung_s3c2410.cfg
  1158. at91sam9g10.cfg samsung_s3c2440.cfg
  1159. at91sam9g20.cfg samsung_s3c2450.cfg
  1160. at91sam9g45.cfg samsung_s3c4510.cfg
  1161. at91sam9rl.cfg samsung_s3c6410.cfg
  1162. atmega128.cfg sharp_lh79532.cfg
  1163. avr32.cfg smp8634.cfg
  1164. c100.cfg spear3xx.cfg
  1165. c100config.tcl stellaris.cfg
  1166. c100helper.tcl stm32.cfg
  1167. c100regs.tcl stm32f0x_stlink.cfg
  1168. cs351x.cfg stm32f1x.cfg
  1169. davinci.cfg stm32f1x_stlink.cfg
  1170. dragonite.cfg stm32f2x.cfg
  1171. dsp56321.cfg stm32f2x_stlink.cfg
  1172. dsp568013.cfg stm32f2xxx.cfg
  1173. dsp568037.cfg stm32f4x.cfg
  1174. epc9301.cfg stm32f4x_stlink.cfg
  1175. faux.cfg stm32l.cfg
  1176. feroceon.cfg stm32lx_stlink.cfg
  1177. fm3.cfg stm32_stlink.cfg
  1178. hilscher_netx10.cfg stm32xl.cfg
  1179. hilscher_netx500.cfg str710.cfg
  1180. hilscher_netx50.cfg str730.cfg
  1181. icepick.cfg str750.cfg
  1182. imx21.cfg str912.cfg
  1183. imx25.cfg swj-dp.tcl
  1184. imx27.cfg test_reset_syntax_error.cfg
  1185. imx28.cfg test_syntax_error.cfg
  1186. imx31.cfg ti_dm355.cfg
  1187. imx35.cfg ti_dm365.cfg
  1188. imx51.cfg ti_dm6446.cfg
  1189. imx53.cfg tmpa900.cfg
  1190. imx.cfg tmpa910.cfg
  1191. is5114.cfg u8500.cfg
  1192. @end example
  1193. @item @emph{more} ... browse for other library files which may be useful.
  1194. For example, there are various generic and CPU-specific utilities.
  1195. @end itemize
  1196. The @file{openocd.cfg} user config
  1197. file may override features in any of the above files by
  1198. setting variables before sourcing the target file, or by adding
  1199. commands specific to their situation.
  1200. @section Interface Config Files
  1201. The user config file
  1202. should be able to source one of these files with a command like this:
  1203. @example
  1204. source [find interface/FOOBAR.cfg]
  1205. @end example
  1206. A preconfigured interface file should exist for every debug adapter
  1207. in use today with OpenOCD.
  1208. That said, perhaps some of these config files
  1209. have only been used by the developer who created it.
  1210. A separate chapter gives information about how to set these up.
  1211. @xref{Debug Adapter Configuration}.
  1212. Read the OpenOCD source code (and Developer's Guide)
  1213. if you have a new kind of hardware interface
  1214. and need to provide a driver for it.
  1215. @section Board Config Files
  1216. @cindex config file, board
  1217. @cindex board config file
  1218. The user config file
  1219. should be able to source one of these files with a command like this:
  1220. @example
  1221. source [find board/FOOBAR.cfg]
  1222. @end example
  1223. The point of a board config file is to package everything
  1224. about a given board that user config files need to know.
  1225. In summary the board files should contain (if present)
  1226. @enumerate
  1227. @item One or more @command{source [target/...cfg]} statements
  1228. @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
  1229. @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
  1230. @item Target @code{reset} handlers for SDRAM and I/O configuration
  1231. @item JTAG adapter reset configuration (@pxref{Reset Configuration})
  1232. @item All things that are not ``inside a chip''
  1233. @end enumerate
  1234. Generic things inside target chips belong in target config files,
  1235. not board config files. So for example a @code{reset-init} event
  1236. handler should know board-specific oscillator and PLL parameters,
  1237. which it passes to target-specific utility code.
  1238. The most complex task of a board config file is creating such a
  1239. @code{reset-init} event handler.
  1240. Define those handlers last, after you verify the rest of the board
  1241. configuration works.
  1242. @subsection Communication Between Config files
  1243. In addition to target-specific utility code, another way that
  1244. board and target config files communicate is by following a
  1245. convention on how to use certain variables.
  1246. The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
  1247. Thus the rule we follow in OpenOCD is this: Variables that begin with
  1248. a leading underscore are temporary in nature, and can be modified and
  1249. used at will within a target configuration file.
  1250. Complex board config files can do the things like this,
  1251. for a board with three chips:
  1252. @example
  1253. # Chip #1: PXA270 for network side, big endian
  1254. set CHIPNAME network
  1255. set ENDIAN big
  1256. source [find target/pxa270.cfg]
  1257. # on return: _TARGETNAME = network.cpu
  1258. # other commands can refer to the "network.cpu" target.
  1259. $_TARGETNAME configure .... events for this CPU..
  1260. # Chip #2: PXA270 for video side, little endian
  1261. set CHIPNAME video
  1262. set ENDIAN little
  1263. source [find target/pxa270.cfg]
  1264. # on return: _TARGETNAME = video.cpu
  1265. # other commands can refer to the "video.cpu" target.
  1266. $_TARGETNAME configure .... events for this CPU..
  1267. # Chip #3: Xilinx FPGA for glue logic
  1268. set CHIPNAME xilinx
  1269. unset ENDIAN
  1270. source [find target/spartan3.cfg]
  1271. @end example
  1272. That example is oversimplified because it doesn't show any flash memory,
  1273. or the @code{reset-init} event handlers to initialize external DRAM
  1274. or (assuming it needs it) load a configuration into the FPGA.
  1275. Such features are usually needed for low-level work with many boards,
  1276. where ``low level'' implies that the board initialization software may
  1277. not be working. (That's a common reason to need JTAG tools. Another
  1278. is to enable working with microcontroller-based systems, which often
  1279. have no debugging support except a JTAG connector.)
  1280. Target config files may also export utility functions to board and user
  1281. config files. Such functions should use name prefixes, to help avoid
  1282. naming collisions.
  1283. Board files could also accept input variables from user config files.
  1284. For example, there might be a @code{J4_JUMPER} setting used to identify
  1285. what kind of flash memory a development board is using, or how to set
  1286. up other clocks and peripherals.
  1287. @subsection Variable Naming Convention
  1288. @cindex variable names
  1289. Most boards have only one instance of a chip.
  1290. However, it should be easy to create a board with more than
  1291. one such chip (as shown above).
  1292. Accordingly, we encourage these conventions for naming
  1293. variables associated with different @file{target.cfg} files,
  1294. to promote consistency and
  1295. so that board files can override target defaults.
  1296. Inputs to target config files include:
  1297. @itemize @bullet
  1298. @item @code{CHIPNAME} ...
  1299. This gives a name to the overall chip, and is used as part of
  1300. tap identifier dotted names.
  1301. While the default is normally provided by the chip manufacturer,
  1302. board files may need to distinguish between instances of a chip.
  1303. @item @code{ENDIAN} ...
  1304. By default @option{little} - although chips may hard-wire @option{big}.
  1305. Chips that can't change endianness don't need to use this variable.
  1306. @item @code{CPUTAPID} ...
  1307. When OpenOCD examines the JTAG chain, it can be told verify the
  1308. chips against the JTAG IDCODE register.
  1309. The target file will hold one or more defaults, but sometimes the
  1310. chip in a board will use a different ID (perhaps a newer revision).
  1311. @end itemize
  1312. Outputs from target config files include:
  1313. @itemize @bullet
  1314. @item @code{_TARGETNAME} ...
  1315. By convention, this variable is created by the target configuration
  1316. script. The board configuration file may make use of this variable to
  1317. configure things like a ``reset init'' script, or other things
  1318. specific to that board and that target.
  1319. If the chip has 2 targets, the names are @code{_TARGETNAME0},
  1320. @code{_TARGETNAME1}, ... etc.
  1321. @end itemize
  1322. @subsection The reset-init Event Handler
  1323. @cindex event, reset-init
  1324. @cindex reset-init handler
  1325. Board config files run in the OpenOCD configuration stage;
  1326. they can't use TAPs or targets, since they haven't been
  1327. fully set up yet.
  1328. This means you can't write memory or access chip registers;
  1329. you can't even verify that a flash chip is present.
  1330. That's done later in event handlers, of which the target @code{reset-init}
  1331. handler is one of the most important.
  1332. Except on microcontrollers, the basic job of @code{reset-init} event
  1333. handlers is setting up flash and DRAM, as normally handled by boot loaders.
  1334. Microcontrollers rarely use boot loaders; they run right out of their
  1335. on-chip flash and SRAM memory. But they may want to use one of these
  1336. handlers too, if just for developer convenience.
  1337. @quotation Note
  1338. Because this is so very board-specific, and chip-specific, no examples
  1339. are included here.
  1340. Instead, look at the board config files distributed with OpenOCD.
  1341. If you have a boot loader, its source code will help; so will
  1342. configuration files for other JTAG tools
  1343. (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
  1344. @end quotation
  1345. Some of this code could probably be shared between different boards.
  1346. For example, setting up a DRAM controller often doesn't differ by
  1347. much except the bus width (16 bits or 32?) and memory timings, so a
  1348. reusable TCL procedure loaded by the @file{target.cfg} file might take
  1349. those as parameters.
  1350. Similarly with oscillator, PLL, and clock setup;
  1351. and disabling the watchdog.
  1352. Structure the code cleanly, and provide comments to help
  1353. the next developer doing such work.
  1354. (@emph{You might be that next person} trying to reuse init code!)
  1355. The last thing normally done in a @code{reset-init} handler is probing
  1356. whatever flash memory was configured. For most chips that needs to be
  1357. done while the associated target is halted, either because JTAG memory
  1358. access uses the CPU or to prevent conflicting CPU access.
  1359. @subsection JTAG Clock Rate
  1360. Before your @code{reset-init} handler has set up
  1361. the PLLs and clocking, you may need to run with
  1362. a low JTAG clock rate.
  1363. @xref{jtagspeed,,JTAG Speed}.
  1364. Then you'd increase that rate after your handler has
  1365. made it possible to use the faster JTAG clock.
  1366. When the initial low speed is board-specific, for example
  1367. because it depends on a board-specific oscillator speed, then
  1368. you should probably set it up in the board config file;
  1369. if it's target-specific, it belongs in the target config file.
  1370. For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
  1371. @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
  1372. is one sixth of the CPU clock; or one eighth for ARM11 cores.
  1373. Consult chip documentation to determine the peak JTAG clock rate,
  1374. which might be less than that.
  1375. @quotation Warning
  1376. On most ARMs, JTAG clock detection is coupled to the core clock, so
  1377. software using a @option{wait for interrupt} operation blocks JTAG access.
  1378. Adaptive clocking provides a partial workaround, but a more complete
  1379. solution just avoids using that instruction with JTAG debuggers.
  1380. @end quotation
  1381. If both the chip and the board support adaptive clocking,
  1382. use the @command{jtag_rclk}
  1383. command, in case your board is used with JTAG adapter which
  1384. also supports it. Otherwise use @command{adapter_khz}.
  1385. Set the slow rate at the beginning of the reset sequence,
  1386. and the faster rate as soon as the clocks are at full speed.
  1387. @anchor{theinitboardprocedure}
  1388. @subsection The init_board procedure
  1389. @cindex init_board procedure
  1390. The concept of @code{init_board} procedure is very similar to @code{init_targets}
  1391. (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
  1392. configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
  1393. (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
  1394. spearate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
  1395. everything target specific (internal flash, internal RAM, etc.) and the second one to configure
  1396. everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
  1397. Additionally ``linear'' board config file will most likely fail when target config file uses
  1398. @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
  1399. so separating these two configuration stages is very convenient, as the easiest way to overcome this
  1400. problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
  1401. need to override @code{init_targets} defined in target config files when they only need to to add some specifics.
  1402. Just as @code{init_targets}, the @code{init_board} procedure can be overriden by ``next level'' script (which sources
  1403. the original), allowing greater code reuse.
  1404. @example
  1405. ### board_file.cfg ###
  1406. # source target file that does most of the config in init_targets
  1407. source [find target/target.cfg]
  1408. proc enable_fast_clock @{@} @{
  1409. # enables fast on-board clock source
  1410. # configures the chip to use it
  1411. @}
  1412. # initialize only board specifics - reset, clock, adapter frequency
  1413. proc init_board @{@} @{
  1414. reset_config trst_and_srst trst_pulls_srst
  1415. $_TARGETNAME configure -event reset-init @{
  1416. adapter_khz 1
  1417. enable_fast_clock
  1418. adapter_khz 10000
  1419. @}
  1420. @}
  1421. @end example
  1422. @section Target Config Files
  1423. @cindex config file, target
  1424. @cindex target config file
  1425. Board config files communicate with target config files using
  1426. naming conventions as described above, and may source one or
  1427. more target config files like this:
  1428. @example
  1429. source [find target/FOOBAR.cfg]
  1430. @end example
  1431. The point of a target config file is to package everything
  1432. about a given chip that board config files need to know.
  1433. In summary the target files should contain
  1434. @enumerate
  1435. @item Set defaults
  1436. @item Add TAPs to the scan chain
  1437. @item Add CPU targets (includes GDB support)
  1438. @item CPU/Chip/CPU-Core specific features
  1439. @item On-Chip flash
  1440. @end enumerate
  1441. As a rule of thumb, a target file sets up only one chip.
  1442. For a microcontroller, that will often include a single TAP,
  1443. which is a CPU needing a GDB target, and its on-chip flash.
  1444. More complex chips may include multiple TAPs, and the target
  1445. config file may need to define them all before OpenOCD
  1446. can talk to the chip.
  1447. For example, some phone chips have JTAG scan chains that include
  1448. an ARM core for operating system use, a DSP,
  1449. another ARM core embedded in an image processing engine,
  1450. and other processing engines.
  1451. @subsection Default Value Boiler Plate Code
  1452. All target configuration files should start with code like this,
  1453. letting board config files express environment-specific
  1454. differences in how things should be set up.
  1455. @example
  1456. # Boards may override chip names, perhaps based on role,
  1457. # but the default should match what the vendor uses
  1458. if @{ [info exists CHIPNAME] @} @{
  1459. set _CHIPNAME $CHIPNAME
  1460. @} else @{
  1461. set _CHIPNAME sam7x256
  1462. @}
  1463. # ONLY use ENDIAN with targets that can change it.
  1464. if @{ [info exists ENDIAN] @} @{
  1465. set _ENDIAN $ENDIAN
  1466. @} else @{
  1467. set _ENDIAN little
  1468. @}
  1469. # TAP identifiers may change as chips mature, for example with
  1470. # new revision fields (the "3" here). Pick a good default; you
  1471. # can pass several such identifiers to the "jtag newtap" command.
  1472. if @{ [info exists CPUTAPID ] @} @{
  1473. set _CPUTAPID $CPUTAPID
  1474. @} else @{
  1475. set _CPUTAPID 0x3f0f0f0f
  1476. @}
  1477. @end example
  1478. @c but 0x3f0f0f0f is for an str73x part ...
  1479. @emph{Remember:} Board config files may include multiple target
  1480. config files, or the same target file multiple times
  1481. (changing at least @code{CHIPNAME}).
  1482. Likewise, the target configuration file should define
  1483. @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
  1484. use it later on when defining debug targets:
  1485. @example
  1486. set _TARGETNAME $_CHIPNAME.cpu
  1487. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  1488. @end example
  1489. @subsection Adding TAPs to the Scan Chain
  1490. After the ``defaults'' are set up,
  1491. add the TAPs on each chip to the JTAG scan chain.
  1492. @xref{TAP Declaration}, and the naming convention
  1493. for taps.
  1494. In the simplest case the chip has only one TAP,
  1495. probably for a CPU or FPGA.
  1496. The config file for the Atmel AT91SAM7X256
  1497. looks (in part) like this:
  1498. @example
  1499. jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  1500. @end example
  1501. A board with two such at91sam7 chips would be able
  1502. to source such a config file twice, with different
  1503. values for @code{CHIPNAME}, so
  1504. it adds a different TAP each time.
  1505. If there are nonzero @option{-expected-id} values,
  1506. OpenOCD attempts to verify the actual tap id against those values.
  1507. It will issue error messages if there is mismatch, which
  1508. can help to pinpoint problems in OpenOCD configurations.
  1509. @example
  1510. JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
  1511. (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
  1512. ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
  1513. ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
  1514. ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
  1515. @end example
  1516. There are more complex examples too, with chips that have
  1517. multiple TAPs. Ones worth looking at include:
  1518. @itemize
  1519. @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
  1520. plus a JRC to enable them
  1521. @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
  1522. @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
  1523. is not currently used)
  1524. @end itemize
  1525. @subsection Add CPU targets
  1526. After adding a TAP for a CPU, you should set it up so that
  1527. GDB and other commands can use it.
  1528. @xref{CPU Configuration}.
  1529. For the at91sam7 example above, the command can look like this;
  1530. note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
  1531. to little endian, and this chip doesn't support changing that.
  1532. @example
  1533. set _TARGETNAME $_CHIPNAME.cpu
  1534. target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
  1535. @end example
  1536. Work areas are small RAM areas associated with CPU targets.
  1537. They are used by OpenOCD to speed up downloads,
  1538. and to download small snippets of code to program flash chips.
  1539. If the chip includes a form of ``on-chip-ram'' - and many do - define
  1540. a work area if you can.
  1541. Again using the at91sam7 as an example, this can look like:
  1542. @example
  1543. $_TARGETNAME configure -work-area-phys 0x00200000 \
  1544. -work-area-size 0x4000 -work-area-backup 0
  1545. @end example
  1546. @anchor{definecputargetsworkinginsmp}
  1547. @subsection Define CPU targets working in SMP
  1548. @cindex SMP
  1549. After setting targets, you can define a list of targets working in SMP.
  1550. @example
  1551. set _TARGETNAME_1 $_CHIPNAME.cpu1
  1552. set _TARGETNAME_2 $_CHIPNAME.cpu2
  1553. target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
  1554. -coreid 0 -dbgbase $_DAP_DBG1
  1555. target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
  1556. -coreid 1 -dbgbase $_DAP_DBG2
  1557. #define 2 targets working in smp.
  1558. target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
  1559. @end example
  1560. In the above example on cortex_a8, 2 cpus are working in SMP.
  1561. In SMP only one GDB instance is created and :
  1562. @itemize @bullet
  1563. @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
  1564. @item halt command triggers the halt of all targets in the list.
  1565. @item resume command triggers the write context and the restart of all targets in the list.
  1566. @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
  1567. @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
  1568. displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
  1569. @end itemize
  1570. The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
  1571. command have been implemented.
  1572. @itemize @bullet
  1573. @item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
  1574. @item cortex_a8 smp_off : disable SMP mode, the current target is the one
  1575. displayed in the GDB session, only this target is now controlled by GDB
  1576. session. This behaviour is useful during system boot up.
  1577. @item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
  1578. following example.
  1579. @end itemize
  1580. @example
  1581. >cortex_a8 smp_gdb
  1582. gdb coreid 0 -> -1
  1583. #0 : coreid 0 is displayed to GDB ,
  1584. #-> -1 : next resume triggers a real resume
  1585. > cortex_a8 smp_gdb 1
  1586. gdb coreid 0 -> 1
  1587. #0 :coreid 0 is displayed to GDB ,
  1588. #->1 : next resume displays coreid 1 to GDB
  1589. > resume
  1590. > cortex_a8 smp_gdb
  1591. gdb coreid 1 -> 1
  1592. #1 :coreid 1 is displayed to GDB ,
  1593. #->1 : next resume displays coreid 1 to GDB
  1594. > cortex_a8 smp_gdb -1
  1595. gdb coreid 1 -> -1
  1596. #1 :coreid 1 is displayed to GDB,
  1597. #->-1 : next resume triggers a real resume
  1598. @end example
  1599. @subsection Chip Reset Setup
  1600. As a rule, you should put the @command{reset_config} command
  1601. into the board file. Most things you think you know about a
  1602. chip can be tweaked by the board.
  1603. Some chips have specific ways the TRST and SRST signals are
  1604. managed. In the unusual case that these are @emph{chip specific}
  1605. and can never be changed by board wiring, they could go here.
  1606. For example, some chips can't support JTAG debugging without
  1607. both signals.
  1608. Provide a @code{reset-assert} event handler if you can.
  1609. Such a handler uses JTAG operations to reset the target,
  1610. letting this target config be used in systems which don't
  1611. provide the optional SRST signal, or on systems where you
  1612. don't want to reset all targets at once.
  1613. Such a handler might write to chip registers to force a reset,
  1614. use a JRC to do that (preferable -- the target may be wedged!),
  1615. or force a watchdog timer to trigger.
  1616. (For Cortex-M3 targets, this is not necessary. The target
  1617. driver knows how to use trigger an NVIC reset when SRST is
  1618. not available.)
  1619. Some chips need special attention during reset handling if
  1620. they're going to be used with JTAG.
  1621. An example might be needing to send some commands right
  1622. after the target's TAP has been reset, providing a
  1623. @code{reset-deassert-post} event handler that writes a chip
  1624. register to report that JTAG debugging is being done.
  1625. Another would be reconfiguring the watchdog so that it stops
  1626. counting while the core is halted in the debugger.
  1627. JTAG clocking constraints often change during reset, and in
  1628. some cases target config files (rather than board config files)
  1629. are the right places to handle some of those issues.
  1630. For example, immediately after reset most chips run using a
  1631. slower clock than they will use later.
  1632. That means that after reset (and potentially, as OpenOCD
  1633. first starts up) they must use a slower JTAG clock rate
  1634. than they will use later.
  1635. @xref{jtagspeed,,JTAG Speed}.
  1636. @quotation Important
  1637. When you are debugging code that runs right after chip
  1638. reset, getting these issues right is critical.
  1639. In particular, if you see intermittent failures when
  1640. OpenOCD verifies the scan chain after reset,
  1641. look at how you are setting up JTAG clocking.
  1642. @end quotation
  1643. @anchor{theinittargetsprocedure}
  1644. @subsection The init_targets procedure
  1645. @cindex init_targets procedure
  1646. Target config files can either be ``linear'' (script executed line-by-line when parsed in
  1647. configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
  1648. procedure called @code{init_targets}, which will be executed when entering run stage
  1649. (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
  1650. Such procedure can be overriden by ``next level'' script (which sources the original).
  1651. This concept faciliates code reuse when basic target config files provide generic configuration
  1652. procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
  1653. a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
  1654. because sourcing them executes every initialization commands they provide.
  1655. @example
  1656. ### generic_file.cfg ###
  1657. proc setup_my_chip @{chip_name flash_size ram_size@} @{
  1658. # basic initialization procedure ...
  1659. @}
  1660. proc init_targets @{@} @{
  1661. # initializes generic chip with 4kB of flash and 1kB of RAM
  1662. setup_my_chip MY_GENERIC_CHIP 4096 1024
  1663. @}
  1664. ### specific_file.cfg ###
  1665. source [find target/generic_file.cfg]
  1666. proc init_targets @{@} @{
  1667. # initializes specific chip with 128kB of flash and 64kB of RAM
  1668. setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
  1669. @}
  1670. @end example
  1671. The easiest way to convert ``linear'' config files to @code{init_targets} version is to
  1672. enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
  1673. For an example of this scheme see LPC2000 target config files.
  1674. The @code{init_boards} procedure is a similar concept concerning board config files
  1675. (@xref{theinitboardprocedure,,The init_board procedure}.)
  1676. @subsection ARM Core Specific Hacks
  1677. If the chip has a DCC, enable it. If the chip is an ARM9 with some
  1678. special high speed download features - enable it.
  1679. If present, the MMU, the MPU and the CACHE should be disabled.
  1680. Some ARM cores are equipped with trace support, which permits
  1681. examination of the instruction and data bus activity. Trace
  1682. activity is controlled through an ``Embedded Trace Module'' (ETM)
  1683. on one of the core's scan chains. The ETM emits voluminous data
  1684. through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
  1685. If you are using an external trace port,
  1686. configure it in your board config file.
  1687. If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
  1688. configure it in your target config file.
  1689. @example
  1690. etm config $_TARGETNAME 16 normal full etb
  1691. etb config $_TARGETNAME $_CHIPNAME.etb
  1692. @end example
  1693. @subsection Internal Flash Configuration
  1694. This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
  1695. @b{Never ever} in the ``target configuration file'' define any type of
  1696. flash that is external to the chip. (For example a BOOT flash on
  1697. Chip Select 0.) Such flash information goes in a board file - not
  1698. the TARGET (chip) file.
  1699. Examples:
  1700. @itemize @bullet
  1701. @item at91sam7x256 - has 256K flash YES enable it.
  1702. @item str912 - has flash internal YES enable it.
  1703. @item imx27 - uses boot flash on CS0 - it goes in the board file.
  1704. @item pxa270 - again - CS0 flash - it goes in the board file.
  1705. @end itemize
  1706. @anchor{translatingconfigurationfiles}
  1707. @section Translating Configuration Files
  1708. @cindex translation
  1709. If you have a configuration file for another hardware debugger
  1710. or toolset (Abatron, BDI2000, BDI3000, CCS,
  1711. Lauterbach, Segger, Macraigor, etc.), translating
  1712. it into OpenOCD syntax is often quite straightforward. The most tricky
  1713. part of creating a configuration script is oftentimes the reset init
  1714. sequence where e.g. PLLs, DRAM and the like is set up.
  1715. One trick that you can use when translating is to write small
  1716. Tcl procedures to translate the syntax into OpenOCD syntax. This
  1717. can avoid manual translation errors and make it easier to
  1718. convert other scripts later on.
  1719. Example of transforming quirky arguments to a simple search and
  1720. replace job:
  1721. @example
  1722. # Lauterbach syntax(?)
  1723. #
  1724. # Data.Set c15:0x042f %long 0x40000015
  1725. #
  1726. # OpenOCD syntax when using procedure below.
  1727. #
  1728. # setc15 0x01 0x00050078
  1729. proc setc15 @{regs value@} @{
  1730. global TARGETNAME
  1731. echo [format "set p15 0x%04x, 0x%08x" $regs $value]
  1732. arm mcr 15 [expr ($regs>>12)&0x7] \
  1733. [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
  1734. [expr ($regs>>8)&0x7] $value
  1735. @}
  1736. @end example
  1737. @node Daemon Configuration
  1738. @chapter Daemon Configuration
  1739. @cindex initialization
  1740. The commands here are commonly found in the openocd.cfg file and are
  1741. used to specify what TCP/IP ports are used, and how GDB should be
  1742. supported.
  1743. @anchor{configurationstage}
  1744. @section Configuration Stage
  1745. @cindex configuration stage
  1746. @cindex config command
  1747. When the OpenOCD server process starts up, it enters a
  1748. @emph{configuration stage} which is the only time that
  1749. certain commands, @emph{configuration commands}, may be issued.
  1750. Normally, configuration commands are only available
  1751. inside startup scripts.
  1752. In this manual, the definition of a configuration command is
  1753. presented as a @emph{Config Command}, not as a @emph{Command}
  1754. which may be issued interactively.
  1755. The runtime @command{help} command also highlights configuration
  1756. commands, and those which may be issued at any time.
  1757. Those configuration commands include declaration of TAPs,
  1758. flash banks,
  1759. the interface used for JTAG communication,
  1760. and other basic setup.
  1761. The server must leave the configuration stage before it
  1762. may access or activate TAPs.
  1763. After it leaves this stage, configuration commands may no
  1764. longer be issued.
  1765. @anchor{enteringtherunstage}
  1766. @section Entering the Run Stage
  1767. The first thing OpenOCD does after leaving the configuration
  1768. stage is to verify that it can talk to the scan chain
  1769. (list of TAPs) which has been configured.
  1770. It will warn if it doesn't find TAPs it expects to find,
  1771. or finds TAPs that aren't supposed to be there.
  1772. You should see no errors at this point.
  1773. If you see errors, resolve them by correcting the
  1774. commands you used to configure the server.
  1775. Common errors include using an initial JTAG speed that's too
  1776. fast, and not providing the right IDCODE values for the TAPs
  1777. on the scan chain.
  1778. Once OpenOCD has entered the run stage, a number of commands
  1779. become available.
  1780. A number of these relate to the debug targets you may have declared.
  1781. For example, the @command{mww} command will not be available until
  1782. a target has been successfuly instantiated.
  1783. If you want to use those commands, you may need to force
  1784. entry to the run stage.
  1785. @deffn {Config Command} init
  1786. This command terminates the configuration stage and
  1787. enters the run stage. This helps when you need to have
  1788. the startup scripts manage tasks such as resetting the target,
  1789. programming flash, etc. To reset the CPU upon startup, add "init" and
  1790. "reset" at the end of the config script or at the end of the OpenOCD
  1791. command line using the @option{-c} command line switch.
  1792. If this command does not appear in any startup/configuration file
  1793. OpenOCD executes the command for you after processing all
  1794. configuration files and/or command line options.
  1795. @b{NOTE:} This command normally occurs at or near the end of your
  1796. openocd.cfg file to force OpenOCD to ``initialize'' and make the
  1797. targets ready. For example: If your openocd.cfg file needs to
  1798. read/write memory on your target, @command{init} must occur before
  1799. the memory read/write commands. This includes @command{nand probe}.
  1800. @end deffn
  1801. @deffn {Overridable Procedure} jtag_init
  1802. This is invoked at server startup to verify that it can talk
  1803. to the scan chain (list of TAPs) which has been configured.
  1804. The default implementation first tries @command{jtag arp_init},
  1805. which uses only a lightweight JTAG reset before examining the
  1806. scan chain.
  1807. If that fails, it tries again, using a harder reset
  1808. from the overridable procedure @command{init_reset}.
  1809. Implementations must have verified the JTAG scan chain before
  1810. they return.
  1811. This is done by calling @command{jtag arp_init}
  1812. (or @command{jtag arp_init-reset}).
  1813. @end deffn
  1814. @anchor{tcpipports}
  1815. @section TCP/IP Ports
  1816. @cindex TCP port
  1817. @cindex server
  1818. @cindex port
  1819. @cindex security
  1820. The OpenOCD server accepts remote commands in several syntaxes.
  1821. Each syntax uses a different TCP/IP port, which you may specify
  1822. only during configuration (before those ports are opened).
  1823. For reasons including security, you may wish to prevent remote
  1824. access using one or more of these ports.
  1825. In such cases, just specify the relevant port number as zero.
  1826. If you disable all access through TCP/IP, you will need to
  1827. use the command line @option{-pipe} option.
  1828. @deffn {Command} gdb_port [number]
  1829. @cindex GDB server
  1830. Normally gdb listens to a TCP/IP port, but GDB can also
  1831. communicate via pipes(stdin/out or named pipes). The name
  1832. "gdb_port" stuck because it covers probably more than 90% of
  1833. the normal use cases.
  1834. No arguments reports GDB port. "pipe" means listen to stdin
  1835. output to stdout, an integer is base port number, "disable"
  1836. disables the gdb server.
  1837. When using "pipe", also use log_output to redirect the log
  1838. output to a file so as not to flood the stdin/out pipes.
  1839. The -p/--pipe option is deprecated and a warning is printed
  1840. as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
  1841. Any other string is interpreted as named pipe to listen to.
  1842. Output pipe is the same name as input pipe, but with 'o' appended,
  1843. e.g. /var/gdb, /var/gdbo.
  1844. The GDB port for the first target will be the base port, the
  1845. second target will listen on gdb_port + 1, and so on.
  1846. When not specified during the configuration stage,
  1847. the port @var{number} defaults to 3333.
  1848. @end deffn
  1849. @deffn {Command} tcl_port [number]
  1850. Specify or query the port used for a simplified RPC
  1851. connection that can be used by clients to issue TCL commands and get the
  1852. output from the Tcl engine.
  1853. Intended as a machine interface.
  1854. When not specified during the configuration stage,
  1855. the port @var{number} defaults to 6666.
  1856. @end deffn
  1857. @deffn {Command} telnet_port [number]
  1858. Specify or query the
  1859. port on which to listen for incoming telnet connections.
  1860. This port is intended for interaction with one human through TCL commands.
  1861. When not specified during the configuration stage,
  1862. the port @var{number} defaults to 4444.
  1863. When specified as zero, this port is not activated.
  1864. @end deffn
  1865. @anchor{gdbconfiguration}
  1866. @section GDB Configuration
  1867. @cindex GDB
  1868. @cindex GDB configuration
  1869. You can reconfigure some GDB behaviors if needed.
  1870. The ones listed here are static and global.
  1871. @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
  1872. @xref{targetevents,,Target Events}, about configuring target-specific event handling.
  1873. @anchor{gdbbreakpointoverride}
  1874. @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
  1875. Force breakpoint type for gdb @command{break} commands.
  1876. This option supports GDB GUIs which don't
  1877. distinguish hard versus soft breakpoints, if the default OpenOCD and
  1878. GDB behaviour is not sufficient. GDB normally uses hardware
  1879. breakpoints if the memory map has been set up for flash regions.
  1880. @end deffn
  1881. @anchor{gdbflashprogram}
  1882. @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
  1883. Set to @option{enable} to cause OpenOCD to program the flash memory when a
  1884. vFlash packet is received.
  1885. The default behaviour is @option{enable}.
  1886. @end deffn
  1887. @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
  1888. Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
  1889. requested. GDB will then know when to set hardware breakpoints, and program flash
  1890. using the GDB load command. @command{gdb_flash_program enable} must also be enabled
  1891. for flash programming to work.
  1892. Default behaviour is @option{enable}.
  1893. @xref{gdbflashprogram,,gdb_flash_program}.
  1894. @end deffn
  1895. @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
  1896. Specifies whether data aborts cause an error to be reported
  1897. by GDB memory read packets.
  1898. The default behaviour is @option{disable};
  1899. use @option{enable} see these errors reported.
  1900. @end deffn
  1901. @anchor{eventpolling}
  1902. @section Event Polling
  1903. Hardware debuggers are parts of asynchronous systems,
  1904. where significant events can happen at any time.
  1905. The OpenOCD server needs to detect some of these events,
  1906. so it can report them to through TCL command line
  1907. or to GDB.
  1908. Examples of such events include:
  1909. @itemize
  1910. @item One of the targets can stop running ... maybe it triggers
  1911. a code breakpoint or data watchpoint, or halts itself.
  1912. @item Messages may be sent over ``debug message'' channels ... many
  1913. targets support such messages sent over JTAG,
  1914. for receipt by the person debugging or tools.
  1915. @item Loss of power ... some adapters can detect these events.
  1916. @item Resets not issued through JTAG ... such reset sources
  1917. can include button presses or other system hardware, sometimes
  1918. including the target itself (perhaps through a watchdog).
  1919. @item Debug instrumentation sometimes supports event triggering
  1920. such as ``trace buffer full'' (so it can quickly be emptied)
  1921. or other signals (to correlate with code behavior).
  1922. @end itemize
  1923. None of those events are signaled through standard JTAG signals.
  1924. However, most conventions for JTAG connectors include voltage
  1925. level and system reset (SRST) signal detection.
  1926. Some connectors also include instrumentation signals, which
  1927. can imply events when those signals are inputs.
  1928. In general, OpenOCD needs to periodically check for those events,
  1929. either by looking at the status of signals on the JTAG connector
  1930. or by sending synchronous ``tell me your status'' JTAG requests
  1931. to the various active targets.
  1932. There is a command to manage and monitor that polling,
  1933. which is normally done in the background.
  1934. @deffn Command poll [@option{on}|@option{off}]
  1935. Poll the current target for its current state.
  1936. (Also, @pxref{targetcurstate,,target curstate}.)
  1937. If that target is in debug mode, architecture
  1938. specific information about the current state is printed.
  1939. An optional parameter
  1940. allows background polling to be enabled and disabled.
  1941. You could use this from the TCL command shell, or
  1942. from GDB using @command{monitor poll} command.
  1943. Leave background polling enabled while you're using GDB.
  1944. @example
  1945. > poll
  1946. background polling: on
  1947. target state: halted
  1948. target halted in ARM state due to debug-request, \
  1949. current mode: Supervisor
  1950. cpsr: 0x800000d3 pc: 0x11081bfc
  1951. MMU: disabled, D-Cache: disabled, I-Cache: enabled
  1952. >
  1953. @end example
  1954. @end deffn
  1955. @node Debug Adapter Configuration
  1956. @chapter Debug Adapter Configuration
  1957. @cindex config file, interface
  1958. @cindex interface config file
  1959. Correctly installing OpenOCD includes making your operating system give
  1960. OpenOCD access to debug adapters. Once that has been done, Tcl commands
  1961. are used to select which one is used, and to configure how it is used.
  1962. @quotation Note
  1963. Because OpenOCD started out with a focus purely on JTAG, you may find
  1964. places where it wrongly presumes JTAG is the only transport protocol
  1965. in use. Be aware that recent versions of OpenOCD are removing that
  1966. limitation. JTAG remains more functional than most other transports.
  1967. Other transports do not support boundary scan operations, or may be
  1968. specific to a given chip vendor. Some might be usable only for
  1969. programming flash memory, instead of also for debugging.
  1970. @end quotation
  1971. Debug Adapters/Interfaces/Dongles are normally configured
  1972. through commands in an interface configuration
  1973. file which is sourced by your @file{openocd.cfg} file, or
  1974. through a command line @option{-f interface/....cfg} option.
  1975. @example
  1976. source [find interface/olimex-jtag-tiny.cfg]
  1977. @end example
  1978. These commands tell
  1979. OpenOCD what type of JTAG adapter you have, and how to talk to it.
  1980. A few cases are so simple that you only need to say what driver to use:
  1981. @example
  1982. # jlink interface
  1983. interface jlink
  1984. @end example
  1985. Most adapters need a bit more configuration than that.
  1986. @section Interface Configuration
  1987. The interface command tells OpenOCD what type of debug adapter you are
  1988. using. Depending on the type of adapter, you may need to use one or
  1989. more additional commands to further identify or configure the adapter.
  1990. @deffn {Config Command} {interface} name
  1991. Use the interface driver @var{name} to connect to the
  1992. target.
  1993. @end deffn
  1994. @deffn Command {interface_list}
  1995. List the debug adapter drivers that have been built into
  1996. the running copy of OpenOCD.
  1997. @end deffn
  1998. @deffn Command {interface transports} transport_name+
  1999. Specifies the transports supported by this debug adapter.
  2000. The adapter driver builds-in similar knowledge; use this only
  2001. when external configuration (such as jumpering) changes what
  2002. the hardware can support.
  2003. @end deffn
  2004. @deffn Command {adapter_name}
  2005. Returns the name of the debug adapter driver being used.
  2006. @end deffn
  2007. @section Interface Drivers
  2008. Each of the interface drivers listed here must be explicitly
  2009. enabled when OpenOCD is configured, in order to be made
  2010. available at run time.
  2011. @deffn {Interface Driver} {amt_jtagaccel}
  2012. Amontec Chameleon in its JTAG Accelerator configuration,
  2013. connected to a PC's EPP mode parallel port.
  2014. This defines some driver-specific commands:
  2015. @deffn {Config Command} {parport_port} number
  2016. Specifies either the address of the I/O port (default: 0x378 for LPT1) or
  2017. the number of the @file{/dev/parport} device.
  2018. @end deffn
  2019. @deffn {Config Command} rtck [@option{enable}|@option{disable}]
  2020. Displays status of RTCK option.
  2021. Optionally sets that option first.
  2022. @end deffn
  2023. @end deffn
  2024. @deffn {Interface Driver} {arm-jtag-ew}
  2025. Olimex ARM-JTAG-EW USB adapter
  2026. This has one driver-specific command:
  2027. @deffn Command {armjtagew_info}
  2028. Logs some status
  2029. @end deffn
  2030. @end deffn
  2031. @deffn {Interface Driver} {at91rm9200}
  2032. Supports bitbanged JTAG from the local system,
  2033. presuming that system is an Atmel AT91rm9200
  2034. and a specific set of GPIOs is used.
  2035. @c command: at91rm9200_device NAME
  2036. @c chooses among list of bit configs ... only one option
  2037. @end deffn
  2038. @deffn {Interface Driver} {dummy}
  2039. A dummy software-only driver for debugging.
  2040. @end deffn
  2041. @deffn {Interface Driver} {ep93xx}
  2042. Cirrus Logic EP93xx based single-board computer bit-banging (in development)
  2043. @end deffn
  2044. @deffn {Interface Driver} {ft2232}
  2045. FTDI FT2232 (USB) based devices over one of the userspace libraries.
  2046. Note that this driver has several flaws and the @command{ftdi} driver is
  2047. recommended as its replacement.
  2048. These interfaces have several commands, used to configure the driver
  2049. before initializing the JTAG scan chain:
  2050. @deffn {Config Command} {ft2232_device_desc} description
  2051. Provides the USB device description (the @emph{iProduct string})
  2052. of the FTDI FT2232 device. If not
  2053. specified, the FTDI default value is used. This setting is only valid
  2054. if compiled with FTD2XX support.
  2055. @end deffn
  2056. @deffn {Config Command} {ft2232_serial} serial-number
  2057. Specifies the @var{serial-number} of the FTDI FT2232 device to use,
  2058. in case the vendor provides unique IDs and more than one FT2232 device
  2059. is connected to the host.
  2060. If not specified, serial numbers are not considered.
  2061. (Note that USB serial numbers can be arbitrary Unicode strings,
  2062. and are not restricted to containing only decimal digits.)
  2063. @end deffn
  2064. @deffn {Config Command} {ft2232_layout} name
  2065. Each vendor's FT2232 device can use different GPIO signals
  2066. to control output-enables, reset signals, and LEDs.
  2067. Currently valid layout @var{name} values include:
  2068. @itemize @minus
  2069. @item @b{axm0432_jtag} Axiom AXM-0432
  2070. @item @b{comstick} Hitex STR9 comstick
  2071. @item @b{cortino} Hitex Cortino JTAG interface
  2072. @item @b{evb_lm3s811} TI/Luminary Micro EVB_LM3S811 as a JTAG interface,
  2073. either for the local Cortex-M3 (SRST only)
  2074. or in a passthrough mode (neither SRST nor TRST)
  2075. This layout can not support the SWO trace mechanism, and should be
  2076. used only for older boards (before rev C).
  2077. @item @b{luminary_icdi} This layout should be used with most TI/Luminary
  2078. eval boards, including Rev C LM3S811 eval boards and the eponymous
  2079. ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
  2080. to debug some other target. It can support the SWO trace mechanism.
  2081. @item @b{flyswatter} Tin Can Tools Flyswatter
  2082. @item @b{icebear} ICEbear JTAG adapter from Section 5
  2083. @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
  2084. @item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
  2085. @item @b{m5960} American Microsystems M5960
  2086. @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
  2087. @item @b{oocdlink} OOCDLink
  2088. @c oocdlink ~= jtagkey_prototype_v1
  2089. @item @b{redbee-econotag} Integrated with a Redbee development board.
  2090. @item @b{redbee-usb} Integrated with a Redbee USB-stick development board.
  2091. @item @b{sheevaplug} Marvell Sheevaplug development kit
  2092. @item @b{signalyzer} Xverve Signalyzer
  2093. @item @b{stm32stick} Hitex STM32 Performance Stick
  2094. @item @b{turtelizer2} egnite Software turtelizer2
  2095. @item @b{usbjtag} "USBJTAG-1" layout described in the OpenOCD diploma thesis
  2096. @end itemize
  2097. @end deffn
  2098. @deffn {Config Command} {ft2232_vid_pid} [vid pid]+
  2099. The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
  2100. default values are used.
  2101. Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
  2102. @example
  2103. ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
  2104. @end example
  2105. @end deffn
  2106. @deffn {Config Command} {ft2232_latency} ms
  2107. On some systems using FT2232 based JTAG interfaces the FT_Read function call in
  2108. ft2232_read() fails to return the expected number of bytes. This can be caused by
  2109. USB communication delays and has proved hard to reproduce and debug. Setting the
  2110. FT2232 latency timer to a larger value increases delays for short USB packets but it
  2111. also reduces the risk of timeouts before receiving the expected number of bytes.
  2112. The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
  2113. @end deffn
  2114. @deffn {Config Command} {ft2232_channel} channel
  2115. Used to select the channel of the ft2232 chip to use (between 1 and 4).
  2116. The default value is 1.
  2117. @end deffn
  2118. For example, the interface config file for a
  2119. Turtelizer JTAG Adapter looks something like this:
  2120. @example
  2121. interface ft2232
  2122. ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
  2123. ft2232_layout turtelizer2
  2124. ft2232_vid_pid 0x0403 0xbdc8
  2125. @end example
  2126. @end deffn
  2127. @deffn {Interface Driver} {ftdi}
  2128. This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
  2129. Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
  2130. It is a complete rewrite to address a large number of problems with the ft2232
  2131. interface driver.
  2132. The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
  2133. bypassing intermediate libraries like libftdi of D2XX. Performance-wise it is
  2134. consistently faster than the ft2232 driver, sometimes several times faster.
  2135. A major improvement of this driver is that support for new FTDI based adapters
  2136. can be added competely through configuration files, without the need to patch
  2137. and rebuild OpenOCD.
  2138. The driver uses a signal abstraction to enable Tcl configuration files to
  2139. define outputs for one or several FTDI GPIO. These outputs can then be
  2140. controlled using the @command{ftdi_set_signal} command. Special signal names
  2141. are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
  2142. will be used for their customary purpose.
  2143. Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
  2144. be controlled differently. In order to support tristateable signals such as
  2145. nSRST, both a data GPIO and an output-enable GPIO can be specified for each
  2146. signal. The following output buffer configurations are supported:
  2147. @itemize @minus
  2148. @item Push-pull with one FTDI output as (non-)inverted data line
  2149. @item Open drain with one FTDI output as (non-)inverted output-enable
  2150. @item Tristate with one FTDI output as (non-)inverted data line and another
  2151. FTDI output as (non-)inverted output-enable
  2152. @item Unbuffered, using the FTDI GPIO as a tristate output directly by
  2153. switching data and direction as necessary
  2154. @end itemize
  2155. These interfaces have several commands, used to configure the driver
  2156. before initializing the JTAG scan chain:
  2157. @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
  2158. The vendor ID and product ID of the adapter. If not specified, the FTDI
  2159. default values are used.
  2160. Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
  2161. @example
  2162. ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
  2163. @end example
  2164. @end deffn
  2165. @deffn {Config Command} {ftdi_device_desc} description
  2166. Provides the USB device description (the @emph{iProduct string})
  2167. of the adapter. If not specified, the device description is ignored
  2168. during device selection.
  2169. @end deffn
  2170. @deffn {Config Command} {ftdi_serial} serial-number
  2171. Specifies the @var{serial-number} of the adapter to use,
  2172. in case the vendor provides unique IDs and more than one adapter
  2173. is connected to the host.
  2174. If not specified, serial numbers are not considered.
  2175. (Note that USB serial numbers can be arbitrary Unicode strings,
  2176. and are not restricted to containing only decimal digits.)
  2177. @end deffn
  2178. @deffn {Config Command} {ftdi_channel} channel
  2179. Selects the channel of the FTDI device to use for MPSSE operations. Most
  2180. adapters use the default, channel 0, but there are exceptions.
  2181. @end deffn
  2182. @deffn {Config Command} {ftdi_layout_init} data direction
  2183. Specifies the initial values of the FTDI GPIO data and direction registers.
  2184. Each value is a 16-bit number corresponding to the concatenation of the high
  2185. and low FTDI GPIO registers. The values should be selected based on the
  2186. schematics of the adapter, such that all signals are set to safe levels with
  2187. minimal impact on the target system. Avoid floating inputs, conflicting outputs
  2188. and initially asserted reset signals.
  2189. @end deffn
  2190. @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-oe}|@option{-noe} oe_mask]
  2191. Creates a signal with the specified @var{name}, controlled by one or more FTDI
  2192. GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
  2193. register bitmasks to tell the driver the connection and type of the output
  2194. buffer driving the respective signal. @var{data_mask} is the bitmask for the
  2195. pin(s) connected to the data input of the output buffer. @option{-ndata} is
  2196. used with inverting data inputs and @option{-data} with non-inverting inputs.
  2197. The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
  2198. not-output-enable) input to the output buffer is connected.
  2199. Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
  2200. simple open-collector transistor driver would be specified with @option{-oe}
  2201. only. In that case the signal can only be set to drive low or to Hi-Z and the
  2202. driver will complain if the signal is set to drive high. Which means that if
  2203. it's a reset signal, @command{reset_config} must be specified as
  2204. @option{srst_open_drain}, not @option{srst_push_pull}.
  2205. A special case is provided when @option{-data} and @option{-oe} is set to the
  2206. same bitmask. Then the FTDI pin is considered being connected straight to the
  2207. target without any buffer. The FTDI pin is then switched between output and
  2208. input as necessary to provide the full set of low, high and Hi-Z
  2209. characteristics. In all other cases, the pins specified in a signal definition
  2210. are always driven by the FTDI.
  2211. @end deffn
  2212. @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
  2213. Set a previously defined signal to the specified level.
  2214. @itemize @minus
  2215. @item @option{0}, drive low
  2216. @item @option{1}, drive high
  2217. @item @option{z}, set to high-impedance
  2218. @end itemize
  2219. @end deffn
  2220. For example adapter definitions, see the configuration files shipped in the
  2221. @file{interface/ftdi} directory.
  2222. @end deffn
  2223. @deffn {Interface Driver} {remote_bitbang}
  2224. Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
  2225. with a remote process and sends ASCII encoded bitbang requests to that process
  2226. instead of directly driving JTAG.
  2227. The remote_bitbang driver is useful for debugging software running on
  2228. processors which are being simulated.
  2229. @deffn {Config Command} {remote_bitbang_port} number
  2230. Specifies the TCP port of the remote process to connect to or 0 to use UNIX
  2231. sockets instead of TCP.
  2232. @end deffn
  2233. @deffn {Config Command} {remote_bitbang_host} hostname
  2234. Specifies the hostname of the remote process to connect to using TCP, or the
  2235. name of the UNIX socket to use if remote_bitbang_port is 0.
  2236. @end deffn
  2237. For example, to connect remotely via TCP to the host foobar you might have
  2238. something like:
  2239. @example
  2240. interface remote_bitbang
  2241. remote_bitbang_port 3335
  2242. remote_bitbang_host foobar
  2243. @end example
  2244. To connect to another process running locally via UNIX sockets with socket
  2245. named mysocket:
  2246. @example
  2247. interface remote_bitbang
  2248. remote_bitbang_port 0
  2249. remote_bitbang_host mysocket
  2250. @end example
  2251. @end deffn
  2252. @deffn {Interface Driver} {usb_blaster}
  2253. USB JTAG/USB-Blaster compatibles over one of the userspace libraries
  2254. for FTDI chips. These interfaces have several commands, used to
  2255. configure the driver before initializing the JTAG scan chain:
  2256. @deffn {Config Command} {usb_blaster_device_desc} description
  2257. Provides the USB device description (the @emph{iProduct string})
  2258. of the FTDI FT245 device. If not
  2259. specified, the FTDI default value is used. This setting is only valid
  2260. if compiled with FTD2XX support.
  2261. @end deffn
  2262. @deffn {Config Command} {usb_blaster_vid_pid} vid pid
  2263. The vendor ID and product ID of the FTDI FT245 device. If not specified,
  2264. default values are used.
  2265. Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
  2266. Altera USB-Blaster (default):
  2267. @example
  2268. usb_blaster_vid_pid 0x09FB 0x6001
  2269. @end example
  2270. The following VID/PID is for Kolja Waschk's USB JTAG:
  2271. @example
  2272. usb_blaster_vid_pid 0x16C0 0x06AD
  2273. @end example
  2274. @end deffn
  2275. @deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
  2276. Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
  2277. female JTAG header). These pins can be used as SRST and/or TRST provided the
  2278. appropriate connections are made on the target board.
  2279. For example, to use pin 6 as SRST (as with an AVR board):
  2280. @example
  2281. $_TARGETNAME configure -event reset-assert \
  2282. "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
  2283. @end example
  2284. @end deffn
  2285. @end deffn
  2286. @deffn {Interface Driver} {gw16012}
  2287. Gateworks GW16012 JTAG programmer.
  2288. This has one driver-specific command:
  2289. @deffn {Config Command} {parport_port} [port_number]
  2290. Display either the address of the I/O port
  2291. (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
  2292. If a parameter is provided, first switch to use that port.
  2293. This is a write-once setting.
  2294. @end deffn
  2295. @end deffn
  2296. @deffn {Interface Driver} {jlink}
  2297. Segger J-Link family of USB adapters. It currently supports only the JTAG transport.
  2298. @quotation Compatibility Note
  2299. Segger released many firmware versions for the many harware versions they
  2300. produced. OpenOCD was extensively tested and intended to run on all of them,
  2301. but some combinations were reported as incompatible. As a general
  2302. recommendation, it is advisable to use the latest firmware version
  2303. available for each hardware version. However the current V8 is a moving
  2304. target, and Segger firmware versions released after the OpenOCD was
  2305. released may not be compatible. In such cases it is recommended to
  2306. revert to the last known functional version. For 0.5.0, this is from
  2307. "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
  2308. version is from "May 3 2012 18:36:22", packed with 4.46f.
  2309. @end quotation
  2310. @deffn {Command} {jlink caps}
  2311. Display the device firmware capabilities.
  2312. @end deffn
  2313. @deffn {Command} {jlink info}
  2314. Display various device information, like hardware version, firmware version, current bus status.
  2315. @end deffn
  2316. @deffn {Command} {jlink hw_jtag} [@option{2}|@option{3}]
  2317. Set the JTAG protocol version to be used. Without argument, show the actual JTAG protocol version.
  2318. @end deffn
  2319. @deffn {Command} {jlink config}
  2320. Display the J-Link configuration.
  2321. @end deffn
  2322. @deffn {Command} {jlink config kickstart} [val]
  2323. Set the Kickstart power on JTAG-pin 19. Without argument, show the Kickstart configuration.
  2324. @end deffn
  2325. @deffn {Command} {jlink config mac_address} [@option{ff:ff:ff:ff:ff:ff}]
  2326. Set the MAC address of the J-Link Pro. Without argument, show the MAC address.
  2327. @end deffn
  2328. @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
  2329. Set the IP configuration of the J-Link Pro, where A.B.C.D is the IP address,
  2330. E the bit of the subnet mask and
  2331. F.G.H.I the subnet mask. Without arguments, show the IP configuration.
  2332. @end deffn
  2333. @deffn {Command} {jlink config usb_address} [@option{0x00} to @option{0x03} or @option{0xff}]
  2334. Set the USB address; this will also change the product id. Without argument, show the USB address.
  2335. @end deffn
  2336. @deffn {Command} {jlink config reset}
  2337. Reset the current configuration.
  2338. @end deffn
  2339. @deffn {Command} {jlink config save}
  2340. Save the current configuration to the internal persistent storage.
  2341. @end deffn
  2342. @deffn {Config} {jlink pid} val
  2343. Set the USB PID of the interface. As a configuration command, it can be used only before 'init'.
  2344. @end deffn
  2345. @end deffn
  2346. @deffn {Interface Driver} {parport}
  2347. Supports PC parallel port bit-banging cables:
  2348. Wigglers, PLD download cable, and more.
  2349. These interfaces have several commands, used to configure the driver
  2350. before initializing the JTAG scan chain:
  2351. @deffn {Config Command} {parport_cable} name
  2352. Set the layout of the parallel port cable used to connect to the target.
  2353. This is a write-once setting.
  2354. Currently valid cable @var{name} values include:
  2355. @itemize @minus
  2356. @item @b{altium} Altium Universal JTAG cable.
  2357. @item @b{arm-jtag} Same as original wiggler except SRST and
  2358. TRST connections reversed and TRST is also inverted.
  2359. @item @b{chameleon} The Amontec Chameleon's CPLD when operated
  2360. in configuration mode. This is only used to
  2361. program the Chameleon itself, not a connected target.
  2362. @item @b{dlc5} The Xilinx Parallel cable III.
  2363. @item @b{flashlink} The ST Parallel cable.
  2364. @item @b{lattice} Lattice ispDOWNLOAD Cable
  2365. @item @b{old_amt_wiggler} The Wiggler configuration that comes with
  2366. some versions of
  2367. Amontec's Chameleon Programmer. The new version available from
  2368. the website uses the original Wiggler layout ('@var{wiggler}')
  2369. @item @b{triton} The parallel port adapter found on the
  2370. ``Karo Triton 1 Development Board''.
  2371. This is also the layout used by the HollyGates design
  2372. (see @uref{http://www.lartmaker.nl/projects/jtag/}).
  2373. @item @b{wiggler} The original Wiggler layout, also supported by
  2374. several clones, such as the Olimex ARM-JTAG
  2375. @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
  2376. @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
  2377. @end itemize
  2378. @end deffn
  2379. @deffn {Config Command} {parport_port} [port_number]
  2380. Display either the address of the I/O port
  2381. (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
  2382. If a parameter is provided, first switch to use that port.
  2383. This is a write-once setting.
  2384. When using PPDEV to access the parallel port, use the number of the parallel port:
  2385. @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
  2386. you may encounter a problem.
  2387. @end deffn
  2388. @deffn Command {parport_toggling_time} [nanoseconds]
  2389. Displays how many nanoseconds the hardware needs to toggle TCK;
  2390. the parport driver uses this value to obey the
  2391. @command{adapter_khz} configuration.
  2392. When the optional @var{nanoseconds} parameter is given,
  2393. that setting is changed before displaying the current value.
  2394. The default setting should work reasonably well on commodity PC hardware.
  2395. However, you may want to calibrate for your specific hardware.
  2396. @quotation Tip
  2397. To measure the toggling time with a logic analyzer or a digital storage
  2398. oscilloscope, follow the procedure below:
  2399. @example
  2400. > parport_toggling_time 1000
  2401. > adapter_khz 500
  2402. @end example
  2403. This sets the maximum JTAG clock speed of the hardware, but
  2404. the actual speed probably deviates from the requested 500 kHz.
  2405. Now, measure the time between the two closest spaced TCK transitions.
  2406. You can use @command{runtest 1000} or something similar to generate a
  2407. large set of samples.
  2408. Update the setting to match your measurement:
  2409. @example
  2410. > parport_toggling_time <measured nanoseconds>
  2411. @end example
  2412. Now the clock speed will be a better match for @command{adapter_khz rate}
  2413. commands given in OpenOCD scripts and event handlers.
  2414. You can do something similar with many digital multimeters, but note
  2415. that you'll probably need to run the clock continuously for several
  2416. seconds before it decides what clock rate to show. Adjust the
  2417. toggling time up or down until the measured clock rate is a good
  2418. match for the adapter_khz rate you specified; be conservative.
  2419. @end quotation
  2420. @end deffn
  2421. @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
  2422. This will configure the parallel driver to write a known
  2423. cable-specific value to the parallel interface on exiting OpenOCD.
  2424. @end deffn
  2425. For example, the interface configuration file for a
  2426. classic ``Wiggler'' cable on LPT2 might look something like this:
  2427. @example
  2428. interface parport
  2429. parport_port 0x278
  2430. parport_cable wiggler
  2431. @end example
  2432. @end deffn
  2433. @deffn {Interface Driver} {presto}
  2434. ASIX PRESTO USB JTAG programmer.
  2435. @deffn {Config Command} {presto_serial} serial_string
  2436. Configures the USB serial number of the Presto device to use.
  2437. @end deffn
  2438. @end deffn
  2439. @deffn {Interface Driver} {rlink}
  2440. Raisonance RLink USB adapter
  2441. @end deffn
  2442. @deffn {Interface Driver} {usbprog}
  2443. usbprog is a freely programmable USB adapter.
  2444. @end deffn
  2445. @deffn {Interface Driver} {vsllink}
  2446. vsllink is part of Versaloon which is a versatile USB programmer.
  2447. @quotation Note
  2448. This defines quite a few driver-specific commands,
  2449. which are not currently documented here.
  2450. @end quotation
  2451. @end deffn
  2452. @deffn {Interface Driver} {hla}
  2453. This is a driver that supports multiple High Level Adapters.
  2454. This type of adapter does not expose some of the lower level api's
  2455. that OpenOCD would normally use to access the target.
  2456. Currently supported adapters include the ST STLINK and TI ICDI.
  2457. @deffn {Config Command} {hla_device_desc} description
  2458. Currently Not Supported.
  2459. @end deffn
  2460. @deffn {Config Command} {hla_serial} serial
  2461. Currently Not Supported.
  2462. @end deffn
  2463. @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
  2464. Specifies the adapter layout to use.
  2465. @end deffn
  2466. @deffn {Config Command} {hla_vid_pid} vid pid
  2467. The vendor ID and product ID of the device.
  2468. @end deffn
  2469. @deffn {Config Command} {stlink_api} api_level
  2470. Manually sets the stlink api used, valid options are 1 or 2. (@b{STLINK Only}).
  2471. @end deffn
  2472. @end deffn
  2473. @deffn {Interface Driver} {opendous}
  2474. opendous-jtag is a freely programmable USB adapter.
  2475. @end deffn
  2476. @deffn {Interface Driver} {ulink}
  2477. This is the Keil ULINK v1 JTAG debugger.
  2478. @end deffn
  2479. @deffn {Interface Driver} {ZY1000}
  2480. This is the Zylin ZY1000 JTAG debugger.
  2481. @end deffn
  2482. @quotation Note
  2483. This defines some driver-specific commands,
  2484. which are not currently documented here.
  2485. @end quotation
  2486. @deffn Command power [@option{on}|@option{off}]
  2487. Turn power switch to target on/off.
  2488. No arguments: print status.
  2489. @end deffn
  2490. @section Transport Configuration
  2491. @cindex Transport
  2492. As noted earlier, depending on the version of OpenOCD you use,
  2493. and the debug adapter you are using,
  2494. several transports may be available to
  2495. communicate with debug targets (or perhaps to program flash memory).
  2496. @deffn Command {transport list}
  2497. displays the names of the transports supported by this
  2498. version of OpenOCD.
  2499. @end deffn
  2500. @deffn Command {transport select} transport_name
  2501. Select which of the supported transports to use in this OpenOCD session.
  2502. The transport must be supported by the debug adapter hardware and by the
  2503. version of OPenOCD you are using (including the adapter's driver).
  2504. No arguments: returns name of session's selected transport.
  2505. @end deffn
  2506. @subsection JTAG Transport
  2507. @cindex JTAG
  2508. JTAG is the original transport supported by OpenOCD, and most
  2509. of the OpenOCD commands support it.
  2510. JTAG transports expose a chain of one or more Test Access Points (TAPs),
  2511. each of which must be explicitly declared.
  2512. JTAG supports both debugging and boundary scan testing.
  2513. Flash programming support is built on top of debug support.
  2514. @subsection SWD Transport
  2515. @cindex SWD
  2516. @cindex Serial Wire Debug
  2517. SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
  2518. Debug Access Point (DAP, which must be explicitly declared.
  2519. (SWD uses fewer signal wires than JTAG.)
  2520. SWD is debug-oriented, and does not support boundary scan testing.
  2521. Flash programming support is built on top of debug support.
  2522. (Some processors support both JTAG and SWD.)
  2523. @deffn Command {swd newdap} ...
  2524. Declares a single DAP which uses SWD transport.
  2525. Parameters are currently the same as "jtag newtap" but this is
  2526. expected to change.
  2527. @end deffn
  2528. @deffn Command {swd wcr trn prescale}
  2529. Updates TRN (turnaraound delay) and prescaling.fields of the
  2530. Wire Control Register (WCR).
  2531. No parameters: displays current settings.
  2532. @end deffn
  2533. @subsection SPI Transport
  2534. @cindex SPI
  2535. @cindex Serial Peripheral Interface
  2536. The Serial Peripheral Interface (SPI) is a general purpose transport
  2537. which uses four wire signaling. Some processors use it as part of a
  2538. solution for flash programming.
  2539. @anchor{jtagspeed}
  2540. @section JTAG Speed
  2541. JTAG clock setup is part of system setup.
  2542. It @emph{does not belong with interface setup} since any interface
  2543. only knows a few of the constraints for the JTAG clock speed.
  2544. Sometimes the JTAG speed is
  2545. changed during the target initialization process: (1) slow at
  2546. reset, (2) program the CPU clocks, (3) run fast.
  2547. Both the "slow" and "fast" clock rates are functions of the
  2548. oscillators used, the chip, the board design, and sometimes
  2549. power management software that may be active.
  2550. The speed used during reset, and the scan chain verification which
  2551. follows reset, can be adjusted using a @code{reset-start}
  2552. target event handler.
  2553. It can then be reconfigured to a faster speed by a
  2554. @code{reset-init} target event handler after it reprograms those
  2555. CPU clocks, or manually (if something else, such as a boot loader,
  2556. sets up those clocks).
  2557. @xref{targetevents,,Target Events}.
  2558. When the initial low JTAG speed is a chip characteristic, perhaps
  2559. because of a required oscillator speed, provide such a handler
  2560. in the target config file.
  2561. When that speed is a function of a board-specific characteristic
  2562. such as which speed oscillator is used, it belongs in the board
  2563. config file instead.
  2564. In both cases it's safest to also set the initial JTAG clock rate
  2565. to that same slow speed, so that OpenOCD never starts up using a
  2566. clock speed that's faster than the scan chain can support.
  2567. @example
  2568. jtag_rclk 3000
  2569. $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
  2570. @end example
  2571. If your system supports adaptive clocking (RTCK), configuring
  2572. JTAG to use that is probably the most robust approach.
  2573. However, it introduces delays to synchronize clocks; so it
  2574. may not be the fastest solution.
  2575. @b{NOTE:} Script writers should consider using @command{jtag_rclk}
  2576. instead of @command{adapter_khz}, but only for (ARM) cores and boards
  2577. which support adaptive clocking.
  2578. @deffn {Command} adapter_khz max_speed_kHz
  2579. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
  2580. JTAG interfaces usually support a limited number of
  2581. speeds. The speed actually used won't be faster
  2582. than the speed specified.
  2583. Chip data sheets generally include a top JTAG clock rate.
  2584. The actual rate is often a function of a CPU core clock,
  2585. and is normally less than that peak rate.
  2586. For example, most ARM cores accept at most one sixth of the CPU clock.
  2587. Speed 0 (khz) selects RTCK method.
  2588. @xref{faqrtck,,FAQ RTCK}.
  2589. If your system uses RTCK, you won't need to change the
  2590. JTAG clocking after setup.
  2591. Not all interfaces, boards, or targets support ``rtck''.
  2592. If the interface device can not
  2593. support it, an error is returned when you try to use RTCK.
  2594. @end deffn
  2595. @defun jtag_rclk fallback_speed_kHz
  2596. @cindex adaptive clocking
  2597. @cindex RTCK
  2598. This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
  2599. If that fails (maybe the interface, board, or target doesn't
  2600. support it), falls back to the specified frequency.
  2601. @example
  2602. # Fall back to 3mhz if RTCK is not supported
  2603. jtag_rclk 3000
  2604. @end example
  2605. @end defun
  2606. @node Reset Configuration
  2607. @chapter Reset Configuration
  2608. @cindex Reset Configuration
  2609. Every system configuration may require a different reset
  2610. configuration. This can also be quite confusing.
  2611. Resets also interact with @var{reset-init} event handlers,
  2612. which do things like setting up clocks and DRAM, and
  2613. JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
  2614. They can also interact with JTAG routers.
  2615. Please see the various board files for examples.
  2616. @quotation Note
  2617. To maintainers and integrators:
  2618. Reset configuration touches several things at once.
  2619. Normally the board configuration file
  2620. should define it and assume that the JTAG adapter supports
  2621. everything that's wired up to the board's JTAG connector.
  2622. However, the target configuration file could also make note
  2623. of something the silicon vendor has done inside the chip,
  2624. which will be true for most (or all) boards using that chip.
  2625. And when the JTAG adapter doesn't support everything, the
  2626. user configuration file will need to override parts of
  2627. the reset configuration provided by other files.
  2628. @end quotation
  2629. @section Types of Reset
  2630. There are many kinds of reset possible through JTAG, but
  2631. they may not all work with a given board and adapter.
  2632. That's part of why reset configuration can be error prone.
  2633. @itemize @bullet
  2634. @item
  2635. @emph{System Reset} ... the @emph{SRST} hardware signal
  2636. resets all chips connected to the JTAG adapter, such as processors,
  2637. power management chips, and I/O controllers. Normally resets triggered
  2638. with this signal behave exactly like pressing a RESET button.
  2639. @item
  2640. @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
  2641. just the TAP controllers connected to the JTAG adapter.
  2642. Such resets should not be visible to the rest of the system; resetting a
  2643. device's TAP controller just puts that controller into a known state.
  2644. @item
  2645. @emph{Emulation Reset} ... many devices can be reset through JTAG
  2646. commands. These resets are often distinguishable from system
  2647. resets, either explicitly (a "reset reason" register says so)
  2648. or implicitly (not all parts of the chip get reset).
  2649. @item
  2650. @emph{Other Resets} ... system-on-chip devices often support
  2651. several other types of reset.
  2652. You may need to arrange that a watchdog timer stops
  2653. while debugging, preventing a watchdog reset.
  2654. There may be individual module resets.
  2655. @end itemize
  2656. In the best case, OpenOCD can hold SRST, then reset
  2657. the TAPs via TRST and send commands through JTAG to halt the
  2658. CPU at the reset vector before the 1st instruction is executed.
  2659. Then when it finally releases the SRST signal, the system is
  2660. halted under debugger control before any code has executed.
  2661. This is the behavior required to support the @command{reset halt}
  2662. and @command{reset init} commands; after @command{reset init} a
  2663. board-specific script might do things like setting up DRAM.
  2664. (@xref{resetcommand,,Reset Command}.)
  2665. @anchor{srstandtrstissues}
  2666. @section SRST and TRST Issues
  2667. Because SRST and TRST are hardware signals, they can have a
  2668. variety of system-specific constraints. Some of the most
  2669. common issues are:
  2670. @itemize @bullet
  2671. @item @emph{Signal not available} ... Some boards don't wire
  2672. SRST or TRST to the JTAG connector. Some JTAG adapters don't
  2673. support such signals even if they are wired up.
  2674. Use the @command{reset_config} @var{signals} options to say
  2675. when either of those signals is not connected.
  2676. When SRST is not available, your code might not be able to rely
  2677. on controllers having been fully reset during code startup.
  2678. Missing TRST is not a problem, since JTAG-level resets can
  2679. be triggered using with TMS signaling.
  2680. @item @emph{Signals shorted} ... Sometimes a chip, board, or
  2681. adapter will connect SRST to TRST, instead of keeping them separate.
  2682. Use the @command{reset_config} @var{combination} options to say
  2683. when those signals aren't properly independent.
  2684. @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
  2685. delay circuit, reset supervisor, or on-chip features can extend
  2686. the effect of a JTAG adapter's reset for some time after the adapter
  2687. stops issuing the reset. For example, there may be chip or board
  2688. requirements that all reset pulses last for at least a
  2689. certain amount of time; and reset buttons commonly have
  2690. hardware debouncing.
  2691. Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
  2692. commands to say when extra delays are needed.
  2693. @item @emph{Drive type} ... Reset lines often have a pullup
  2694. resistor, letting the JTAG interface treat them as open-drain
  2695. signals. But that's not a requirement, so the adapter may need
  2696. to use push/pull output drivers.
  2697. Also, with weak pullups it may be advisable to drive
  2698. signals to both levels (push/pull) to minimize rise times.
  2699. Use the @command{reset_config} @var{trst_type} and
  2700. @var{srst_type} parameters to say how to drive reset signals.
  2701. @item @emph{Special initialization} ... Targets sometimes need
  2702. special JTAG initialization sequences to handle chip-specific
  2703. issues (not limited to errata).
  2704. For example, certain JTAG commands might need to be issued while
  2705. the system as a whole is in a reset state (SRST active)
  2706. but the JTAG scan chain is usable (TRST inactive).
  2707. Many systems treat combined assertion of SRST and TRST as a
  2708. trigger for a harder reset than SRST alone.
  2709. Such custom reset handling is discussed later in this chapter.
  2710. @end itemize
  2711. There can also be other issues.
  2712. Some devices don't fully conform to the JTAG specifications.
  2713. Trivial system-specific differences are common, such as
  2714. SRST and TRST using slightly different names.
  2715. There are also vendors who distribute key JTAG documentation for
  2716. their chips only to developers who have signed a Non-Disclosure
  2717. Agreement (NDA).
  2718. Sometimes there are chip-specific extensions like a requirement to use
  2719. the normally-optional TRST signal (precluding use of JTAG adapters which
  2720. don't pass TRST through), or needing extra steps to complete a TAP reset.
  2721. In short, SRST and especially TRST handling may be very finicky,
  2722. needing to cope with both architecture and board specific constraints.
  2723. @section Commands for Handling Resets
  2724. @deffn {Command} adapter_nsrst_assert_width milliseconds
  2725. Minimum amount of time (in milliseconds) OpenOCD should wait
  2726. after asserting nSRST (active-low system reset) before
  2727. allowing it to be deasserted.
  2728. @end deffn
  2729. @deffn {Command} adapter_nsrst_delay milliseconds
  2730. How long (in milliseconds) OpenOCD should wait after deasserting
  2731. nSRST (active-low system reset) before starting new JTAG operations.
  2732. When a board has a reset button connected to SRST line it will
  2733. probably have hardware debouncing, implying you should use this.
  2734. @end deffn
  2735. @deffn {Command} jtag_ntrst_assert_width milliseconds
  2736. Minimum amount of time (in milliseconds) OpenOCD should wait
  2737. after asserting nTRST (active-low JTAG TAP reset) before
  2738. allowing it to be deasserted.
  2739. @end deffn
  2740. @deffn {Command} jtag_ntrst_delay milliseconds
  2741. How long (in milliseconds) OpenOCD should wait after deasserting
  2742. nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
  2743. @end deffn
  2744. @deffn {Command} reset_config mode_flag ...
  2745. This command displays or modifies the reset configuration
  2746. of your combination of JTAG board and target in target
  2747. configuration scripts.
  2748. Information earlier in this section describes the kind of problems
  2749. the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
  2750. As a rule this command belongs only in board config files,
  2751. describing issues like @emph{board doesn't connect TRST};
  2752. or in user config files, addressing limitations derived
  2753. from a particular combination of interface and board.
  2754. (An unlikely example would be using a TRST-only adapter
  2755. with a board that only wires up SRST.)
  2756. The @var{mode_flag} options can be specified in any order, but only one
  2757. of each type -- @var{signals}, @var{combination}, @var{gates},
  2758. @var{trst_type}, @var{srst_type} and @var{connect_type}
  2759. -- may be specified at a time.
  2760. If you don't provide a new value for a given type, its previous
  2761. value (perhaps the default) is unchanged.
  2762. For example, this means that you don't need to say anything at all about
  2763. TRST just to declare that if the JTAG adapter should want to drive SRST,
  2764. it must explicitly be driven high (@option{srst_push_pull}).
  2765. @itemize
  2766. @item
  2767. @var{signals} can specify which of the reset signals are connected.
  2768. For example, If the JTAG interface provides SRST, but the board doesn't
  2769. connect that signal properly, then OpenOCD can't use it.
  2770. Possible values are @option{none} (the default), @option{trst_only},
  2771. @option{srst_only} and @option{trst_and_srst}.
  2772. @quotation Tip
  2773. If your board provides SRST and/or TRST through the JTAG connector,
  2774. you must declare that so those signals can be used.
  2775. @end quotation
  2776. @item
  2777. The @var{combination} is an optional value specifying broken reset
  2778. signal implementations.
  2779. The default behaviour if no option given is @option{separate},
  2780. indicating everything behaves normally.
  2781. @option{srst_pulls_trst} states that the
  2782. test logic is reset together with the reset of the system (e.g. NXP
  2783. LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
  2784. the system is reset together with the test logic (only hypothetical, I
  2785. haven't seen hardware with such a bug, and can be worked around).
  2786. @option{combined} implies both @option{srst_pulls_trst} and
  2787. @option{trst_pulls_srst}.
  2788. @item
  2789. The @var{gates} tokens control flags that describe some cases where
  2790. JTAG may be unvailable during reset.
  2791. @option{srst_gates_jtag} (default)
  2792. indicates that asserting SRST gates the
  2793. JTAG clock. This means that no communication can happen on JTAG
  2794. while SRST is asserted.
  2795. Its converse is @option{srst_nogate}, indicating that JTAG commands
  2796. can safely be issued while SRST is active.
  2797. @item
  2798. The @var{connect_type} tokens control flags that describe some cases where
  2799. SRST is asserted while connecting to the target. @option{srst_nogate}
  2800. is required to use this option.
  2801. @option{connect_deassert_srst} (default)
  2802. indicates that SRST will not be asserted while connecting to the target.
  2803. Its converse is @option{connect_assert_srst}, indicating that SRST will
  2804. be asserted before any target connection.
  2805. Only some targets support this feature, STM32 and STR9 are examples.
  2806. This feature is useful if you are unable to connect to your target due
  2807. to incorrect options byte config or illegal program execution.
  2808. @end itemize
  2809. The optional @var{trst_type} and @var{srst_type} parameters allow the
  2810. driver mode of each reset line to be specified. These values only affect
  2811. JTAG interfaces with support for different driver modes, like the Amontec
  2812. JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
  2813. relevant signal (TRST or SRST) is not connected.
  2814. @itemize
  2815. @item
  2816. Possible @var{trst_type} driver modes for the test reset signal (TRST)
  2817. are the default @option{trst_push_pull}, and @option{trst_open_drain}.
  2818. Most boards connect this signal to a pulldown, so the JTAG TAPs
  2819. never leave reset unless they are hooked up to a JTAG adapter.
  2820. @item
  2821. Possible @var{srst_type} driver modes for the system reset signal (SRST)
  2822. are the default @option{srst_open_drain}, and @option{srst_push_pull}.
  2823. Most boards connect this signal to a pullup, and allow the
  2824. signal to be pulled low by various events including system
  2825. powerup and pressing a reset button.
  2826. @end itemize
  2827. @end deffn
  2828. @section Custom Reset Handling
  2829. @cindex events
  2830. OpenOCD has several ways to help support the various reset
  2831. mechanisms provided by chip and board vendors.
  2832. The commands shown in the previous section give standard parameters.
  2833. There are also @emph{event handlers} associated with TAPs or Targets.
  2834. Those handlers are Tcl procedures you can provide, which are invoked
  2835. at particular points in the reset sequence.
  2836. @emph{When SRST is not an option} you must set
  2837. up a @code{reset-assert} event handler for your target.
  2838. For example, some JTAG adapters don't include the SRST signal;
  2839. and some boards have multiple targets, and you won't always
  2840. want to reset everything at once.
  2841. After configuring those mechanisms, you might still
  2842. find your board doesn't start up or reset correctly.
  2843. For example, maybe it needs a slightly different sequence
  2844. of SRST and/or TRST manipulations, because of quirks that
  2845. the @command{reset_config} mechanism doesn't address;
  2846. or asserting both might trigger a stronger reset, which
  2847. needs special attention.
  2848. Experiment with lower level operations, such as @command{jtag_reset}
  2849. and the @command{jtag arp_*} operations shown here,
  2850. to find a sequence of operations that works.
  2851. @xref{JTAG Commands}.
  2852. When you find a working sequence, it can be used to override
  2853. @command{jtag_init}, which fires during OpenOCD startup
  2854. (@pxref{configurationstage,,Configuration Stage});
  2855. or @command{init_reset}, which fires during reset processing.
  2856. You might also want to provide some project-specific reset
  2857. schemes. For example, on a multi-target board the standard
  2858. @command{reset} command would reset all targets, but you
  2859. may need the ability to reset only one target at time and
  2860. thus want to avoid using the board-wide SRST signal.
  2861. @deffn {Overridable Procedure} init_reset mode
  2862. This is invoked near the beginning of the @command{reset} command,
  2863. usually to provide as much of a cold (power-up) reset as practical.
  2864. By default it is also invoked from @command{jtag_init} if
  2865. the scan chain does not respond to pure JTAG operations.
  2866. The @var{mode} parameter is the parameter given to the
  2867. low level reset command (@option{halt},
  2868. @option{init}, or @option{run}), @option{setup},
  2869. or potentially some other value.
  2870. The default implementation just invokes @command{jtag arp_init-reset}.
  2871. Replacements will normally build on low level JTAG
  2872. operations such as @command{jtag_reset}.
  2873. Operations here must not address individual TAPs
  2874. (or their associated targets)
  2875. until the JTAG scan chain has first been verified to work.
  2876. Implementations must have verified the JTAG scan chain before
  2877. they return.
  2878. This is done by calling @command{jtag arp_init}
  2879. (or @command{jtag arp_init-reset}).
  2880. @end deffn
  2881. @deffn Command {jtag arp_init}
  2882. This validates the scan chain using just the four
  2883. standard JTAG signals (TMS, TCK, TDI, TDO).
  2884. It starts by issuing a JTAG-only reset.
  2885. Then it performs checks to verify that the scan chain configuration
  2886. matches the TAPs it can observe.
  2887. Those checks include checking IDCODE values for each active TAP,
  2888. and verifying the length of their instruction registers using
  2889. TAP @code{-ircapture} and @code{-irmask} values.
  2890. If these tests all pass, TAP @code{setup} events are
  2891. issued to all TAPs with handlers for that event.
  2892. @end deffn
  2893. @deffn Command {jtag arp_init-reset}
  2894. This uses TRST and SRST to try resetting
  2895. everything on the JTAG scan chain
  2896. (and anything else connected to SRST).
  2897. It then invokes the logic of @command{jtag arp_init}.
  2898. @end deffn
  2899. @node TAP Declaration
  2900. @chapter TAP Declaration
  2901. @cindex TAP declaration
  2902. @cindex TAP configuration
  2903. @emph{Test Access Ports} (TAPs) are the core of JTAG.
  2904. TAPs serve many roles, including:
  2905. @itemize @bullet
  2906. @item @b{Debug Target} A CPU TAP can be used as a GDB debug target
  2907. @item @b{Flash Programing} Some chips program the flash directly via JTAG.
  2908. Others do it indirectly, making a CPU do it.
  2909. @item @b{Program Download} Using the same CPU support GDB uses,
  2910. you can initialize a DRAM controller, download code to DRAM, and then
  2911. start running that code.
  2912. @item @b{Boundary Scan} Most chips support boundary scan, which
  2913. helps test for board assembly problems like solder bridges
  2914. and missing connections
  2915. @end itemize
  2916. OpenOCD must know about the active TAPs on your board(s).
  2917. Setting up the TAPs is the core task of your configuration files.
  2918. Once those TAPs are set up, you can pass their names to code
  2919. which sets up CPUs and exports them as GDB targets,
  2920. probes flash memory, performs low-level JTAG operations, and more.
  2921. @section Scan Chains
  2922. @cindex scan chain
  2923. TAPs are part of a hardware @dfn{scan chain},
  2924. which is daisy chain of TAPs.
  2925. They also need to be added to
  2926. OpenOCD's software mirror of that hardware list,
  2927. giving each member a name and associating other data with it.
  2928. Simple scan chains, with a single TAP, are common in
  2929. systems with a single microcontroller or microprocessor.
  2930. More complex chips may have several TAPs internally.
  2931. Very complex scan chains might have a dozen or more TAPs:
  2932. several in one chip, more in the next, and connecting
  2933. to other boards with their own chips and TAPs.
  2934. You can display the list with the @command{scan_chain} command.
  2935. (Don't confuse this with the list displayed by the @command{targets}
  2936. command, presented in the next chapter.
  2937. That only displays TAPs for CPUs which are configured as
  2938. debugging targets.)
  2939. Here's what the scan chain might look like for a chip more than one TAP:
  2940. @verbatim
  2941. TapName Enabled IdCode Expected IrLen IrCap IrMask
  2942. -- ------------------ ------- ---------- ---------- ----- ----- ------
  2943. 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
  2944. 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
  2945. 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
  2946. @end verbatim
  2947. OpenOCD can detect some of that information, but not all
  2948. of it. @xref{autoprobing,,Autoprobing}.
  2949. Unfortunately those TAPs can't always be autoconfigured,
  2950. because not all devices provide good support for that.
  2951. JTAG doesn't require supporting IDCODE instructions, and
  2952. chips with JTAG routers may not link TAPs into the chain
  2953. until they are told to do so.
  2954. The configuration mechanism currently supported by OpenOCD
  2955. requires explicit configuration of all TAP devices using
  2956. @command{jtag newtap} commands, as detailed later in this chapter.
  2957. A command like this would declare one tap and name it @code{chip1.cpu}:
  2958. @example
  2959. jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
  2960. @end example
  2961. Each target configuration file lists the TAPs provided
  2962. by a given chip.
  2963. Board configuration files combine all the targets on a board,
  2964. and so forth.
  2965. Note that @emph{the order in which TAPs are declared is very important.}
  2966. It must match the order in the JTAG scan chain, both inside
  2967. a single chip and between them.
  2968. @xref{faqtaporder,,FAQ TAP Order}.
  2969. For example, the ST Microsystems STR912 chip has
  2970. three separate TAPs@footnote{See the ST
  2971. document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
  2972. 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
  2973. @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
  2974. To configure those taps, @file{target/str912.cfg}
  2975. includes commands something like this:
  2976. @example
  2977. jtag newtap str912 flash ... params ...
  2978. jtag newtap str912 cpu ... params ...
  2979. jtag newtap str912 bs ... params ...
  2980. @end example
  2981. Actual config files use a variable instead of literals like
  2982. @option{str912}, to support more than one chip of each type.
  2983. @xref{Config File Guidelines}.
  2984. @deffn Command {jtag names}
  2985. Returns the names of all current TAPs in the scan chain.
  2986. Use @command{jtag cget} or @command{jtag tapisenabled}
  2987. to examine attributes and state of each TAP.
  2988. @example
  2989. foreach t [jtag names] @{
  2990. puts [format "TAP: %s\n" $t]
  2991. @}
  2992. @end example
  2993. @end deffn
  2994. @deffn Command {scan_chain}
  2995. Displays the TAPs in the scan chain configuration,
  2996. and their status.
  2997. The set of TAPs listed by this command is fixed by
  2998. exiting the OpenOCD configuration stage,
  2999. but systems with a JTAG router can
  3000. enable or disable TAPs dynamically.
  3001. @end deffn
  3002. @c FIXME! "jtag cget" should be able to return all TAP
  3003. @c attributes, like "$target_name cget" does for targets.
  3004. @c Probably want "jtag eventlist", and a "tap-reset" event
  3005. @c (on entry to RESET state).
  3006. @section TAP Names
  3007. @cindex dotted name
  3008. When TAP objects are declared with @command{jtag newtap},
  3009. a @dfn{dotted.name} is created for the TAP, combining the
  3010. name of a module (usually a chip) and a label for the TAP.
  3011. For example: @code{xilinx.tap}, @code{str912.flash},
  3012. @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
  3013. Many other commands use that dotted.name to manipulate or
  3014. refer to the TAP. For example, CPU configuration uses the
  3015. name, as does declaration of NAND or NOR flash banks.
  3016. The components of a dotted name should follow ``C'' symbol
  3017. name rules: start with an alphabetic character, then numbers
  3018. and underscores are OK; while others (including dots!) are not.
  3019. @quotation Tip
  3020. In older code, JTAG TAPs were numbered from 0..N.
  3021. This feature is still present.
  3022. However its use is highly discouraged, and
  3023. should not be relied on; it will be removed by mid-2010.
  3024. Update all of your scripts to use TAP names rather than numbers,
  3025. by paying attention to the runtime warnings they trigger.
  3026. Using TAP numbers in target configuration scripts prevents
  3027. reusing those scripts on boards with multiple targets.
  3028. @end quotation
  3029. @section TAP Declaration Commands
  3030. @c shouldn't this be(come) a {Config Command}?
  3031. @deffn Command {jtag newtap} chipname tapname configparams...
  3032. Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
  3033. and configured according to the various @var{configparams}.
  3034. The @var{chipname} is a symbolic name for the chip.
  3035. Conventionally target config files use @code{$_CHIPNAME},
  3036. defaulting to the model name given by the chip vendor but
  3037. overridable.
  3038. @cindex TAP naming convention
  3039. The @var{tapname} reflects the role of that TAP,
  3040. and should follow this convention:
  3041. @itemize @bullet
  3042. @item @code{bs} -- For boundary scan if this is a seperate TAP;
  3043. @item @code{cpu} -- The main CPU of the chip, alternatively
  3044. @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
  3045. @code{arm1} and @code{arm2} on chips two ARMs, and so forth;
  3046. @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
  3047. @item @code{flash} -- If the chip has a flash TAP, like the str912;
  3048. @item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
  3049. on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
  3050. @item @code{tap} -- Should be used only FPGA or CPLD like devices
  3051. with a single TAP;
  3052. @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
  3053. @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
  3054. For example, the Freescale IMX31 has a SDMA (Smart DMA) with
  3055. a JTAG TAP; that TAP should be named @code{sdma}.
  3056. @end itemize
  3057. Every TAP requires at least the following @var{configparams}:
  3058. @itemize @bullet
  3059. @item @code{-irlen} @var{NUMBER}
  3060. @*The length in bits of the
  3061. instruction register, such as 4 or 5 bits.
  3062. @end itemize
  3063. A TAP may also provide optional @var{configparams}:
  3064. @itemize @bullet
  3065. @item @code{-disable} (or @code{-enable})
  3066. @*Use the @code{-disable} parameter to flag a TAP which is not
  3067. linked in to the scan chain after a reset using either TRST
  3068. or the JTAG state machine's @sc{reset} state.
  3069. You may use @code{-enable} to highlight the default state
  3070. (the TAP is linked in).
  3071. @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
  3072. @item @code{-expected-id} @var{number}
  3073. @*A non-zero @var{number} represents a 32-bit IDCODE
  3074. which you expect to find when the scan chain is examined.
  3075. These codes are not required by all JTAG devices.
  3076. @emph{Repeat the option} as many times as required if more than one
  3077. ID code could appear (for example, multiple versions).
  3078. Specify @var{number} as zero to suppress warnings about IDCODE
  3079. values that were found but not included in the list.
  3080. Provide this value if at all possible, since it lets OpenOCD
  3081. tell when the scan chain it sees isn't right. These values
  3082. are provided in vendors' chip documentation, usually a technical
  3083. reference manual. Sometimes you may need to probe the JTAG
  3084. hardware to find these values.
  3085. @xref{autoprobing,,Autoprobing}.
  3086. @item @code{-ignore-version}
  3087. @*Specify this to ignore the JTAG version field in the @code{-expected-id}
  3088. option. When vendors put out multiple versions of a chip, or use the same
  3089. JTAG-level ID for several largely-compatible chips, it may be more practical
  3090. to ignore the version field than to update config files to handle all of
  3091. the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
  3092. @item @code{-ircapture} @var{NUMBER}
  3093. @*The bit pattern loaded by the TAP into the JTAG shift register
  3094. on entry to the @sc{ircapture} state, such as 0x01.
  3095. JTAG requires the two LSBs of this value to be 01.
  3096. By default, @code{-ircapture} and @code{-irmask} are set
  3097. up to verify that two-bit value. You may provide
  3098. additional bits, if you know them, or indicate that
  3099. a TAP doesn't conform to the JTAG specification.
  3100. @item @code{-irmask} @var{NUMBER}
  3101. @*A mask used with @code{-ircapture}
  3102. to verify that instruction scans work correctly.
  3103. Such scans are not used by OpenOCD except to verify that
  3104. there seems to be no problems with JTAG scan chain operations.
  3105. @end itemize
  3106. @end deffn
  3107. @section Other TAP commands
  3108. @deffn Command {jtag cget} dotted.name @option{-event} name
  3109. @deffnx Command {jtag configure} dotted.name @option{-event} name string
  3110. At this writing this TAP attribute
  3111. mechanism is used only for event handling.
  3112. (It is not a direct analogue of the @code{cget}/@code{configure}
  3113. mechanism for debugger targets.)
  3114. See the next section for information about the available events.
  3115. The @code{configure} subcommand assigns an event handler,
  3116. a TCL string which is evaluated when the event is triggered.
  3117. The @code{cget} subcommand returns that handler.
  3118. @end deffn
  3119. @section TAP Events
  3120. @cindex events
  3121. @cindex TAP events
  3122. OpenOCD includes two event mechanisms.
  3123. The one presented here applies to all JTAG TAPs.
  3124. The other applies to debugger targets,
  3125. which are associated with certain TAPs.
  3126. The TAP events currently defined are:
  3127. @itemize @bullet
  3128. @item @b{post-reset}
  3129. @* The TAP has just completed a JTAG reset.
  3130. The tap may still be in the JTAG @sc{reset} state.
  3131. Handlers for these events might perform initialization sequences
  3132. such as issuing TCK cycles, TMS sequences to ensure
  3133. exit from the ARM SWD mode, and more.
  3134. Because the scan chain has not yet been verified, handlers for these events
  3135. @emph{should not issue commands which scan the JTAG IR or DR registers}
  3136. of any particular target.
  3137. @b{NOTE:} As this is written (September 2009), nothing prevents such access.
  3138. @item @b{setup}
  3139. @* The scan chain has been reset and verified.
  3140. This handler may enable TAPs as needed.
  3141. @item @b{tap-disable}
  3142. @* The TAP needs to be disabled. This handler should
  3143. implement @command{jtag tapdisable}
  3144. by issuing the relevant JTAG commands.
  3145. @item @b{tap-enable}
  3146. @* The TAP needs to be enabled. This handler should
  3147. implement @command{jtag tapenable}
  3148. by issuing the relevant JTAG commands.
  3149. @end itemize
  3150. If you need some action after each JTAG reset, which isn't actually
  3151. specific to any TAP (since you can't yet trust the scan chain's
  3152. contents to be accurate), you might:
  3153. @example
  3154. jtag configure CHIP.jrc -event post-reset @{
  3155. echo "JTAG Reset done"
  3156. ... non-scan jtag operations to be done after reset
  3157. @}
  3158. @end example
  3159. @anchor{enablinganddisablingtaps}
  3160. @section Enabling and Disabling TAPs
  3161. @cindex JTAG Route Controller
  3162. @cindex jrc
  3163. In some systems, a @dfn{JTAG Route Controller} (JRC)
  3164. is used to enable and/or disable specific JTAG TAPs.
  3165. Many ARM based chips from Texas Instruments include
  3166. an ``ICEpick'' module, which is a JRC.
  3167. Such chips include DaVinci and OMAP3 processors.
  3168. A given TAP may not be visible until the JRC has been
  3169. told to link it into the scan chain; and if the JRC
  3170. has been told to unlink that TAP, it will no longer
  3171. be visible.
  3172. Such routers address problems that JTAG ``bypass mode''
  3173. ignores, such as:
  3174. @itemize
  3175. @item The scan chain can only go as fast as its slowest TAP.
  3176. @item Having many TAPs slows instruction scans, since all
  3177. TAPs receive new instructions.
  3178. @item TAPs in the scan chain must be powered up, which wastes
  3179. power and prevents debugging some power management mechanisms.
  3180. @end itemize
  3181. The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
  3182. as implied by the existence of JTAG routers.
  3183. However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
  3184. does include a kind of JTAG router functionality.
  3185. @c (a) currently the event handlers don't seem to be able to
  3186. @c fail in a way that could lead to no-change-of-state.
  3187. In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
  3188. shown below, and is implemented using TAP event handlers.
  3189. So for example, when defining a TAP for a CPU connected to
  3190. a JTAG router, your @file{target.cfg} file
  3191. should define TAP event handlers using
  3192. code that looks something like this:
  3193. @example
  3194. jtag configure CHIP.cpu -event tap-enable @{
  3195. ... jtag operations using CHIP.jrc
  3196. @}
  3197. jtag configure CHIP.cpu -event tap-disable @{
  3198. ... jtag operations using CHIP.jrc
  3199. @}
  3200. @end example
  3201. Then you might want that CPU's TAP enabled almost all the time:
  3202. @example
  3203. jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
  3204. @end example
  3205. Note how that particular setup event handler declaration
  3206. uses quotes to evaluate @code{$CHIP} when the event is configured.
  3207. Using brackets @{ @} would cause it to be evaluated later,
  3208. at runtime, when it might have a different value.
  3209. @deffn Command {jtag tapdisable} dotted.name
  3210. If necessary, disables the tap
  3211. by sending it a @option{tap-disable} event.
  3212. Returns the string "1" if the tap
  3213. specified by @var{dotted.name} is enabled,
  3214. and "0" if it is disabled.
  3215. @end deffn
  3216. @deffn Command {jtag tapenable} dotted.name
  3217. If necessary, enables the tap
  3218. by sending it a @option{tap-enable} event.
  3219. Returns the string "1" if the tap
  3220. specified by @var{dotted.name} is enabled,
  3221. and "0" if it is disabled.
  3222. @end deffn
  3223. @deffn Command {jtag tapisenabled} dotted.name
  3224. Returns the string "1" if the tap
  3225. specified by @var{dotted.name} is enabled,
  3226. and "0" if it is disabled.
  3227. @quotation Note
  3228. Humans will find the @command{scan_chain} command more helpful
  3229. for querying the state of the JTAG taps.
  3230. @end quotation
  3231. @end deffn
  3232. @anchor{autoprobing}
  3233. @section Autoprobing
  3234. @cindex autoprobe
  3235. @cindex JTAG autoprobe
  3236. TAP configuration is the first thing that needs to be done
  3237. after interface and reset configuration. Sometimes it's
  3238. hard finding out what TAPs exist, or how they are identified.
  3239. Vendor documentation is not always easy to find and use.
  3240. To help you get past such problems, OpenOCD has a limited
  3241. @emph{autoprobing} ability to look at the scan chain, doing
  3242. a @dfn{blind interrogation} and then reporting the TAPs it finds.
  3243. To use this mechanism, start the OpenOCD server with only data
  3244. that configures your JTAG interface, and arranges to come up
  3245. with a slow clock (many devices don't support fast JTAG clocks
  3246. right when they come out of reset).
  3247. For example, your @file{openocd.cfg} file might have:
  3248. @example
  3249. source [find interface/olimex-arm-usb-tiny-h.cfg]
  3250. reset_config trst_and_srst
  3251. jtag_rclk 8
  3252. @end example
  3253. When you start the server without any TAPs configured, it will
  3254. attempt to autoconfigure the TAPs. There are two parts to this:
  3255. @enumerate
  3256. @item @emph{TAP discovery} ...
  3257. After a JTAG reset (sometimes a system reset may be needed too),
  3258. each TAP's data registers will hold the contents of either the
  3259. IDCODE or BYPASS register.
  3260. If JTAG communication is working, OpenOCD will see each TAP,
  3261. and report what @option{-expected-id} to use with it.
  3262. @item @emph{IR Length discovery} ...
  3263. Unfortunately JTAG does not provide a reliable way to find out
  3264. the value of the @option{-irlen} parameter to use with a TAP
  3265. that is discovered.
  3266. If OpenOCD can discover the length of a TAP's instruction
  3267. register, it will report it.
  3268. Otherwise you may need to consult vendor documentation, such
  3269. as chip data sheets or BSDL files.
  3270. @end enumerate
  3271. In many cases your board will have a simple scan chain with just
  3272. a single device. Here's what OpenOCD reported with one board
  3273. that's a bit more complex:
  3274. @example
  3275. clock speed 8 kHz
  3276. There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
  3277. AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
  3278. AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
  3279. AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
  3280. AUTO auto0.tap - use "... -irlen 4"
  3281. AUTO auto1.tap - use "... -irlen 4"
  3282. AUTO auto2.tap - use "... -irlen 6"
  3283. no gdb ports allocated as no target has been specified
  3284. @end example
  3285. Given that information, you should be able to either find some existing
  3286. config files to use, or create your own. If you create your own, you
  3287. would configure from the bottom up: first a @file{target.cfg} file
  3288. with these TAPs, any targets associated with them, and any on-chip
  3289. resources; then a @file{board.cfg} with off-chip resources, clocking,
  3290. and so forth.
  3291. @node CPU Configuration
  3292. @chapter CPU Configuration
  3293. @cindex GDB target
  3294. This chapter discusses how to set up GDB debug targets for CPUs.
  3295. You can also access these targets without GDB
  3296. (@pxref{Architecture and Core Commands},
  3297. and @ref{targetstatehandling,,Target State handling}) and
  3298. through various kinds of NAND and NOR flash commands.
  3299. If you have multiple CPUs you can have multiple such targets.
  3300. We'll start by looking at how to examine the targets you have,
  3301. then look at how to add one more target and how to configure it.
  3302. @section Target List
  3303. @cindex target, current
  3304. @cindex target, list
  3305. All targets that have been set up are part of a list,
  3306. where each member has a name.
  3307. That name should normally be the same as the TAP name.
  3308. You can display the list with the @command{targets}
  3309. (plural!) command.
  3310. This display often has only one CPU; here's what it might
  3311. look like with more than one:
  3312. @verbatim
  3313. TargetName Type Endian TapName State
  3314. -- ------------------ ---------- ------ ------------------ ------------
  3315. 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
  3316. 1 MyTarget cortex_m3 little mychip.foo tap-disabled
  3317. @end verbatim
  3318. One member of that list is the @dfn{current target}, which
  3319. is implicitly referenced by many commands.
  3320. It's the one marked with a @code{*} near the target name.
  3321. In particular, memory addresses often refer to the address
  3322. space seen by that current target.
  3323. Commands like @command{mdw} (memory display words)
  3324. and @command{flash erase_address} (erase NOR flash blocks)
  3325. are examples; and there are many more.
  3326. Several commands let you examine the list of targets:
  3327. @deffn Command {target count}
  3328. @emph{Note: target numbers are deprecated; don't use them.
  3329. They will be removed shortly after August 2010, including this command.
  3330. Iterate target using @command{target names}, not by counting.}
  3331. Returns the number of targets, @math{N}.
  3332. The highest numbered target is @math{N - 1}.
  3333. @example
  3334. set c [target count]
  3335. for @{ set x 0 @} @{ $x < $c @} @{ incr x @} @{
  3336. # Assuming you have created this function
  3337. print_target_details $x
  3338. @}
  3339. @end example
  3340. @end deffn
  3341. @deffn Command {target current}
  3342. Returns the name of the current target.
  3343. @end deffn
  3344. @deffn Command {target names}
  3345. Lists the names of all current targets in the list.
  3346. @example
  3347. foreach t [target names] @{
  3348. puts [format "Target: %s\n" $t]
  3349. @}
  3350. @end example
  3351. @end deffn
  3352. @deffn Command {target number} number
  3353. @emph{Note: target numbers are deprecated; don't use them.
  3354. They will be removed shortly after August 2010, including this command.}
  3355. The list of targets is numbered starting at zero.
  3356. This command returns the name of the target at index @var{number}.
  3357. @example
  3358. set thename [target number $x]
  3359. puts [format "Target %d is: %s\n" $x $thename]
  3360. @end example
  3361. @end deffn
  3362. @c yep, "target list" would have been better.
  3363. @c plus maybe "target setdefault".
  3364. @deffn Command targets [name]
  3365. @emph{Note: the name of this command is plural. Other target
  3366. command names are singular.}
  3367. With no parameter, this command displays a table of all known
  3368. targets in a user friendly form.
  3369. With a parameter, this command sets the current target to
  3370. the given target with the given @var{name}; this is
  3371. only relevant on boards which have more than one target.
  3372. @end deffn
  3373. @section Target CPU Types and Variants
  3374. @cindex target type
  3375. @cindex CPU type
  3376. @cindex CPU variant
  3377. Each target has a @dfn{CPU type}, as shown in the output of
  3378. the @command{targets} command. You need to specify that type
  3379. when calling @command{target create}.
  3380. The CPU type indicates more than just the instruction set.
  3381. It also indicates how that instruction set is implemented,
  3382. what kind of debug support it integrates,
  3383. whether it has an MMU (and if so, what kind),
  3384. what core-specific commands may be available
  3385. (@pxref{Architecture and Core Commands}),
  3386. and more.
  3387. For some CPU types, OpenOCD also defines @dfn{variants} which
  3388. indicate differences that affect their handling.
  3389. For example, a particular implementation bug might need to be
  3390. worked around in some chip versions.
  3391. It's easy to see what target types are supported,
  3392. since there's a command to list them.
  3393. However, there is currently no way to list what target variants
  3394. are supported (other than by reading the OpenOCD source code).
  3395. @anchor{targettypes}
  3396. @deffn Command {target types}
  3397. Lists all supported target types.
  3398. At this writing, the supported CPU types and variants are:
  3399. @itemize @bullet
  3400. @item @code{arm11} -- this is a generation of ARMv6 cores
  3401. @item @code{arm720t} -- this is an ARMv4 core with an MMU
  3402. @item @code{arm7tdmi} -- this is an ARMv4 core
  3403. @item @code{arm920t} -- this is an ARMv4 core with an MMU
  3404. @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
  3405. @item @code{arm966e} -- this is an ARMv5 core
  3406. @item @code{arm9tdmi} -- this is an ARMv4 core
  3407. @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
  3408. (Support for this is preliminary and incomplete.)
  3409. @item @code{cortex_a8} -- this is an ARMv7 core with an MMU
  3410. @item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
  3411. compact Thumb2 instruction set.
  3412. @item @code{dragonite} -- resembles arm966e
  3413. @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
  3414. (Support for this is still incomplete.)
  3415. @item @code{fa526} -- resembles arm920 (w/o Thumb)
  3416. @item @code{feroceon} -- resembles arm926
  3417. @item @code{mips_m4k} -- a MIPS core. This supports one variant:
  3418. @item @code{xscale} -- this is actually an architecture,
  3419. not a CPU type. It is based on the ARMv5 architecture.
  3420. There are several variants defined:
  3421. @itemize @minus
  3422. @item @code{ixp42x}, @code{ixp45x}, @code{ixp46x},
  3423. @code{pxa27x} ... instruction register length is 7 bits
  3424. @item @code{pxa250}, @code{pxa255},
  3425. @code{pxa26x} ... instruction register length is 5 bits
  3426. @item @code{pxa3xx} ... instruction register length is 11 bits
  3427. @end itemize
  3428. @end itemize
  3429. @end deffn
  3430. To avoid being confused by the variety of ARM based cores, remember
  3431. this key point: @emph{ARM is a technology licencing company}.
  3432. (See: @url{http://www.arm.com}.)
  3433. The CPU name used by OpenOCD will reflect the CPU design that was
  3434. licenced, not a vendor brand which incorporates that design.
  3435. Name prefixes like arm7, arm9, arm11, and cortex
  3436. reflect design generations;
  3437. while names like ARMv4, ARMv5, ARMv6, and ARMv7
  3438. reflect an architecture version implemented by a CPU design.
  3439. @anchor{targetconfiguration}
  3440. @section Target Configuration
  3441. Before creating a ``target'', you must have added its TAP to the scan chain.
  3442. When you've added that TAP, you will have a @code{dotted.name}
  3443. which is used to set up the CPU support.
  3444. The chip-specific configuration file will normally configure its CPU(s)
  3445. right after it adds all of the chip's TAPs to the scan chain.
  3446. Although you can set up a target in one step, it's often clearer if you
  3447. use shorter commands and do it in two steps: create it, then configure
  3448. optional parts.
  3449. All operations on the target after it's created will use a new
  3450. command, created as part of target creation.
  3451. The two main things to configure after target creation are
  3452. a work area, which usually has target-specific defaults even
  3453. if the board setup code overrides them later;
  3454. and event handlers (@pxref{targetevents,,Target Events}), which tend
  3455. to be much more board-specific.
  3456. The key steps you use might look something like this
  3457. @example
  3458. target create MyTarget cortex_m3 -chain-position mychip.cpu
  3459. $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
  3460. $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
  3461. $MyTarget configure -event reset-init @{ myboard_reinit @}
  3462. @end example
  3463. You should specify a working area if you can; typically it uses some
  3464. on-chip SRAM.
  3465. Such a working area can speed up many things, including bulk
  3466. writes to target memory;
  3467. flash operations like checking to see if memory needs to be erased;
  3468. GDB memory checksumming;
  3469. and more.
  3470. @quotation Warning
  3471. On more complex chips, the work area can become
  3472. inaccessible when application code
  3473. (such as an operating system)
  3474. enables or disables the MMU.
  3475. For example, the particular MMU context used to acess the virtual
  3476. address will probably matter ... and that context might not have
  3477. easy access to other addresses needed.
  3478. At this writing, OpenOCD doesn't have much MMU intelligence.
  3479. @end quotation
  3480. It's often very useful to define a @code{reset-init} event handler.
  3481. For systems that are normally used with a boot loader,
  3482. common tasks include updating clocks and initializing memory
  3483. controllers.
  3484. That may be needed to let you write the boot loader into flash,
  3485. in order to ``de-brick'' your board; or to load programs into
  3486. external DDR memory without having run the boot loader.
  3487. @deffn Command {target create} target_name type configparams...
  3488. This command creates a GDB debug target that refers to a specific JTAG tap.
  3489. It enters that target into a list, and creates a new
  3490. command (@command{@var{target_name}}) which is used for various
  3491. purposes including additional configuration.
  3492. @itemize @bullet
  3493. @item @var{target_name} ... is the name of the debug target.
  3494. By convention this should be the same as the @emph{dotted.name}
  3495. of the TAP associated with this target, which must be specified here
  3496. using the @code{-chain-position @var{dotted.name}} configparam.
  3497. This name is also used to create the target object command,
  3498. referred to here as @command{$target_name},
  3499. and in other places the target needs to be identified.
  3500. @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
  3501. @item @var{configparams} ... all parameters accepted by
  3502. @command{$target_name configure} are permitted.
  3503. If the target is big-endian, set it here with @code{-endian big}.
  3504. If the variant matters, set it here with @code{-variant}.
  3505. You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
  3506. @end itemize
  3507. @end deffn
  3508. @deffn Command {$target_name configure} configparams...
  3509. The options accepted by this command may also be
  3510. specified as parameters to @command{target create}.
  3511. Their values can later be queried one at a time by
  3512. using the @command{$target_name cget} command.
  3513. @emph{Warning:} changing some of these after setup is dangerous.
  3514. For example, moving a target from one TAP to another;
  3515. and changing its endianness or variant.
  3516. @itemize @bullet
  3517. @item @code{-chain-position} @var{dotted.name} -- names the TAP
  3518. used to access this target.
  3519. @item @code{-endian} (@option{big}|@option{little}) -- specifies
  3520. whether the CPU uses big or little endian conventions
  3521. @item @code{-event} @var{event_name} @var{event_body} --
  3522. @xref{targetevents,,Target Events}.
  3523. Note that this updates a list of named event handlers.
  3524. Calling this twice with two different event names assigns
  3525. two different handlers, but calling it twice with the
  3526. same event name assigns only one handler.
  3527. @item @code{-variant} @var{name} -- specifies a variant of the target,
  3528. which OpenOCD needs to know about.
  3529. @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
  3530. whether the work area gets backed up; by default,
  3531. @emph{it is not backed up.}
  3532. When possible, use a working_area that doesn't need to be backed up,
  3533. since performing a backup slows down operations.
  3534. For example, the beginning of an SRAM block is likely to
  3535. be used by most build systems, but the end is often unused.
  3536. @item @code{-work-area-size} @var{size} -- specify work are size,
  3537. in bytes. The same size applies regardless of whether its physical
  3538. or virtual address is being used.
  3539. @item @code{-work-area-phys} @var{address} -- set the work area
  3540. base @var{address} to be used when no MMU is active.
  3541. @item @code{-work-area-virt} @var{address} -- set the work area
  3542. base @var{address} to be used when an MMU is active.
  3543. @emph{Do not specify a value for this except on targets with an MMU.}
  3544. The value should normally correspond to a static mapping for the
  3545. @code{-work-area-phys} address, set up by the current operating system.
  3546. @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
  3547. @var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}|
  3548. @option{FreeRTOS}|@option{linux}|@option{ChibiOS}.
  3549. @end itemize
  3550. @end deffn
  3551. @section Other $target_name Commands
  3552. @cindex object command
  3553. The Tcl/Tk language has the concept of object commands,
  3554. and OpenOCD adopts that same model for targets.
  3555. A good Tk example is a on screen button.
  3556. Once a button is created a button
  3557. has a name (a path in Tk terms) and that name is useable as a first
  3558. class command. For example in Tk, one can create a button and later
  3559. configure it like this:
  3560. @example
  3561. # Create
  3562. button .foobar -background red -command @{ foo @}
  3563. # Modify
  3564. .foobar configure -foreground blue
  3565. # Query
  3566. set x [.foobar cget -background]
  3567. # Report
  3568. puts [format "The button is %s" $x]
  3569. @end example
  3570. In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
  3571. button, and its object commands are invoked the same way.
  3572. @example
  3573. str912.cpu mww 0x1234 0x42
  3574. omap3530.cpu mww 0x5555 123
  3575. @end example
  3576. The commands supported by OpenOCD target objects are:
  3577. @deffn Command {$target_name arp_examine}
  3578. @deffnx Command {$target_name arp_halt}
  3579. @deffnx Command {$target_name arp_poll}
  3580. @deffnx Command {$target_name arp_reset}
  3581. @deffnx Command {$target_name arp_waitstate}
  3582. Internal OpenOCD scripts (most notably @file{startup.tcl})
  3583. use these to deal with specific reset cases.
  3584. They are not otherwise documented here.
  3585. @end deffn
  3586. @deffn Command {$target_name array2mem} arrayname width address count
  3587. @deffnx Command {$target_name mem2array} arrayname width address count
  3588. These provide an efficient script-oriented interface to memory.
  3589. The @code{array2mem} primitive writes bytes, halfwords, or words;
  3590. while @code{mem2array} reads them.
  3591. In both cases, the TCL side uses an array, and
  3592. the target side uses raw memory.
  3593. The efficiency comes from enabling the use of
  3594. bulk JTAG data transfer operations.
  3595. The script orientation comes from working with data
  3596. values that are packaged for use by TCL scripts;
  3597. @command{mdw} type primitives only print data they retrieve,
  3598. and neither store nor return those values.
  3599. @itemize
  3600. @item @var{arrayname} ... is the name of an array variable
  3601. @item @var{width} ... is 8/16/32 - indicating the memory access size
  3602. @item @var{address} ... is the target memory address
  3603. @item @var{count} ... is the number of elements to process
  3604. @end itemize
  3605. @end deffn
  3606. @deffn Command {$target_name cget} queryparm
  3607. Each configuration parameter accepted by
  3608. @command{$target_name configure}
  3609. can be individually queried, to return its current value.
  3610. The @var{queryparm} is a parameter name
  3611. accepted by that command, such as @code{-work-area-phys}.
  3612. There are a few special cases:
  3613. @itemize @bullet
  3614. @item @code{-event} @var{event_name} -- returns the handler for the
  3615. event named @var{event_name}.
  3616. This is a special case because setting a handler requires
  3617. two parameters.
  3618. @item @code{-type} -- returns the target type.
  3619. This is a special case because this is set using
  3620. @command{target create} and can't be changed
  3621. using @command{$target_name configure}.
  3622. @end itemize
  3623. For example, if you wanted to summarize information about
  3624. all the targets you might use something like this:
  3625. @example
  3626. foreach name [target names] @{
  3627. set y [$name cget -endian]
  3628. set z [$name cget -type]
  3629. puts [format "Chip %d is %s, Endian: %s, type: %s" \
  3630. $x $name $y $z]
  3631. @}
  3632. @end example
  3633. @end deffn
  3634. @anchor{targetcurstate}
  3635. @deffn Command {$target_name curstate}
  3636. Displays the current target state:
  3637. @code{debug-running},
  3638. @code{halted},
  3639. @code{reset},
  3640. @code{running}, or @code{unknown}.
  3641. (Also, @pxref{eventpolling,,Event Polling}.)
  3642. @end deffn
  3643. @deffn Command {$target_name eventlist}
  3644. Displays a table listing all event handlers
  3645. currently associated with this target.
  3646. @xref{targetevents,,Target Events}.
  3647. @end deffn
  3648. @deffn Command {$target_name invoke-event} event_name
  3649. Invokes the handler for the event named @var{event_name}.
  3650. (This is primarily intended for use by OpenOCD framework
  3651. code, for example by the reset code in @file{startup.tcl}.)
  3652. @end deffn
  3653. @deffn Command {$target_name mdw} addr [count]
  3654. @deffnx Command {$target_name mdh} addr [count]
  3655. @deffnx Command {$target_name mdb} addr [count]
  3656. Display contents of address @var{addr}, as
  3657. 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
  3658. or 8-bit bytes (@command{mdb}).
  3659. If @var{count} is specified, displays that many units.
  3660. (If you want to manipulate the data instead of displaying it,
  3661. see the @code{mem2array} primitives.)
  3662. @end deffn
  3663. @deffn Command {$target_name mww} addr word
  3664. @deffnx Command {$target_name mwh} addr halfword
  3665. @deffnx Command {$target_name mwb} addr byte
  3666. Writes the specified @var{word} (32 bits),
  3667. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  3668. at the specified address @var{addr}.
  3669. @end deffn
  3670. @anchor{targetevents}
  3671. @section Target Events
  3672. @cindex target events
  3673. @cindex events
  3674. At various times, certain things can happen, or you want them to happen.
  3675. For example:
  3676. @itemize @bullet
  3677. @item What should happen when GDB connects? Should your target reset?
  3678. @item When GDB tries to flash the target, do you need to enable the flash via a special command?
  3679. @item Is using SRST appropriate (and possible) on your system?
  3680. Or instead of that, do you need to issue JTAG commands to trigger reset?
  3681. SRST usually resets everything on the scan chain, which can be inappropriate.
  3682. @item During reset, do you need to write to certain memory locations
  3683. to set up system clocks or
  3684. to reconfigure the SDRAM?
  3685. How about configuring the watchdog timer, or other peripherals,
  3686. to stop running while you hold the core stopped for debugging?
  3687. @end itemize
  3688. All of the above items can be addressed by target event handlers.
  3689. These are set up by @command{$target_name configure -event} or
  3690. @command{target create ... -event}.
  3691. The programmer's model matches the @code{-command} option used in Tcl/Tk
  3692. buttons and events. The two examples below act the same, but one creates
  3693. and invokes a small procedure while the other inlines it.
  3694. @example
  3695. proc my_attach_proc @{ @} @{
  3696. echo "Reset..."
  3697. reset halt
  3698. @}
  3699. mychip.cpu configure -event gdb-attach my_attach_proc
  3700. mychip.cpu configure -event gdb-attach @{
  3701. echo "Reset..."
  3702. # To make flash probe and gdb load to flash work we need a reset init.
  3703. reset init
  3704. @}
  3705. @end example
  3706. The following target events are defined:
  3707. @itemize @bullet
  3708. @item @b{debug-halted}
  3709. @* The target has halted for debug reasons (i.e.: breakpoint)
  3710. @item @b{debug-resumed}
  3711. @* The target has resumed (i.e.: gdb said run)
  3712. @item @b{early-halted}
  3713. @* Occurs early in the halt process
  3714. @item @b{examine-start}
  3715. @* Before target examine is called.
  3716. @item @b{examine-end}
  3717. @* After target examine is called with no errors.
  3718. @item @b{gdb-attach}
  3719. @* When GDB connects. This is before any communication with the target, so this
  3720. can be used to set up the target so it is possible to probe flash. Probing flash
  3721. is necessary during gdb connect if gdb load is to write the image to flash. Another
  3722. use of the flash memory map is for GDB to automatically hardware/software breakpoints
  3723. depending on whether the breakpoint is in RAM or read only memory.
  3724. @item @b{gdb-detach}
  3725. @* When GDB disconnects
  3726. @item @b{gdb-end}
  3727. @* When the target has halted and GDB is not doing anything (see early halt)
  3728. @item @b{gdb-flash-erase-start}
  3729. @* Before the GDB flash process tries to erase the flash
  3730. @item @b{gdb-flash-erase-end}
  3731. @* After the GDB flash process has finished erasing the flash
  3732. @item @b{gdb-flash-write-start}
  3733. @* Before GDB writes to the flash
  3734. @item @b{gdb-flash-write-end}
  3735. @* After GDB writes to the flash
  3736. @item @b{gdb-start}
  3737. @* Before the target steps, gdb is trying to start/resume the target
  3738. @item @b{halted}
  3739. @* The target has halted
  3740. @item @b{reset-assert-pre}
  3741. @* Issued as part of @command{reset} processing
  3742. after @command{reset_init} was triggered
  3743. but before either SRST alone is re-asserted on the scan chain,
  3744. or @code{reset-assert} is triggered.
  3745. @item @b{reset-assert}
  3746. @* Issued as part of @command{reset} processing
  3747. after @command{reset-assert-pre} was triggered.
  3748. When such a handler is present, cores which support this event will use
  3749. it instead of asserting SRST.
  3750. This support is essential for debugging with JTAG interfaces which
  3751. don't include an SRST line (JTAG doesn't require SRST), and for
  3752. selective reset on scan chains that have multiple targets.
  3753. @item @b{reset-assert-post}
  3754. @* Issued as part of @command{reset} processing
  3755. after @code{reset-assert} has been triggered.
  3756. or the target asserted SRST on the entire scan chain.
  3757. @item @b{reset-deassert-pre}
  3758. @* Issued as part of @command{reset} processing
  3759. after @code{reset-assert-post} has been triggered.
  3760. @item @b{reset-deassert-post}
  3761. @* Issued as part of @command{reset} processing
  3762. after @code{reset-deassert-pre} has been triggered
  3763. and (if the target is using it) after SRST has been
  3764. released on the scan chain.
  3765. @item @b{reset-end}
  3766. @* Issued as the final step in @command{reset} processing.
  3767. @ignore
  3768. @item @b{reset-halt-post}
  3769. @* Currently not used
  3770. @item @b{reset-halt-pre}
  3771. @* Currently not used
  3772. @end ignore
  3773. @item @b{reset-init}
  3774. @* Used by @b{reset init} command for board-specific initialization.
  3775. This event fires after @emph{reset-deassert-post}.
  3776. This is where you would configure PLLs and clocking, set up DRAM so
  3777. you can download programs that don't fit in on-chip SRAM, set up pin
  3778. multiplexing, and so on.
  3779. (You may be able to switch to a fast JTAG clock rate here, after
  3780. the target clocks are fully set up.)
  3781. @item @b{reset-start}
  3782. @* Issued as part of @command{reset} processing
  3783. before @command{reset_init} is called.
  3784. This is the most robust place to use @command{jtag_rclk}
  3785. or @command{adapter_khz} to switch to a low JTAG clock rate,
  3786. when reset disables PLLs needed to use a fast clock.
  3787. @ignore
  3788. @item @b{reset-wait-pos}
  3789. @* Currently not used
  3790. @item @b{reset-wait-pre}
  3791. @* Currently not used
  3792. @end ignore
  3793. @item @b{resume-start}
  3794. @* Before any target is resumed
  3795. @item @b{resume-end}
  3796. @* After all targets have resumed
  3797. @item @b{resumed}
  3798. @* Target has resumed
  3799. @end itemize
  3800. @node Flash Commands
  3801. @chapter Flash Commands
  3802. OpenOCD has different commands for NOR and NAND flash;
  3803. the ``flash'' command works with NOR flash, while
  3804. the ``nand'' command works with NAND flash.
  3805. This partially reflects different hardware technologies:
  3806. NOR flash usually supports direct CPU instruction and data bus access,
  3807. while data from a NAND flash must be copied to memory before it can be
  3808. used. (SPI flash must also be copied to memory before use.)
  3809. However, the documentation also uses ``flash'' as a generic term;
  3810. for example, ``Put flash configuration in board-specific files''.
  3811. Flash Steps:
  3812. @enumerate
  3813. @item Configure via the command @command{flash bank}
  3814. @* Do this in a board-specific configuration file,
  3815. passing parameters as needed by the driver.
  3816. @item Operate on the flash via @command{flash subcommand}
  3817. @* Often commands to manipulate the flash are typed by a human, or run
  3818. via a script in some automated way. Common tasks include writing a
  3819. boot loader, operating system, or other data.
  3820. @item GDB Flashing
  3821. @* Flashing via GDB requires the flash be configured via ``flash
  3822. bank'', and the GDB flash features be enabled.
  3823. @xref{gdbconfiguration,,GDB Configuration}.
  3824. @end enumerate
  3825. Many CPUs have the ablity to ``boot'' from the first flash bank.
  3826. This means that misprogramming that bank can ``brick'' a system,
  3827. so that it can't boot.
  3828. JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
  3829. board by (re)installing working boot firmware.
  3830. @anchor{norconfiguration}
  3831. @section Flash Configuration Commands
  3832. @cindex flash configuration
  3833. @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
  3834. Configures a flash bank which provides persistent storage
  3835. for addresses from @math{base} to @math{base + size - 1}.
  3836. These banks will often be visible to GDB through the target's memory map.
  3837. In some cases, configuring a flash bank will activate extra commands;
  3838. see the driver-specific documentation.
  3839. @itemize @bullet
  3840. @item @var{name} ... may be used to reference the flash bank
  3841. in other flash commands. A number is also available.
  3842. @item @var{driver} ... identifies the controller driver
  3843. associated with the flash bank being declared.
  3844. This is usually @code{cfi} for external flash, or else
  3845. the name of a microcontroller with embedded flash memory.
  3846. @xref{flashdriverlist,,Flash Driver List}.
  3847. @item @var{base} ... Base address of the flash chip.
  3848. @item @var{size} ... Size of the chip, in bytes.
  3849. For some drivers, this value is detected from the hardware.
  3850. @item @var{chip_width} ... Width of the flash chip, in bytes;
  3851. ignored for most microcontroller drivers.
  3852. @item @var{bus_width} ... Width of the data bus used to access the
  3853. chip, in bytes; ignored for most microcontroller drivers.
  3854. @item @var{target} ... Names the target used to issue
  3855. commands to the flash controller.
  3856. @comment Actually, it's currently a controller-specific parameter...
  3857. @item @var{driver_options} ... drivers may support, or require,
  3858. additional parameters. See the driver-specific documentation
  3859. for more information.
  3860. @end itemize
  3861. @quotation Note
  3862. This command is not available after OpenOCD initialization has completed.
  3863. Use it in board specific configuration files, not interactively.
  3864. @end quotation
  3865. @end deffn
  3866. @comment the REAL name for this command is "ocd_flash_banks"
  3867. @comment less confusing would be: "flash list" (like "nand list")
  3868. @deffn Command {flash banks}
  3869. Prints a one-line summary of each device that was
  3870. declared using @command{flash bank}, numbered from zero.
  3871. Note that this is the @emph{plural} form;
  3872. the @emph{singular} form is a very different command.
  3873. @end deffn
  3874. @deffn Command {flash list}
  3875. Retrieves a list of associative arrays for each device that was
  3876. declared using @command{flash bank}, numbered from zero.
  3877. This returned list can be manipulated easily from within scripts.
  3878. @end deffn
  3879. @deffn Command {flash probe} num
  3880. Identify the flash, or validate the parameters of the configured flash. Operation
  3881. depends on the flash type.
  3882. The @var{num} parameter is a value shown by @command{flash banks}.
  3883. Most flash commands will implicitly @emph{autoprobe} the bank;
  3884. flash drivers can distinguish between probing and autoprobing,
  3885. but most don't bother.
  3886. @end deffn
  3887. @section Erasing, Reading, Writing to Flash
  3888. @cindex flash erasing
  3889. @cindex flash reading
  3890. @cindex flash writing
  3891. @cindex flash programming
  3892. @anchor{flashprogrammingcommands}
  3893. One feature distinguishing NOR flash from NAND or serial flash technologies
  3894. is that for read access, it acts exactly like any other addressible memory.
  3895. This means you can use normal memory read commands like @command{mdw} or
  3896. @command{dump_image} with it, with no special @command{flash} subcommands.
  3897. @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
  3898. Write access works differently. Flash memory normally needs to be erased
  3899. before it's written. Erasing a sector turns all of its bits to ones, and
  3900. writing can turn ones into zeroes. This is why there are special commands
  3901. for interactive erasing and writing, and why GDB needs to know which parts
  3902. of the address space hold NOR flash memory.
  3903. @quotation Note
  3904. Most of these erase and write commands leverage the fact that NOR flash
  3905. chips consume target address space. They implicitly refer to the current
  3906. JTAG target, and map from an address in that target's address space
  3907. back to a flash bank.
  3908. @comment In May 2009, those mappings may fail if any bank associated
  3909. @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
  3910. A few commands use abstract addressing based on bank and sector numbers,
  3911. and don't depend on searching the current target and its address space.
  3912. Avoid confusing the two command models.
  3913. @end quotation
  3914. Some flash chips implement software protection against accidental writes,
  3915. since such buggy writes could in some cases ``brick'' a system.
  3916. For such systems, erasing and writing may require sector protection to be
  3917. disabled first.
  3918. Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
  3919. and AT91SAM7 on-chip flash.
  3920. @xref{flashprotect,,flash protect}.
  3921. @deffn Command {flash erase_sector} num first last
  3922. Erase sectors in bank @var{num}, starting at sector @var{first}
  3923. up to and including @var{last}.
  3924. Sector numbering starts at 0.
  3925. Providing a @var{last} sector of @option{last}
  3926. specifies "to the end of the flash bank".
  3927. The @var{num} parameter is a value shown by @command{flash banks}.
  3928. @end deffn
  3929. @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
  3930. Erase sectors starting at @var{address} for @var{length} bytes.
  3931. Unless @option{pad} is specified, @math{address} must begin a
  3932. flash sector, and @math{address + length - 1} must end a sector.
  3933. Specifying @option{pad} erases extra data at the beginning and/or
  3934. end of the specified region, as needed to erase only full sectors.
  3935. The flash bank to use is inferred from the @var{address}, and
  3936. the specified length must stay within that bank.
  3937. As a special case, when @var{length} is zero and @var{address} is
  3938. the start of the bank, the whole flash is erased.
  3939. If @option{unlock} is specified, then the flash is unprotected
  3940. before erase starts.
  3941. @end deffn
  3942. @deffn Command {flash fillw} address word length
  3943. @deffnx Command {flash fillh} address halfword length
  3944. @deffnx Command {flash fillb} address byte length
  3945. Fills flash memory with the specified @var{word} (32 bits),
  3946. @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
  3947. starting at @var{address} and continuing
  3948. for @var{length} units (word/halfword/byte).
  3949. No erasure is done before writing; when needed, that must be done
  3950. before issuing this command.
  3951. Writes are done in blocks of up to 1024 bytes, and each write is
  3952. verified by reading back the data and comparing it to what was written.
  3953. The flash bank to use is inferred from the @var{address} of
  3954. each block, and the specified length must stay within that bank.
  3955. @end deffn
  3956. @comment no current checks for errors if fill blocks touch multiple banks!
  3957. @deffn Command {flash write_bank} num filename offset
  3958. Write the binary @file{filename} to flash bank @var{num},
  3959. starting at @var{offset} bytes from the beginning of the bank.
  3960. The @var{num} parameter is a value shown by @command{flash banks}.
  3961. @end deffn
  3962. @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
  3963. Write the image @file{filename} to the current target's flash bank(s).
  3964. A relocation @var{offset} may be specified, in which case it is added
  3965. to the base address for each section in the image.
  3966. The file [@var{type}] can be specified
  3967. explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
  3968. @option{elf} (ELF file), @option{s19} (Motorola s19).
  3969. @option{mem}, or @option{builder}.
  3970. The relevant flash sectors will be erased prior to programming
  3971. if the @option{erase} parameter is given. If @option{unlock} is
  3972. provided, then the flash banks are unlocked before erase and
  3973. program. The flash bank to use is inferred from the address of
  3974. each image section.
  3975. @quotation Warning
  3976. Be careful using the @option{erase} flag when the flash is holding
  3977. data you want to preserve.
  3978. Portions of the flash outside those described in the image's
  3979. sections might be erased with no notice.
  3980. @itemize
  3981. @item
  3982. When a section of the image being written does not fill out all the
  3983. sectors it uses, the unwritten parts of those sectors are necessarily
  3984. also erased, because sectors can't be partially erased.
  3985. @item
  3986. Data stored in sector "holes" between image sections are also affected.
  3987. For example, "@command{flash write_image erase ...}" of an image with
  3988. one byte at the beginning of a flash bank and one byte at the end
  3989. erases the entire bank -- not just the two sectors being written.
  3990. @end itemize
  3991. Also, when flash protection is important, you must re-apply it after
  3992. it has been removed by the @option{unlock} flag.
  3993. @end quotation
  3994. @end deffn
  3995. @section Other Flash commands
  3996. @cindex flash protection
  3997. @deffn Command {flash erase_check} num
  3998. Check erase state of sectors in flash bank @var{num},
  3999. and display that status.
  4000. The @var{num} parameter is a value shown by @command{flash banks}.
  4001. @end deffn
  4002. @deffn Command {flash info} num
  4003. Print info about flash bank @var{num}
  4004. The @var{num} parameter is a value shown by @command{flash banks}.
  4005. This command will first query the hardware, it does not print cached
  4006. and possibly stale information.
  4007. @end deffn
  4008. @anchor{flashprotect}
  4009. @deffn Command {flash protect} num first last (@option{on}|@option{off})
  4010. Enable (@option{on}) or disable (@option{off}) protection of flash sectors
  4011. in flash bank @var{num}, starting at sector @var{first}
  4012. and continuing up to and including @var{last}.
  4013. Providing a @var{last} sector of @option{last}
  4014. specifies "to the end of the flash bank".
  4015. The @var{num} parameter is a value shown by @command{flash banks}.
  4016. @end deffn
  4017. @anchor{program}
  4018. @deffn Command {program} filename [verify] [reset] [offset]
  4019. This is a helper script that simplifies using OpenOCD as a standalone
  4020. programmer. The only required parameter is @option{filename}, the others are optional.
  4021. @xref{Flash Programming}.
  4022. @end deffn
  4023. @anchor{flashdriverlist}
  4024. @section Flash Driver List
  4025. As noted above, the @command{flash bank} command requires a driver name,
  4026. and allows driver-specific options and behaviors.
  4027. Some drivers also activate driver-specific commands.
  4028. @subsection External Flash
  4029. @deffn {Flash Driver} cfi
  4030. @cindex Common Flash Interface
  4031. @cindex CFI
  4032. The ``Common Flash Interface'' (CFI) is the main standard for
  4033. external NOR flash chips, each of which connects to a
  4034. specific external chip select on the CPU.
  4035. Frequently the first such chip is used to boot the system.
  4036. Your board's @code{reset-init} handler might need to
  4037. configure additional chip selects using other commands (like: @command{mww} to
  4038. configure a bus and its timings), or
  4039. perhaps configure a GPIO pin that controls the ``write protect'' pin
  4040. on the flash chip.
  4041. The CFI driver can use a target-specific working area to significantly
  4042. speed up operation.
  4043. The CFI driver can accept the following optional parameters, in any order:
  4044. @itemize
  4045. @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
  4046. like AM29LV010 and similar types.
  4047. @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
  4048. @end itemize
  4049. To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
  4050. wide on a sixteen bit bus:
  4051. @example
  4052. flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
  4053. flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
  4054. @end example
  4055. To configure one bank of 32 MBytes
  4056. built from two sixteen bit (two byte) wide parts wired in parallel
  4057. to create a thirty-two bit (four byte) bus with doubled throughput:
  4058. @example
  4059. flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
  4060. @end example
  4061. @c "cfi part_id" disabled
  4062. @end deffn
  4063. @deffn {Flash Driver} lpcspifi
  4064. @cindex NXP SPI Flash Interface
  4065. @cindex SPIFI
  4066. @cindex lpcspifi
  4067. NXP's LPC43xx and LPC18xx families include a proprietary SPI
  4068. Flash Interface (SPIFI) peripheral that can drive and provide
  4069. memory mapped access to external SPI flash devices.
  4070. The lpcspifi driver initializes this interface and provides
  4071. program and erase functionality for these serial flash devices.
  4072. Use of this driver @b{requires} a working area of at least 1kB
  4073. to be configured on the target device; more than this will
  4074. significantly reduce flash programming times.
  4075. The setup command only requires the @var{base} parameter. All
  4076. other parameters are ignored, and the flash size and layout
  4077. are configured by the driver.
  4078. @example
  4079. flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
  4080. @end example
  4081. @end deffn
  4082. @deffn {Flash Driver} stmsmi
  4083. @cindex STMicroelectronics Serial Memory Interface
  4084. @cindex SMI
  4085. @cindex stmsmi
  4086. Some devices form STMicroelectronics (e.g. STR75x MCU family,
  4087. SPEAr MPU family) include a proprietary
  4088. ``Serial Memory Interface'' (SMI) controller able to drive external
  4089. SPI flash devices.
  4090. Depending on specific device and board configuration, up to 4 external
  4091. flash devices can be connected.
  4092. SMI makes the flash content directly accessible in the CPU address
  4093. space; each external device is mapped in a memory bank.
  4094. CPU can directly read data, execute code and boot from SMI banks.
  4095. Normal OpenOCD commands like @command{mdw} can be used to display
  4096. the flash content.
  4097. The setup command only requires the @var{base} parameter in order
  4098. to identify the memory bank.
  4099. All other parameters are ignored. Additional information, like
  4100. flash size, are detected automatically.
  4101. @example
  4102. flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
  4103. @end example
  4104. @end deffn
  4105. @subsection Internal Flash (Microcontrollers)
  4106. @deffn {Flash Driver} aduc702x
  4107. The ADUC702x analog microcontrollers from Analog Devices
  4108. include internal flash and use ARM7TDMI cores.
  4109. The aduc702x flash driver works with models ADUC7019 through ADUC7028.
  4110. The setup command only requires the @var{target} argument
  4111. since all devices in this family have the same memory layout.
  4112. @example
  4113. flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
  4114. @end example
  4115. @end deffn
  4116. @anchor{at91sam3}
  4117. @deffn {Flash Driver} at91sam3
  4118. @cindex at91sam3
  4119. All members of the AT91SAM3 microcontroller family from
  4120. Atmel include internal flash and use ARM's Cortex-M3 core. The driver
  4121. currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
  4122. that the driver was orginaly developed and tested using the
  4123. AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
  4124. the family was cribbed from the data sheet. @emph{Note to future
  4125. readers/updaters: Please remove this worrysome comment after other
  4126. chips are confirmed.}
  4127. The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
  4128. have one flash bank. In all cases the flash banks are at
  4129. the following fixed locations:
  4130. @example
  4131. # Flash bank 0 - all chips
  4132. flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
  4133. # Flash bank 1 - only 256K chips
  4134. flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
  4135. @end example
  4136. Internally, the AT91SAM3 flash memory is organized as follows.
  4137. Unlike the AT91SAM7 chips, these are not used as parameters
  4138. to the @command{flash bank} command:
  4139. @itemize
  4140. @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
  4141. @item @emph{Bank Size:} 128K/64K Per flash bank
  4142. @item @emph{Sectors:} 16 or 8 per bank
  4143. @item @emph{SectorSize:} 8K Per Sector
  4144. @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
  4145. @end itemize
  4146. The AT91SAM3 driver adds some additional commands:
  4147. @deffn Command {at91sam3 gpnvm}
  4148. @deffnx Command {at91sam3 gpnvm clear} number
  4149. @deffnx Command {at91sam3 gpnvm set} number
  4150. @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
  4151. With no parameters, @command{show} or @command{show all},
  4152. shows the status of all GPNVM bits.
  4153. With @command{show} @var{number}, displays that bit.
  4154. With @command{set} @var{number} or @command{clear} @var{number},
  4155. modifies that GPNVM bit.
  4156. @end deffn
  4157. @deffn Command {at91sam3 info}
  4158. This command attempts to display information about the AT91SAM3
  4159. chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
  4160. Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
  4161. document id: doc6430A] and decodes the values. @emph{Second} it reads the
  4162. various clock configuration registers and attempts to display how it
  4163. believes the chip is configured. By default, the SLOWCLK is assumed to
  4164. be 32768 Hz, see the command @command{at91sam3 slowclk}.
  4165. @end deffn
  4166. @deffn Command {at91sam3 slowclk} [value]
  4167. This command shows/sets the slow clock frequency used in the
  4168. @command{at91sam3 info} command calculations above.
  4169. @end deffn
  4170. @end deffn
  4171. @deffn {Flash Driver} at91sam4
  4172. @cindex at91sam4
  4173. All members of the AT91SAM4 microcontroller family from
  4174. Atmel include internal flash and use ARM's Cortex-M4 core.
  4175. This driver uses the same cmd names/syntax as @xref{at91sam3}.
  4176. @end deffn
  4177. @deffn {Flash Driver} at91sam7
  4178. All members of the AT91SAM7 microcontroller family from Atmel include
  4179. internal flash and use ARM7TDMI cores. The driver automatically
  4180. recognizes a number of these chips using the chip identification
  4181. register, and autoconfigures itself.
  4182. @example
  4183. flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
  4184. @end example
  4185. For chips which are not recognized by the controller driver, you must
  4186. provide additional parameters in the following order:
  4187. @itemize
  4188. @item @var{chip_model} ... label used with @command{flash info}
  4189. @item @var{banks}
  4190. @item @var{sectors_per_bank}
  4191. @item @var{pages_per_sector}
  4192. @item @var{pages_size}
  4193. @item @var{num_nvm_bits}
  4194. @item @var{freq_khz} ... required if an external clock is provided,
  4195. optional (but recommended) when the oscillator frequency is known
  4196. @end itemize
  4197. It is recommended that you provide zeroes for all of those values
  4198. except the clock frequency, so that everything except that frequency
  4199. will be autoconfigured.
  4200. Knowing the frequency helps ensure correct timings for flash access.
  4201. The flash controller handles erases automatically on a page (128/256 byte)
  4202. basis, so explicit erase commands are not necessary for flash programming.
  4203. However, there is an ``EraseAll`` command that can erase an entire flash
  4204. plane (of up to 256KB), and it will be used automatically when you issue
  4205. @command{flash erase_sector} or @command{flash erase_address} commands.
  4206. @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
  4207. Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
  4208. bit for the processor. Each processor has a number of such bits,
  4209. used for controlling features such as brownout detection (so they
  4210. are not truly general purpose).
  4211. @quotation Note
  4212. This assumes that the first flash bank (number 0) is associated with
  4213. the appropriate at91sam7 target.
  4214. @end quotation
  4215. @end deffn
  4216. @end deffn
  4217. @deffn {Flash Driver} avr
  4218. The AVR 8-bit microcontrollers from Atmel integrate flash memory.
  4219. @emph{The current implementation is incomplete.}
  4220. @comment - defines mass_erase ... pointless given flash_erase_address
  4221. @end deffn
  4222. @deffn {Flash Driver} efm32
  4223. All members of the EFM32 microcontroller family from Energy Micro include
  4224. internal flash and use ARM Cortex M3 cores. The driver automatically recognizes
  4225. a number of these chips using the chip identification register, and
  4226. autoconfigures itself.
  4227. @example
  4228. flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
  4229. @end example
  4230. @emph{The current implementation is incomplete. Unprotecting flash pages is not
  4231. supported.}
  4232. @end deffn
  4233. @deffn {Flash Driver} lpc2000
  4234. Most members of the LPC1700 and LPC2000 microcontroller families from NXP
  4235. include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
  4236. @quotation Note
  4237. There are LPC2000 devices which are not supported by the @var{lpc2000}
  4238. driver:
  4239. The LPC2888 is supported by the @var{lpc288x} driver.
  4240. The LPC29xx family is supported by the @var{lpc2900} driver.
  4241. @end quotation
  4242. The @var{lpc2000} driver defines two mandatory and one optional parameters,
  4243. which must appear in the following order:
  4244. @itemize
  4245. @item @var{variant} ... required, may be
  4246. @option{lpc2000_v1} (older LPC21xx and LPC22xx)
  4247. @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
  4248. or @option{lpc1700} (LPC175x and LPC176x)
  4249. @item @var{clock_kHz} ... the frequency, in kiloHertz,
  4250. at which the core is running
  4251. @item @option{calc_checksum} ... optional (but you probably want to provide this!),
  4252. telling the driver to calculate a valid checksum for the exception vector table.
  4253. @quotation Note
  4254. If you don't provide @option{calc_checksum} when you're writing the vector
  4255. table, the boot ROM will almost certainly ignore your flash image.
  4256. However, if you do provide it,
  4257. with most tool chains @command{verify_image} will fail.
  4258. @end quotation
  4259. @end itemize
  4260. LPC flashes don't require the chip and bus width to be specified.
  4261. @example
  4262. flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
  4263. lpc2000_v2 14765 calc_checksum
  4264. @end example
  4265. @deffn {Command} {lpc2000 part_id} bank
  4266. Displays the four byte part identifier associated with
  4267. the specified flash @var{bank}.
  4268. @end deffn
  4269. @end deffn
  4270. @deffn {Flash Driver} lpc288x
  4271. The LPC2888 microcontroller from NXP needs slightly different flash
  4272. support from its lpc2000 siblings.
  4273. The @var{lpc288x} driver defines one mandatory parameter,
  4274. the programming clock rate in Hz.
  4275. LPC flashes don't require the chip and bus width to be specified.
  4276. @example
  4277. flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
  4278. @end example
  4279. @end deffn
  4280. @deffn {Flash Driver} lpc2900
  4281. This driver supports the LPC29xx ARM968E based microcontroller family
  4282. from NXP.
  4283. The predefined parameters @var{base}, @var{size}, @var{chip_width} and
  4284. @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
  4285. sector layout are auto-configured by the driver.
  4286. The driver has one additional mandatory parameter: The CPU clock rate
  4287. (in kHz) at the time the flash operations will take place. Most of the time this
  4288. will not be the crystal frequency, but a higher PLL frequency. The
  4289. @code{reset-init} event handler in the board script is usually the place where
  4290. you start the PLL.
  4291. The driver rejects flashless devices (currently the LPC2930).
  4292. The EEPROM in LPC2900 devices is not mapped directly into the address space.
  4293. It must be handled much more like NAND flash memory, and will therefore be
  4294. handled by a separate @code{lpc2900_eeprom} driver (not yet available).
  4295. Sector protection in terms of the LPC2900 is handled transparently. Every time a
  4296. sector needs to be erased or programmed, it is automatically unprotected.
  4297. What is shown as protection status in the @code{flash info} command, is
  4298. actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
  4299. sector from ever being erased or programmed again. As this is an irreversible
  4300. mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
  4301. and not by the standard @code{flash protect} command.
  4302. Example for a 125 MHz clock frequency:
  4303. @example
  4304. flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
  4305. @end example
  4306. Some @code{lpc2900}-specific commands are defined. In the following command list,
  4307. the @var{bank} parameter is the bank number as obtained by the
  4308. @code{flash banks} command.
  4309. @deffn Command {lpc2900 signature} bank
  4310. Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
  4311. content. This is a hardware feature of the flash block, hence the calculation is
  4312. very fast. You may use this to verify the content of a programmed device against
  4313. a known signature.
  4314. Example:
  4315. @example
  4316. lpc2900 signature 0
  4317. signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
  4318. @end example
  4319. @end deffn
  4320. @deffn Command {lpc2900 read_custom} bank filename
  4321. Reads the 912 bytes of customer information from the flash index sector, and
  4322. saves it to a file in binary format.
  4323. Example:
  4324. @example
  4325. lpc2900 read_custom 0 /path_to/customer_info.bin
  4326. @end example
  4327. @end deffn
  4328. The index sector of the flash is a @emph{write-only} sector. It cannot be
  4329. erased! In order to guard against unintentional write access, all following
  4330. commands need to be preceeded by a successful call to the @code{password}
  4331. command:
  4332. @deffn Command {lpc2900 password} bank password
  4333. You need to use this command right before each of the following commands:
  4334. @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
  4335. @code{lpc2900 secure_jtag}.
  4336. The password string is fixed to "I_know_what_I_am_doing".
  4337. Example:
  4338. @example
  4339. lpc2900 password 0 I_know_what_I_am_doing
  4340. Potentially dangerous operation allowed in next command!
  4341. @end example
  4342. @end deffn
  4343. @deffn Command {lpc2900 write_custom} bank filename type
  4344. Writes the content of the file into the customer info space of the flash index
  4345. sector. The filetype can be specified with the @var{type} field. Possible values
  4346. for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
  4347. @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
  4348. contain a single section, and the contained data length must be exactly
  4349. 912 bytes.
  4350. @quotation Attention
  4351. This cannot be reverted! Be careful!
  4352. @end quotation
  4353. Example:
  4354. @example
  4355. lpc2900 write_custom 0 /path_to/customer_info.bin bin
  4356. @end example
  4357. @end deffn
  4358. @deffn Command {lpc2900 secure_sector} bank first last
  4359. Secures the sector range from @var{first} to @var{last} (including) against
  4360. further program and erase operations. The sector security will be effective
  4361. after the next power cycle.
  4362. @quotation Attention
  4363. This cannot be reverted! Be careful!
  4364. @end quotation
  4365. Secured sectors appear as @emph{protected} in the @code{flash info} command.
  4366. Example:
  4367. @example
  4368. lpc2900 secure_sector 0 1 1
  4369. flash info 0
  4370. #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
  4371. # 0: 0x00000000 (0x2000 8kB) not protected
  4372. # 1: 0x00002000 (0x2000 8kB) protected
  4373. # 2: 0x00004000 (0x2000 8kB) not protected
  4374. @end example
  4375. @end deffn
  4376. @deffn Command {lpc2900 secure_jtag} bank
  4377. Irreversibly disable the JTAG port. The new JTAG security setting will be
  4378. effective after the next power cycle.
  4379. @quotation Attention
  4380. This cannot be reverted! Be careful!
  4381. @end quotation
  4382. Examples:
  4383. @example
  4384. lpc2900 secure_jtag 0
  4385. @end example
  4386. @end deffn
  4387. @end deffn
  4388. @deffn {Flash Driver} ocl
  4389. @emph{No idea what this is, other than using some arm7/arm9 core.}
  4390. @example
  4391. flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
  4392. @end example
  4393. @end deffn
  4394. @deffn {Flash Driver} pic32mx
  4395. The PIC32MX microcontrollers are based on the MIPS 4K cores,
  4396. and integrate flash memory.
  4397. @example
  4398. flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
  4399. flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
  4400. @end example
  4401. @comment numerous *disabled* commands are defined:
  4402. @comment - chip_erase ... pointless given flash_erase_address
  4403. @comment - lock, unlock ... pointless given protect on/off (yes?)
  4404. @comment - pgm_word ... shouldn't bank be deduced from address??
  4405. Some pic32mx-specific commands are defined:
  4406. @deffn Command {pic32mx pgm_word} address value bank
  4407. Programs the specified 32-bit @var{value} at the given @var{address}
  4408. in the specified chip @var{bank}.
  4409. @end deffn
  4410. @deffn Command {pic32mx unlock} bank
  4411. Unlock and erase specified chip @var{bank}.
  4412. This will remove any Code Protection.
  4413. @end deffn
  4414. @end deffn
  4415. @deffn {Flash Driver} stellaris
  4416. All members of the Stellaris LM3Sxxx microcontroller family from
  4417. Texas Instruments
  4418. include internal flash and use ARM Cortex M3 cores.
  4419. The driver automatically recognizes a number of these chips using
  4420. the chip identification register, and autoconfigures itself.
  4421. @footnote{Currently there is a @command{stellaris mass_erase} command.
  4422. That seems pointless since the same effect can be had using the
  4423. standard @command{flash erase_address} command.}
  4424. @example
  4425. flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
  4426. @end example
  4427. @deffn Command {stellaris recover bank_id}
  4428. Performs the @emph{Recovering a "Locked" Device} procedure to
  4429. restore the flash specified by @var{bank_id} and its associated
  4430. nonvolatile registers to their factory default values (erased).
  4431. This is the only way to remove flash protection or re-enable
  4432. debugging if that capability has been disabled.
  4433. Note that the final "power cycle the chip" step in this procedure
  4434. must be performed by hand, since OpenOCD can't do it.
  4435. @quotation Warning
  4436. if more than one Stellaris chip is connected, the procedure is
  4437. applied to all of them.
  4438. @end quotation
  4439. @end deffn
  4440. @end deffn
  4441. @deffn {Flash Driver} stm32f1x
  4442. All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
  4443. from ST Microelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
  4444. The driver automatically recognizes a number of these chips using
  4445. the chip identification register, and autoconfigures itself.
  4446. @example
  4447. flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
  4448. @end example
  4449. Note that some devices have been found that have a flash size register that contains
  4450. an invalid value, to workaround this issue you can override the probed value used by
  4451. the flash driver.
  4452. @example
  4453. flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
  4454. @end example
  4455. If you have a target with dual flash banks then define the second bank
  4456. as per the following example.
  4457. @example
  4458. flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
  4459. @end example
  4460. Some stm32f1x-specific commands
  4461. @footnote{Currently there is a @command{stm32f1x mass_erase} command.
  4462. That seems pointless since the same effect can be had using the
  4463. standard @command{flash erase_address} command.}
  4464. are defined:
  4465. @deffn Command {stm32f1x lock} num
  4466. Locks the entire stm32 device.
  4467. The @var{num} parameter is a value shown by @command{flash banks}.
  4468. @end deffn
  4469. @deffn Command {stm32f1x unlock} num
  4470. Unlocks the entire stm32 device.
  4471. The @var{num} parameter is a value shown by @command{flash banks}.
  4472. @end deffn
  4473. @deffn Command {stm32f1x options_read} num
  4474. Read and display the stm32 option bytes written by
  4475. the @command{stm32f1x options_write} command.
  4476. The @var{num} parameter is a value shown by @command{flash banks}.
  4477. @end deffn
  4478. @deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
  4479. Writes the stm32 option byte with the specified values.
  4480. The @var{num} parameter is a value shown by @command{flash banks}.
  4481. @end deffn
  4482. @end deffn
  4483. @deffn {Flash Driver} stm32f2x
  4484. All members of the STM32F2 and STM32F4 microcontroller families from ST Microelectronics
  4485. include internal flash and use ARM Cortex-M3/M4 cores.
  4486. The driver automatically recognizes a number of these chips using
  4487. the chip identification register, and autoconfigures itself.
  4488. Note that some devices have been found that have a flash size register that contains
  4489. an invalid value, to workaround this issue you can override the probed value used by
  4490. the flash driver.
  4491. @example
  4492. flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
  4493. @end example
  4494. Some stm32f2x-specific commands are defined:
  4495. @deffn Command {stm32f2x lock} num
  4496. Locks the entire stm32 device.
  4497. The @var{num} parameter is a value shown by @command{flash banks}.
  4498. @end deffn
  4499. @deffn Command {stm32f2x unlock} num
  4500. Unlocks the entire stm32 device.
  4501. The @var{num} parameter is a value shown by @command{flash banks}.
  4502. @end deffn
  4503. @end deffn
  4504. @deffn {Flash Driver} stm32lx
  4505. All members of the STM32L microcontroller families from ST Microelectronics
  4506. include internal flash and use ARM Cortex-M3 cores.
  4507. The driver automatically recognizes a number of these chips using
  4508. the chip identification register, and autoconfigures itself.
  4509. Note that some devices have been found that have a flash size register that contains
  4510. an invalid value, to workaround this issue you can override the probed value used by
  4511. the flash driver.
  4512. @example
  4513. flash bank $_FLASHNAME stm32lx 0 0x20000 0 0 $_TARGETNAME
  4514. @end example
  4515. @end deffn
  4516. @deffn {Flash Driver} str7x
  4517. All members of the STR7 microcontroller family from ST Microelectronics
  4518. include internal flash and use ARM7TDMI cores.
  4519. The @var{str7x} driver defines one mandatory parameter, @var{variant},
  4520. which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
  4521. @example
  4522. flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
  4523. @end example
  4524. @deffn Command {str7x disable_jtag} bank
  4525. Activate the Debug/Readout protection mechanism
  4526. for the specified flash bank.
  4527. @end deffn
  4528. @end deffn
  4529. @deffn {Flash Driver} str9x
  4530. Most members of the STR9 microcontroller family from ST Microelectronics
  4531. include internal flash and use ARM966E cores.
  4532. The str9 needs the flash controller to be configured using
  4533. the @command{str9x flash_config} command prior to Flash programming.
  4534. @example
  4535. flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
  4536. str9x flash_config 0 4 2 0 0x80000
  4537. @end example
  4538. @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
  4539. Configures the str9 flash controller.
  4540. The @var{num} parameter is a value shown by @command{flash banks}.
  4541. @itemize @bullet
  4542. @item @var{bbsr} - Boot Bank Size register
  4543. @item @var{nbbsr} - Non Boot Bank Size register
  4544. @item @var{bbadr} - Boot Bank Start Address register
  4545. @item @var{nbbadr} - Boot Bank Start Address register
  4546. @end itemize
  4547. @end deffn
  4548. @end deffn
  4549. @deffn {Flash Driver} tms470
  4550. Most members of the TMS470 microcontroller family from Texas Instruments
  4551. include internal flash and use ARM7TDMI cores.
  4552. This driver doesn't require the chip and bus width to be specified.
  4553. Some tms470-specific commands are defined:
  4554. @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
  4555. Saves programming keys in a register, to enable flash erase and write commands.
  4556. @end deffn
  4557. @deffn Command {tms470 osc_mhz} clock_mhz
  4558. Reports the clock speed, which is used to calculate timings.
  4559. @end deffn
  4560. @deffn Command {tms470 plldis} (0|1)
  4561. Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
  4562. the flash clock.
  4563. @end deffn
  4564. @end deffn
  4565. @deffn {Flash Driver} virtual
  4566. This is a special driver that maps a previously defined bank to another
  4567. address. All bank settings will be copied from the master physical bank.
  4568. The @var{virtual} driver defines one mandatory parameters,
  4569. @itemize
  4570. @item @var{master_bank} The bank that this virtual address refers to.
  4571. @end itemize
  4572. So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
  4573. the flash bank defined at address 0x1fc00000. Any cmds executed on
  4574. the virtual banks are actually performed on the physical banks.
  4575. @example
  4576. flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
  4577. flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
  4578. flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
  4579. @end example
  4580. @end deffn
  4581. @deffn {Flash Driver} fm3
  4582. All members of the FM3 microcontroller family from Fujitsu
  4583. include internal flash and use ARM Cortex M3 cores.
  4584. The @var{fm3} driver uses the @var{target} parameter to select the
  4585. correct bank config, it can currently be one of the following:
  4586. @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
  4587. @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
  4588. @example
  4589. flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
  4590. @end example
  4591. @end deffn
  4592. @subsection str9xpec driver
  4593. @cindex str9xpec
  4594. Here is some background info to help
  4595. you better understand how this driver works. OpenOCD has two flash drivers for
  4596. the str9:
  4597. @enumerate
  4598. @item
  4599. Standard driver @option{str9x} programmed via the str9 core. Normally used for
  4600. flash programming as it is faster than the @option{str9xpec} driver.
  4601. @item
  4602. Direct programming @option{str9xpec} using the flash controller. This is an
  4603. ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
  4604. core does not need to be running to program using this flash driver. Typical use
  4605. for this driver is locking/unlocking the target and programming the option bytes.
  4606. @end enumerate
  4607. Before we run any commands using the @option{str9xpec} driver we must first disable
  4608. the str9 core. This example assumes the @option{str9xpec} driver has been
  4609. configured for flash bank 0.
  4610. @example
  4611. # assert srst, we do not want core running
  4612. # while accessing str9xpec flash driver
  4613. jtag_reset 0 1
  4614. # turn off target polling
  4615. poll off
  4616. # disable str9 core
  4617. str9xpec enable_turbo 0
  4618. # read option bytes
  4619. str9xpec options_read 0
  4620. # re-enable str9 core
  4621. str9xpec disable_turbo 0
  4622. poll on
  4623. reset halt
  4624. @end example
  4625. The above example will read the str9 option bytes.
  4626. When performing a unlock remember that you will not be able to halt the str9 - it
  4627. has been locked. Halting the core is not required for the @option{str9xpec} driver
  4628. as mentioned above, just issue the commands above manually or from a telnet prompt.
  4629. @deffn {Flash Driver} str9xpec
  4630. Only use this driver for locking/unlocking the device or configuring the option bytes.
  4631. Use the standard str9 driver for programming.
  4632. Before using the flash commands the turbo mode must be enabled using the
  4633. @command{str9xpec enable_turbo} command.
  4634. Several str9xpec-specific commands are defined:
  4635. @deffn Command {str9xpec disable_turbo} num
  4636. Restore the str9 into JTAG chain.
  4637. @end deffn
  4638. @deffn Command {str9xpec enable_turbo} num
  4639. Enable turbo mode, will simply remove the str9 from the chain and talk
  4640. directly to the embedded flash controller.
  4641. @end deffn
  4642. @deffn Command {str9xpec lock} num
  4643. Lock str9 device. The str9 will only respond to an unlock command that will
  4644. erase the device.
  4645. @end deffn
  4646. @deffn Command {str9xpec part_id} num
  4647. Prints the part identifier for bank @var{num}.
  4648. @end deffn
  4649. @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
  4650. Configure str9 boot bank.
  4651. @end deffn
  4652. @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
  4653. Configure str9 lvd source.
  4654. @end deffn
  4655. @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
  4656. Configure str9 lvd threshold.
  4657. @end deffn
  4658. @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
  4659. Configure str9 lvd reset warning source.
  4660. @end deffn
  4661. @deffn Command {str9xpec options_read} num
  4662. Read str9 option bytes.
  4663. @end deffn
  4664. @deffn Command {str9xpec options_write} num
  4665. Write str9 option bytes.
  4666. @end deffn
  4667. @deffn Command {str9xpec unlock} num
  4668. unlock str9 device.
  4669. @end deffn
  4670. @end deffn
  4671. @section mFlash
  4672. @subsection mFlash Configuration
  4673. @cindex mFlash Configuration
  4674. @deffn {Config Command} {mflash bank} soc base RST_pin target
  4675. Configures a mflash for @var{soc} host bank at
  4676. address @var{base}.
  4677. The pin number format depends on the host GPIO naming convention.
  4678. Currently, the mflash driver supports s3c2440 and pxa270.
  4679. Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
  4680. @example
  4681. mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
  4682. @end example
  4683. Example for pxa270 mflash where @var{RST pin} is GPIO 43:
  4684. @example
  4685. mflash bank $_FLASHNAME pxa270 0x08000000 43 0
  4686. @end example
  4687. @end deffn
  4688. @subsection mFlash commands
  4689. @cindex mFlash commands
  4690. @deffn Command {mflash config pll} frequency
  4691. Configure mflash PLL.
  4692. The @var{frequency} is the mflash input frequency, in Hz.
  4693. Issuing this command will erase mflash's whole internal nand and write new pll.
  4694. After this command, mflash needs power-on-reset for normal operation.
  4695. If pll was newly configured, storage and boot(optional) info also need to be update.
  4696. @end deffn
  4697. @deffn Command {mflash config boot}
  4698. Configure bootable option.
  4699. If bootable option is set, mflash offer the first 8 sectors
  4700. (4kB) for boot.
  4701. @end deffn
  4702. @deffn Command {mflash config storage}
  4703. Configure storage information.
  4704. For the normal storage operation, this information must be
  4705. written.
  4706. @end deffn
  4707. @deffn Command {mflash dump} num filename offset size
  4708. Dump @var{size} bytes, starting at @var{offset} bytes from the
  4709. beginning of the bank @var{num}, to the file named @var{filename}.
  4710. @end deffn
  4711. @deffn Command {mflash probe}
  4712. Probe mflash.
  4713. @end deffn
  4714. @deffn Command {mflash write} num filename offset
  4715. Write the binary file @var{filename} to mflash bank @var{num}, starting at
  4716. @var{offset} bytes from the beginning of the bank.
  4717. @end deffn
  4718. @node Flash Programming
  4719. @chapter Flash Programming
  4720. OpenOCD implements numerous ways to program the target flash, whether internal or external.
  4721. Programming can be acheived by either using GDB @ref{programmingusinggdb,,Programming using GDB},
  4722. or using the cmds given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
  4723. @*To simplify using the flash cmds directly a jimtcl script is available that handles the programming and verify stage.
  4724. OpenOCD will program/verify/reset the target and shutdown.
  4725. The script is executed as follows and by default the following actions will be peformed.
  4726. @enumerate
  4727. @item 'init' is executed.
  4728. @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
  4729. @item @code{flash write_image} is called to erase and write any flash using the filename given.
  4730. @item @code{verify_image} is called if @option{verify} parameter is given.
  4731. @item @code{reset run} is called if @option{reset} parameter is given.
  4732. @item OpenOCD is shutdown.
  4733. @end enumerate
  4734. An example of usage is given below. @xref{program}.
  4735. @example
  4736. # program and verify using elf/hex/s19. verify and reset
  4737. # are optional parameters
  4738. openocd -f board/stm32f3discovery.cfg \
  4739. -c "program filename.elf verify reset"
  4740. # binary files need the flash address passing
  4741. openocd -f board/stm32f3discovery.cfg \
  4742. -c "program filename.bin 0x08000000"
  4743. @end example
  4744. @node NAND Flash Commands
  4745. @chapter NAND Flash Commands
  4746. @cindex NAND
  4747. Compared to NOR or SPI flash, NAND devices are inexpensive
  4748. and high density. Today's NAND chips, and multi-chip modules,
  4749. commonly hold multiple GigaBytes of data.
  4750. NAND chips consist of a number of ``erase blocks'' of a given
  4751. size (such as 128 KBytes), each of which is divided into a
  4752. number of pages (of perhaps 512 or 2048 bytes each). Each
  4753. page of a NAND flash has an ``out of band'' (OOB) area to hold
  4754. Error Correcting Code (ECC) and other metadata, usually 16 bytes
  4755. of OOB for every 512 bytes of page data.
  4756. One key characteristic of NAND flash is that its error rate
  4757. is higher than that of NOR flash. In normal operation, that
  4758. ECC is used to correct and detect errors. However, NAND
  4759. blocks can also wear out and become unusable; those blocks
  4760. are then marked "bad". NAND chips are even shipped from the
  4761. manufacturer with a few bad blocks. The highest density chips
  4762. use a technology (MLC) that wears out more quickly, so ECC
  4763. support is increasingly important as a way to detect blocks
  4764. that have begun to fail, and help to preserve data integrity
  4765. with techniques such as wear leveling.
  4766. Software is used to manage the ECC. Some controllers don't
  4767. support ECC directly; in those cases, software ECC is used.
  4768. Other controllers speed up the ECC calculations with hardware.
  4769. Single-bit error correction hardware is routine. Controllers
  4770. geared for newer MLC chips may correct 4 or more errors for
  4771. every 512 bytes of data.
  4772. You will need to make sure that any data you write using
  4773. OpenOCD includes the apppropriate kind of ECC. For example,
  4774. that may mean passing the @code{oob_softecc} flag when
  4775. writing NAND data, or ensuring that the correct hardware
  4776. ECC mode is used.
  4777. The basic steps for using NAND devices include:
  4778. @enumerate
  4779. @item Declare via the command @command{nand device}
  4780. @* Do this in a board-specific configuration file,
  4781. passing parameters as needed by the controller.
  4782. @item Configure each device using @command{nand probe}.
  4783. @* Do this only after the associated target is set up,
  4784. such as in its reset-init script or in procures defined
  4785. to access that device.
  4786. @item Operate on the flash via @command{nand subcommand}
  4787. @* Often commands to manipulate the flash are typed by a human, or run
  4788. via a script in some automated way. Common task include writing a
  4789. boot loader, operating system, or other data needed to initialize or
  4790. de-brick a board.
  4791. @end enumerate
  4792. @b{NOTE:} At the time this text was written, the largest NAND
  4793. flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
  4794. This is because the variables used to hold offsets and lengths
  4795. are only 32 bits wide.
  4796. (Larger chips may work in some cases, unless an offset or length
  4797. is larger than 0xffffffff, the largest 32-bit unsigned integer.)
  4798. Some larger devices will work, since they are actually multi-chip
  4799. modules with two smaller chips and individual chipselect lines.
  4800. @anchor{nandconfiguration}
  4801. @section NAND Configuration Commands
  4802. @cindex NAND configuration
  4803. NAND chips must be declared in configuration scripts,
  4804. plus some additional configuration that's done after
  4805. OpenOCD has initialized.
  4806. @deffn {Config Command} {nand device} name driver target [configparams...]
  4807. Declares a NAND device, which can be read and written to
  4808. after it has been configured through @command{nand probe}.
  4809. In OpenOCD, devices are single chips; this is unlike some
  4810. operating systems, which may manage multiple chips as if
  4811. they were a single (larger) device.
  4812. In some cases, configuring a device will activate extra
  4813. commands; see the controller-specific documentation.
  4814. @b{NOTE:} This command is not available after OpenOCD
  4815. initialization has completed. Use it in board specific
  4816. configuration files, not interactively.
  4817. @itemize @bullet
  4818. @item @var{name} ... may be used to reference the NAND bank
  4819. in most other NAND commands. A number is also available.
  4820. @item @var{driver} ... identifies the NAND controller driver
  4821. associated with the NAND device being declared.
  4822. @xref{nanddriverlist,,NAND Driver List}.
  4823. @item @var{target} ... names the target used when issuing
  4824. commands to the NAND controller.
  4825. @comment Actually, it's currently a controller-specific parameter...
  4826. @item @var{configparams} ... controllers may support, or require,
  4827. additional parameters. See the controller-specific documentation
  4828. for more information.
  4829. @end itemize
  4830. @end deffn
  4831. @deffn Command {nand list}
  4832. Prints a summary of each device declared
  4833. using @command{nand device}, numbered from zero.
  4834. Note that un-probed devices show no details.
  4835. @example
  4836. > nand list
  4837. #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
  4838. blocksize: 131072, blocks: 8192
  4839. #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
  4840. blocksize: 131072, blocks: 8192
  4841. >
  4842. @end example
  4843. @end deffn
  4844. @deffn Command {nand probe} num
  4845. Probes the specified device to determine key characteristics
  4846. like its page and block sizes, and how many blocks it has.
  4847. The @var{num} parameter is the value shown by @command{nand list}.
  4848. You must (successfully) probe a device before you can use
  4849. it with most other NAND commands.
  4850. @end deffn
  4851. @section Erasing, Reading, Writing to NAND Flash
  4852. @deffn Command {nand dump} num filename offset length [oob_option]
  4853. @cindex NAND reading
  4854. Reads binary data from the NAND device and writes it to the file,
  4855. starting at the specified offset.
  4856. The @var{num} parameter is the value shown by @command{nand list}.
  4857. Use a complete path name for @var{filename}, so you don't depend
  4858. on the directory used to start the OpenOCD server.
  4859. The @var{offset} and @var{length} must be exact multiples of the
  4860. device's page size. They describe a data region; the OOB data
  4861. associated with each such page may also be accessed.
  4862. @b{NOTE:} At the time this text was written, no error correction
  4863. was done on the data that's read, unless raw access was disabled
  4864. and the underlying NAND controller driver had a @code{read_page}
  4865. method which handled that error correction.
  4866. By default, only page data is saved to the specified file.
  4867. Use an @var{oob_option} parameter to save OOB data:
  4868. @itemize @bullet
  4869. @item no oob_* parameter
  4870. @*Output file holds only page data; OOB is discarded.
  4871. @item @code{oob_raw}
  4872. @*Output file interleaves page data and OOB data;
  4873. the file will be longer than "length" by the size of the
  4874. spare areas associated with each data page.
  4875. Note that this kind of "raw" access is different from
  4876. what's implied by @command{nand raw_access}, which just
  4877. controls whether a hardware-aware access method is used.
  4878. @item @code{oob_only}
  4879. @*Output file has only raw OOB data, and will
  4880. be smaller than "length" since it will contain only the
  4881. spare areas associated with each data page.
  4882. @end itemize
  4883. @end deffn
  4884. @deffn Command {nand erase} num [offset length]
  4885. @cindex NAND erasing
  4886. @cindex NAND programming
  4887. Erases blocks on the specified NAND device, starting at the
  4888. specified @var{offset} and continuing for @var{length} bytes.
  4889. Both of those values must be exact multiples of the device's
  4890. block size, and the region they specify must fit entirely in the chip.
  4891. If those parameters are not specified,
  4892. the whole NAND chip will be erased.
  4893. The @var{num} parameter is the value shown by @command{nand list}.
  4894. @b{NOTE:} This command will try to erase bad blocks, when told
  4895. to do so, which will probably invalidate the manufacturer's bad
  4896. block marker.
  4897. For the remainder of the current server session, @command{nand info}
  4898. will still report that the block ``is'' bad.
  4899. @end deffn
  4900. @deffn Command {nand write} num filename offset [option...]
  4901. @cindex NAND writing
  4902. @cindex NAND programming
  4903. Writes binary data from the file into the specified NAND device,
  4904. starting at the specified offset. Those pages should already
  4905. have been erased; you can't change zero bits to one bits.
  4906. The @var{num} parameter is the value shown by @command{nand list}.
  4907. Use a complete path name for @var{filename}, so you don't depend
  4908. on the directory used to start the OpenOCD server.
  4909. The @var{offset} must be an exact multiple of the device's page size.
  4910. All data in the file will be written, assuming it doesn't run
  4911. past the end of the device.
  4912. Only full pages are written, and any extra space in the last
  4913. page will be filled with 0xff bytes. (That includes OOB data,
  4914. if that's being written.)
  4915. @b{NOTE:} At the time this text was written, bad blocks are
  4916. ignored. That is, this routine will not skip bad blocks,
  4917. but will instead try to write them. This can cause problems.
  4918. Provide at most one @var{option} parameter. With some
  4919. NAND drivers, the meanings of these parameters may change
  4920. if @command{nand raw_access} was used to disable hardware ECC.
  4921. @itemize @bullet
  4922. @item no oob_* parameter
  4923. @*File has only page data, which is written.
  4924. If raw acccess is in use, the OOB area will not be written.
  4925. Otherwise, if the underlying NAND controller driver has
  4926. a @code{write_page} routine, that routine may write the OOB
  4927. with hardware-computed ECC data.
  4928. @item @code{oob_only}
  4929. @*File has only raw OOB data, which is written to the OOB area.
  4930. Each page's data area stays untouched. @i{This can be a dangerous
  4931. option}, since it can invalidate the ECC data.
  4932. You may need to force raw access to use this mode.
  4933. @item @code{oob_raw}
  4934. @*File interleaves data and OOB data, both of which are written
  4935. If raw access is enabled, the data is written first, then the
  4936. un-altered OOB.
  4937. Otherwise, if the underlying NAND controller driver has
  4938. a @code{write_page} routine, that routine may modify the OOB
  4939. before it's written, to include hardware-computed ECC data.
  4940. @item @code{oob_softecc}
  4941. @*File has only page data, which is written.
  4942. The OOB area is filled with 0xff, except for a standard 1-bit
  4943. software ECC code stored in conventional locations.
  4944. You might need to force raw access to use this mode, to prevent
  4945. the underlying driver from applying hardware ECC.
  4946. @item @code{oob_softecc_kw}
  4947. @*File has only page data, which is written.
  4948. The OOB area is filled with 0xff, except for a 4-bit software ECC
  4949. specific to the boot ROM in Marvell Kirkwood SoCs.
  4950. You might need to force raw access to use this mode, to prevent
  4951. the underlying driver from applying hardware ECC.
  4952. @end itemize
  4953. @end deffn
  4954. @deffn Command {nand verify} num filename offset [option...]
  4955. @cindex NAND verification
  4956. @cindex NAND programming
  4957. Verify the binary data in the file has been programmed to the
  4958. specified NAND device, starting at the specified offset.
  4959. The @var{num} parameter is the value shown by @command{nand list}.
  4960. Use a complete path name for @var{filename}, so you don't depend
  4961. on the directory used to start the OpenOCD server.
  4962. The @var{offset} must be an exact multiple of the device's page size.
  4963. All data in the file will be read and compared to the contents of the
  4964. flash, assuming it doesn't run past the end of the device.
  4965. As with @command{nand write}, only full pages are verified, so any extra
  4966. space in the last page will be filled with 0xff bytes.
  4967. The same @var{options} accepted by @command{nand write},
  4968. and the file will be processed similarly to produce the buffers that
  4969. can be compared against the contents produced from @command{nand dump}.
  4970. @b{NOTE:} This will not work when the underlying NAND controller
  4971. driver's @code{write_page} routine must update the OOB with a
  4972. hardward-computed ECC before the data is written. This limitation may
  4973. be removed in a future release.
  4974. @end deffn
  4975. @section Other NAND commands
  4976. @cindex NAND other commands
  4977. @deffn Command {nand check_bad_blocks} num [offset length]
  4978. Checks for manufacturer bad block markers on the specified NAND
  4979. device. If no parameters are provided, checks the whole
  4980. device; otherwise, starts at the specified @var{offset} and
  4981. continues for @var{length} bytes.
  4982. Both of those values must be exact multiples of the device's
  4983. block size, and the region they specify must fit entirely in the chip.
  4984. The @var{num} parameter is the value shown by @command{nand list}.
  4985. @b{NOTE:} Before using this command you should force raw access
  4986. with @command{nand raw_access enable} to ensure that the underlying
  4987. driver will not try to apply hardware ECC.
  4988. @end deffn
  4989. @deffn Command {nand info} num
  4990. The @var{num} parameter is the value shown by @command{nand list}.
  4991. This prints the one-line summary from "nand list", plus for
  4992. devices which have been probed this also prints any known
  4993. status for each block.
  4994. @end deffn
  4995. @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
  4996. Sets or clears an flag affecting how page I/O is done.
  4997. The @var{num} parameter is the value shown by @command{nand list}.
  4998. This flag is cleared (disabled) by default, but changing that
  4999. value won't affect all NAND devices. The key factor is whether
  5000. the underlying driver provides @code{read_page} or @code{write_page}
  5001. methods. If it doesn't provide those methods, the setting of
  5002. this flag is irrelevant; all access is effectively ``raw''.
  5003. When those methods exist, they are normally used when reading
  5004. data (@command{nand dump} or reading bad block markers) or
  5005. writing it (@command{nand write}). However, enabling
  5006. raw access (setting the flag) prevents use of those methods,
  5007. bypassing hardware ECC logic.
  5008. @i{This can be a dangerous option}, since writing blocks
  5009. with the wrong ECC data can cause them to be marked as bad.
  5010. @end deffn
  5011. @anchor{nanddriverlist}
  5012. @section NAND Driver List
  5013. As noted above, the @command{nand device} command allows
  5014. driver-specific options and behaviors.
  5015. Some controllers also activate controller-specific commands.
  5016. @deffn {NAND Driver} at91sam9
  5017. This driver handles the NAND controllers found on AT91SAM9 family chips from
  5018. Atmel. It takes two extra parameters: address of the NAND chip;
  5019. address of the ECC controller.
  5020. @example
  5021. nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
  5022. @end example
  5023. AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
  5024. @code{read_page} methods are used to utilize the ECC hardware unless they are
  5025. disabled by using the @command{nand raw_access} command. There are four
  5026. additional commands that are needed to fully configure the AT91SAM9 NAND
  5027. controller. Two are optional; most boards use the same wiring for ALE/CLE:
  5028. @deffn Command {at91sam9 cle} num addr_line
  5029. Configure the address line used for latching commands. The @var{num}
  5030. parameter is the value shown by @command{nand list}.
  5031. @end deffn
  5032. @deffn Command {at91sam9 ale} num addr_line
  5033. Configure the address line used for latching addresses. The @var{num}
  5034. parameter is the value shown by @command{nand list}.
  5035. @end deffn
  5036. For the next two commands, it is assumed that the pins have already been
  5037. properly configured for input or output.
  5038. @deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
  5039. Configure the RDY/nBUSY input from the NAND device. The @var{num}
  5040. parameter is the value shown by @command{nand list}. @var{pio_base_addr}
  5041. is the base address of the PIO controller and @var{pin} is the pin number.
  5042. @end deffn
  5043. @deffn Command {at91sam9 ce} num pio_base_addr pin
  5044. Configure the chip enable input to the NAND device. The @var{num}
  5045. parameter is the value shown by @command{nand list}. @var{pio_base_addr}
  5046. is the base address of the PIO controller and @var{pin} is the pin number.
  5047. @end deffn
  5048. @end deffn
  5049. @deffn {NAND Driver} davinci
  5050. This driver handles the NAND controllers found on DaVinci family
  5051. chips from Texas Instruments.
  5052. It takes three extra parameters:
  5053. address of the NAND chip;
  5054. hardware ECC mode to use (@option{hwecc1},
  5055. @option{hwecc4}, @option{hwecc4_infix});
  5056. address of the AEMIF controller on this processor.
  5057. @example
  5058. nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
  5059. @end example
  5060. All DaVinci processors support the single-bit ECC hardware,
  5061. and newer ones also support the four-bit ECC hardware.
  5062. The @code{write_page} and @code{read_page} methods are used
  5063. to implement those ECC modes, unless they are disabled using
  5064. the @command{nand raw_access} command.
  5065. @end deffn
  5066. @deffn {NAND Driver} lpc3180
  5067. These controllers require an extra @command{nand device}
  5068. parameter: the clock rate used by the controller.
  5069. @deffn Command {lpc3180 select} num [mlc|slc]
  5070. Configures use of the MLC or SLC controller mode.
  5071. MLC implies use of hardware ECC.
  5072. The @var{num} parameter is the value shown by @command{nand list}.
  5073. @end deffn
  5074. At this writing, this driver includes @code{write_page}
  5075. and @code{read_page} methods. Using @command{nand raw_access}
  5076. to disable those methods will prevent use of hardware ECC
  5077. in the MLC controller mode, but won't change SLC behavior.
  5078. @end deffn
  5079. @comment current lpc3180 code won't issue 5-byte address cycles
  5080. @deffn {NAND Driver} mx3
  5081. This driver handles the NAND controller in i.MX31. The mxc driver
  5082. should work for this chip aswell.
  5083. @end deffn
  5084. @deffn {NAND Driver} mxc
  5085. This driver handles the NAND controller found in Freescale i.MX
  5086. chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
  5087. The driver takes 3 extra arguments, chip (@option{mx27},
  5088. @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
  5089. and optionally if bad block information should be swapped between
  5090. main area and spare area (@option{biswap}), defaults to off.
  5091. @example
  5092. nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
  5093. @end example
  5094. @deffn Command {mxc biswap} bank_num [enable|disable]
  5095. Turns on/off bad block information swaping from main area,
  5096. without parameter query status.
  5097. @end deffn
  5098. @end deffn
  5099. @deffn {NAND Driver} orion
  5100. These controllers require an extra @command{nand device}
  5101. parameter: the address of the controller.
  5102. @example
  5103. nand device orion 0xd8000000
  5104. @end example
  5105. These controllers don't define any specialized commands.
  5106. At this writing, their drivers don't include @code{write_page}
  5107. or @code{read_page} methods, so @command{nand raw_access} won't
  5108. change any behavior.
  5109. @end deffn
  5110. @deffn {NAND Driver} s3c2410
  5111. @deffnx {NAND Driver} s3c2412
  5112. @deffnx {NAND Driver} s3c2440
  5113. @deffnx {NAND Driver} s3c2443
  5114. @deffnx {NAND Driver} s3c6400
  5115. These S3C family controllers don't have any special
  5116. @command{nand device} options, and don't define any
  5117. specialized commands.
  5118. At this writing, their drivers don't include @code{write_page}
  5119. or @code{read_page} methods, so @command{nand raw_access} won't
  5120. change any behavior.
  5121. @end deffn
  5122. @node PLD/FPGA Commands
  5123. @chapter PLD/FPGA Commands
  5124. @cindex PLD
  5125. @cindex FPGA
  5126. Programmable Logic Devices (PLDs) and the more flexible
  5127. Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
  5128. OpenOCD can support programming them.
  5129. Although PLDs are generally restrictive (cells are less functional, and
  5130. there are no special purpose cells for memory or computational tasks),
  5131. they share the same OpenOCD infrastructure.
  5132. Accordingly, both are called PLDs here.
  5133. @section PLD/FPGA Configuration and Commands
  5134. As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
  5135. OpenOCD maintains a list of PLDs available for use in various commands.
  5136. Also, each such PLD requires a driver.
  5137. They are referenced by the number shown by the @command{pld devices} command,
  5138. and new PLDs are defined by @command{pld device driver_name}.
  5139. @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
  5140. Defines a new PLD device, supported by driver @var{driver_name},
  5141. using the TAP named @var{tap_name}.
  5142. The driver may make use of any @var{driver_options} to configure its
  5143. behavior.
  5144. @end deffn
  5145. @deffn {Command} {pld devices}
  5146. Lists the PLDs and their numbers.
  5147. @end deffn
  5148. @deffn {Command} {pld load} num filename
  5149. Loads the file @file{filename} into the PLD identified by @var{num}.
  5150. The file format must be inferred by the driver.
  5151. @end deffn
  5152. @section PLD/FPGA Drivers, Options, and Commands
  5153. Drivers may support PLD-specific options to the @command{pld device}
  5154. definition command, and may also define commands usable only with
  5155. that particular type of PLD.
  5156. @deffn {FPGA Driver} virtex2
  5157. Virtex-II is a family of FPGAs sold by Xilinx.
  5158. It supports the IEEE 1532 standard for In-System Configuration (ISC).
  5159. No driver-specific PLD definition options are used,
  5160. and one driver-specific command is defined.
  5161. @deffn {Command} {virtex2 read_stat} num
  5162. Reads and displays the Virtex-II status register (STAT)
  5163. for FPGA @var{num}.
  5164. @end deffn
  5165. @end deffn
  5166. @node General Commands
  5167. @chapter General Commands
  5168. @cindex commands
  5169. The commands documented in this chapter here are common commands that
  5170. you, as a human, may want to type and see the output of. Configuration type
  5171. commands are documented elsewhere.
  5172. Intent:
  5173. @itemize @bullet
  5174. @item @b{Source Of Commands}
  5175. @* OpenOCD commands can occur in a configuration script (discussed
  5176. elsewhere) or typed manually by a human or supplied programatically,
  5177. or via one of several TCP/IP Ports.
  5178. @item @b{From the human}
  5179. @* A human should interact with the telnet interface (default port: 4444)
  5180. or via GDB (default port 3333).
  5181. To issue commands from within a GDB session, use the @option{monitor}
  5182. command, e.g. use @option{monitor poll} to issue the @option{poll}
  5183. command. All output is relayed through the GDB session.
  5184. @item @b{Machine Interface}
  5185. The Tcl interface's intent is to be a machine interface. The default Tcl
  5186. port is 5555.
  5187. @end itemize
  5188. @section Daemon Commands
  5189. @deffn {Command} exit
  5190. Exits the current telnet session.
  5191. @end deffn
  5192. @deffn {Command} help [string]
  5193. With no parameters, prints help text for all commands.
  5194. Otherwise, prints each helptext containing @var{string}.
  5195. Not every command provides helptext.
  5196. Configuration commands, and commands valid at any time, are
  5197. explicitly noted in parenthesis.
  5198. In most cases, no such restriction is listed; this indicates commands
  5199. which are only available after the configuration stage has completed.
  5200. @end deffn
  5201. @deffn Command sleep msec [@option{busy}]
  5202. Wait for at least @var{msec} milliseconds before resuming.
  5203. If @option{busy} is passed, busy-wait instead of sleeping.
  5204. (This option is strongly discouraged.)
  5205. Useful in connection with script files
  5206. (@command{script} command and @command{target_name} configuration).
  5207. @end deffn
  5208. @deffn Command shutdown
  5209. Close the OpenOCD daemon, disconnecting all clients (GDB, telnet, other).
  5210. @end deffn
  5211. @anchor{debuglevel}
  5212. @deffn Command debug_level [n]
  5213. @cindex message level
  5214. Display debug level.
  5215. If @var{n} (from 0..3) is provided, then set it to that level.
  5216. This affects the kind of messages sent to the server log.
  5217. Level 0 is error messages only;
  5218. level 1 adds warnings;
  5219. level 2 adds informational messages;
  5220. and level 3 adds debugging messages.
  5221. The default is level 2, but that can be overridden on
  5222. the command line along with the location of that log
  5223. file (which is normally the server's standard output).
  5224. @xref{Running}.
  5225. @end deffn
  5226. @deffn Command echo [-n] message
  5227. Logs a message at "user" priority.
  5228. Output @var{message} to stdout.
  5229. Option "-n" suppresses trailing newline.
  5230. @example
  5231. echo "Downloading kernel -- please wait"
  5232. @end example
  5233. @end deffn
  5234. @deffn Command log_output [filename]
  5235. Redirect logging to @var{filename};
  5236. the initial log output channel is stderr.
  5237. @end deffn
  5238. @deffn Command add_script_search_dir [directory]
  5239. Add @var{directory} to the file/script search path.
  5240. @end deffn
  5241. @anchor{targetstatehandling}
  5242. @section Target State handling
  5243. @cindex reset
  5244. @cindex halt
  5245. @cindex target initialization
  5246. In this section ``target'' refers to a CPU configured as
  5247. shown earlier (@pxref{CPU Configuration}).
  5248. These commands, like many, implicitly refer to
  5249. a current target which is used to perform the
  5250. various operations. The current target may be changed
  5251. by using @command{targets} command with the name of the
  5252. target which should become current.
  5253. @deffn Command reg [(number|name) [value]]
  5254. Access a single register by @var{number} or by its @var{name}.
  5255. The target must generally be halted before access to CPU core
  5256. registers is allowed. Depending on the hardware, some other
  5257. registers may be accessible while the target is running.
  5258. @emph{With no arguments}:
  5259. list all available registers for the current target,
  5260. showing number, name, size, value, and cache status.
  5261. For valid entries, a value is shown; valid entries
  5262. which are also dirty (and will be written back later)
  5263. are flagged as such.
  5264. @emph{With number/name}: display that register's value.
  5265. @emph{With both number/name and value}: set register's value.
  5266. Writes may be held in a writeback cache internal to OpenOCD,
  5267. so that setting the value marks the register as dirty instead
  5268. of immediately flushing that value. Resuming CPU execution
  5269. (including by single stepping) or otherwise activating the
  5270. relevant module will flush such values.
  5271. Cores may have surprisingly many registers in their
  5272. Debug and trace infrastructure:
  5273. @example
  5274. > reg
  5275. ===== ARM registers
  5276. (0) r0 (/32): 0x0000D3C2 (dirty)
  5277. (1) r1 (/32): 0xFD61F31C
  5278. (2) r2 (/32)
  5279. ...
  5280. (164) ETM_contextid_comparator_mask (/32)
  5281. >
  5282. @end example
  5283. @end deffn
  5284. @deffn Command halt [ms]
  5285. @deffnx Command wait_halt [ms]
  5286. The @command{halt} command first sends a halt request to the target,
  5287. which @command{wait_halt} doesn't.
  5288. Otherwise these behave the same: wait up to @var{ms} milliseconds,
  5289. or 5 seconds if there is no parameter, for the target to halt
  5290. (and enter debug mode).
  5291. Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
  5292. @quotation Warning
  5293. On ARM cores, software using the @emph{wait for interrupt} operation
  5294. often blocks the JTAG access needed by a @command{halt} command.
  5295. This is because that operation also puts the core into a low
  5296. power mode by gating the core clock;
  5297. but the core clock is needed to detect JTAG clock transitions.
  5298. One partial workaround uses adaptive clocking: when the core is
  5299. interrupted the operation completes, then JTAG clocks are accepted
  5300. at least until the interrupt handler completes.
  5301. However, this workaround is often unusable since the processor, board,
  5302. and JTAG adapter must all support adaptive JTAG clocking.
  5303. Also, it can't work until an interrupt is issued.
  5304. A more complete workaround is to not use that operation while you
  5305. work with a JTAG debugger.
  5306. Tasking environments generaly have idle loops where the body is the
  5307. @emph{wait for interrupt} operation.
  5308. (On older cores, it is a coprocessor action;
  5309. newer cores have a @option{wfi} instruction.)
  5310. Such loops can just remove that operation, at the cost of higher
  5311. power consumption (because the CPU is needlessly clocked).
  5312. @end quotation
  5313. @end deffn
  5314. @deffn Command resume [address]
  5315. Resume the target at its current code position,
  5316. or the optional @var{address} if it is provided.
  5317. OpenOCD will wait 5 seconds for the target to resume.
  5318. @end deffn
  5319. @deffn Command step [address]
  5320. Single-step the target at its current code position,
  5321. or the optional @var{address} if it is provided.
  5322. @end deffn
  5323. @anchor{resetcommand}
  5324. @deffn Command reset
  5325. @deffnx Command {reset run}
  5326. @deffnx Command {reset halt}
  5327. @deffnx Command {reset init}
  5328. Perform as hard a reset as possible, using SRST if possible.
  5329. @emph{All defined targets will be reset, and target
  5330. events will fire during the reset sequence.}
  5331. The optional parameter specifies what should
  5332. happen after the reset.
  5333. If there is no parameter, a @command{reset run} is executed.
  5334. The other options will not work on all systems.
  5335. @xref{Reset Configuration}.
  5336. @itemize @minus
  5337. @item @b{run} Let the target run
  5338. @item @b{halt} Immediately halt the target
  5339. @item @b{init} Immediately halt the target, and execute the reset-init script
  5340. @end itemize
  5341. @end deffn
  5342. @deffn Command soft_reset_halt
  5343. Requesting target halt and executing a soft reset. This is often used
  5344. when a target cannot be reset and halted. The target, after reset is
  5345. released begins to execute code. OpenOCD attempts to stop the CPU and
  5346. then sets the program counter back to the reset vector. Unfortunately
  5347. the code that was executed may have left the hardware in an unknown
  5348. state.
  5349. @end deffn
  5350. @section I/O Utilities
  5351. These commands are available when
  5352. OpenOCD is built with @option{--enable-ioutil}.
  5353. They are mainly useful on embedded targets,
  5354. notably the ZY1000.
  5355. Hosts with operating systems have complementary tools.
  5356. @emph{Note:} there are several more such commands.
  5357. @deffn Command append_file filename [string]*
  5358. Appends the @var{string} parameters to
  5359. the text file @file{filename}.
  5360. Each string except the last one is followed by one space.
  5361. The last string is followed by a newline.
  5362. @end deffn
  5363. @deffn Command cat filename
  5364. Reads and displays the text file @file{filename}.
  5365. @end deffn
  5366. @deffn Command cp src_filename dest_filename
  5367. Copies contents from the file @file{src_filename}
  5368. into @file{dest_filename}.
  5369. @end deffn
  5370. @deffn Command ip
  5371. @emph{No description provided.}
  5372. @end deffn
  5373. @deffn Command ls
  5374. @emph{No description provided.}
  5375. @end deffn
  5376. @deffn Command mac
  5377. @emph{No description provided.}
  5378. @end deffn
  5379. @deffn Command meminfo
  5380. Display available RAM memory on OpenOCD host.
  5381. Used in OpenOCD regression testing scripts.
  5382. @end deffn
  5383. @deffn Command peek
  5384. @emph{No description provided.}
  5385. @end deffn
  5386. @deffn Command poke
  5387. @emph{No description provided.}
  5388. @end deffn
  5389. @deffn Command rm filename
  5390. @c "rm" has both normal and Jim-level versions??
  5391. Unlinks the file @file{filename}.
  5392. @end deffn
  5393. @deffn Command trunc filename
  5394. Removes all data in the file @file{filename}.
  5395. @end deffn
  5396. @anchor{memoryaccess}
  5397. @section Memory access commands
  5398. @cindex memory access
  5399. These commands allow accesses of a specific size to the memory
  5400. system. Often these are used to configure the current target in some
  5401. special way. For example - one may need to write certain values to the
  5402. SDRAM controller to enable SDRAM.
  5403. @enumerate
  5404. @item Use the @command{targets} (plural) command
  5405. to change the current target.
  5406. @item In system level scripts these commands are deprecated.
  5407. Please use their TARGET object siblings to avoid making assumptions
  5408. about what TAP is the current target, or about MMU configuration.
  5409. @end enumerate
  5410. @deffn Command mdw [phys] addr [count]
  5411. @deffnx Command mdh [phys] addr [count]
  5412. @deffnx Command mdb [phys] addr [count]
  5413. Display contents of address @var{addr}, as
  5414. 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
  5415. or 8-bit bytes (@command{mdb}).
  5416. When the current target has an MMU which is present and active,
  5417. @var{addr} is interpreted as a virtual address.
  5418. Otherwise, or if the optional @var{phys} flag is specified,
  5419. @var{addr} is interpreted as a physical address.
  5420. If @var{count} is specified, displays that many units.
  5421. (If you want to manipulate the data instead of displaying it,
  5422. see the @code{mem2array} primitives.)
  5423. @end deffn
  5424. @deffn Command mww [phys] addr word
  5425. @deffnx Command mwh [phys] addr halfword
  5426. @deffnx Command mwb [phys] addr byte
  5427. Writes the specified @var{word} (32 bits),
  5428. @var{halfword} (16 bits), or @var{byte} (8-bit) value,
  5429. at the specified address @var{addr}.
  5430. When the current target has an MMU which is present and active,
  5431. @var{addr} is interpreted as a virtual address.
  5432. Otherwise, or if the optional @var{phys} flag is specified,
  5433. @var{addr} is interpreted as a physical address.
  5434. @end deffn
  5435. @anchor{imageaccess}
  5436. @section Image loading commands
  5437. @cindex image loading
  5438. @cindex image dumping
  5439. @deffn Command {dump_image} filename address size
  5440. Dump @var{size} bytes of target memory starting at @var{address} to the
  5441. binary file named @var{filename}.
  5442. @end deffn
  5443. @deffn Command {fast_load}
  5444. Loads an image stored in memory by @command{fast_load_image} to the
  5445. current target. Must be preceeded by fast_load_image.
  5446. @end deffn
  5447. @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
  5448. Normally you should be using @command{load_image} or GDB load. However, for
  5449. testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
  5450. host), storing the image in memory and uploading the image to the target
  5451. can be a way to upload e.g. multiple debug sessions when the binary does not change.
  5452. Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
  5453. memory, i.e. does not affect target. This approach is also useful when profiling
  5454. target programming performance as I/O and target programming can easily be profiled
  5455. separately.
  5456. @end deffn
  5457. @deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
  5458. Load image from file @var{filename} to target memory offset by @var{address} from its load address.
  5459. The file format may optionally be specified
  5460. (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
  5461. In addition the following arguments may be specifed:
  5462. @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
  5463. @var{max_length} - maximum number of bytes to load.
  5464. @example
  5465. proc load_image_bin @{fname foffset address length @} @{
  5466. # Load data from fname filename at foffset offset to
  5467. # target at address. Load at most length bytes.
  5468. load_image $fname [expr $address - $foffset] bin $address $length
  5469. @}
  5470. @end example
  5471. @end deffn
  5472. @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
  5473. Displays image section sizes and addresses
  5474. as if @var{filename} were loaded into target memory
  5475. starting at @var{address} (defaults to zero).
  5476. The file format may optionally be specified
  5477. (@option{bin}, @option{ihex}, or @option{elf})
  5478. @end deffn
  5479. @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
  5480. Verify @var{filename} against target memory starting at @var{address}.
  5481. The file format may optionally be specified
  5482. (@option{bin}, @option{ihex}, or @option{elf})
  5483. This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
  5484. @end deffn
  5485. @section Breakpoint and Watchpoint commands
  5486. @cindex breakpoint
  5487. @cindex watchpoint
  5488. CPUs often make debug modules accessible through JTAG, with
  5489. hardware support for a handful of code breakpoints and data
  5490. watchpoints.
  5491. In addition, CPUs almost always support software breakpoints.
  5492. @deffn Command {bp} [address len [@option{hw}]]
  5493. With no parameters, lists all active breakpoints.
  5494. Else sets a breakpoint on code execution starting
  5495. at @var{address} for @var{length} bytes.
  5496. This is a software breakpoint, unless @option{hw} is specified
  5497. in which case it will be a hardware breakpoint.
  5498. (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
  5499. for similar mechanisms that do not consume hardware breakpoints.)
  5500. @end deffn
  5501. @deffn Command {rbp} address
  5502. Remove the breakpoint at @var{address}.
  5503. @end deffn
  5504. @deffn Command {rwp} address
  5505. Remove data watchpoint on @var{address}
  5506. @end deffn
  5507. @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
  5508. With no parameters, lists all active watchpoints.
  5509. Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
  5510. The watch point is an "access" watchpoint unless
  5511. the @option{r} or @option{w} parameter is provided,
  5512. defining it as respectively a read or write watchpoint.
  5513. If a @var{value} is provided, that value is used when determining if
  5514. the watchpoint should trigger. The value may be first be masked
  5515. using @var{mask} to mark ``don't care'' fields.
  5516. @end deffn
  5517. @section Misc Commands
  5518. @cindex profiling
  5519. @deffn Command {profile} seconds filename
  5520. Profiling samples the CPU's program counter as quickly as possible,
  5521. which is useful for non-intrusive stochastic profiling.
  5522. Saves up to 10000 sampines in @file{filename} using ``gmon.out'' format.
  5523. @end deffn
  5524. @deffn Command {version}
  5525. Displays a string identifying the version of this OpenOCD server.
  5526. @end deffn
  5527. @deffn Command {virt2phys} virtual_address
  5528. Requests the current target to map the specified @var{virtual_address}
  5529. to its corresponding physical address, and displays the result.
  5530. @end deffn
  5531. @node Architecture and Core Commands
  5532. @chapter Architecture and Core Commands
  5533. @cindex Architecture Specific Commands
  5534. @cindex Core Specific Commands
  5535. Most CPUs have specialized JTAG operations to support debugging.
  5536. OpenOCD packages most such operations in its standard command framework.
  5537. Some of those operations don't fit well in that framework, so they are
  5538. exposed here as architecture or implementation (core) specific commands.
  5539. @anchor{armhardwaretracing}
  5540. @section ARM Hardware Tracing
  5541. @cindex tracing
  5542. @cindex ETM
  5543. @cindex ETB
  5544. CPUs based on ARM cores may include standard tracing interfaces,
  5545. based on an ``Embedded Trace Module'' (ETM) which sends voluminous
  5546. address and data bus trace records to a ``Trace Port''.
  5547. @itemize
  5548. @item
  5549. Development-oriented boards will sometimes provide a high speed
  5550. trace connector for collecting that data, when the particular CPU
  5551. supports such an interface.
  5552. (The standard connector is a 38-pin Mictor, with both JTAG
  5553. and trace port support.)
  5554. Those trace connectors are supported by higher end JTAG adapters
  5555. and some logic analyzer modules; frequently those modules can
  5556. buffer several megabytes of trace data.
  5557. Configuring an ETM coupled to such an external trace port belongs
  5558. in the board-specific configuration file.
  5559. @item
  5560. If the CPU doesn't provide an external interface, it probably
  5561. has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
  5562. dedicated SRAM. 4KBytes is one common ETB size.
  5563. Configuring an ETM coupled only to an ETB belongs in the CPU-specific
  5564. (target) configuration file, since it works the same on all boards.
  5565. @end itemize
  5566. ETM support in OpenOCD doesn't seem to be widely used yet.
  5567. @quotation Issues
  5568. ETM support may be buggy, and at least some @command{etm config}
  5569. parameters should be detected by asking the ETM for them.
  5570. ETM trigger events could also implement a kind of complex
  5571. hardware breakpoint, much more powerful than the simple
  5572. watchpoint hardware exported by EmbeddedICE modules.
  5573. @emph{Such breakpoints can be triggered even when using the
  5574. dummy trace port driver}.
  5575. It seems like a GDB hookup should be possible,
  5576. as well as tracing only during specific states
  5577. (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
  5578. There should be GUI tools to manipulate saved trace data and help
  5579. analyse it in conjunction with the source code.
  5580. It's unclear how much of a common interface is shared
  5581. with the current XScale trace support, or should be
  5582. shared with eventual Nexus-style trace module support.
  5583. At this writing (November 2009) only ARM7, ARM9, and ARM11 support
  5584. for ETM modules is available. The code should be able to
  5585. work with some newer cores; but not all of them support
  5586. this original style of JTAG access.
  5587. @end quotation
  5588. @subsection ETM Configuration
  5589. ETM setup is coupled with the trace port driver configuration.
  5590. @deffn {Config Command} {etm config} target width mode clocking driver
  5591. Declares the ETM associated with @var{target}, and associates it
  5592. with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
  5593. Several of the parameters must reflect the trace port capabilities,
  5594. which are a function of silicon capabilties (exposed later
  5595. using @command{etm info}) and of what hardware is connected to
  5596. that port (such as an external pod, or ETB).
  5597. The @var{width} must be either 4, 8, or 16,
  5598. except with ETMv3.0 and newer modules which may also
  5599. support 1, 2, 24, 32, 48, and 64 bit widths.
  5600. (With those versions, @command{etm info} also shows whether
  5601. the selected port width and mode are supported.)
  5602. The @var{mode} must be @option{normal}, @option{multiplexed},
  5603. or @option{demultiplexed}.
  5604. The @var{clocking} must be @option{half} or @option{full}.
  5605. @quotation Warning
  5606. With ETMv3.0 and newer, the bits set with the @var{mode} and
  5607. @var{clocking} parameters both control the mode.
  5608. This modified mode does not map to the values supported by
  5609. previous ETM modules, so this syntax is subject to change.
  5610. @end quotation
  5611. @quotation Note
  5612. You can see the ETM registers using the @command{reg} command.
  5613. Not all possible registers are present in every ETM.
  5614. Most of the registers are write-only, and are used to configure
  5615. what CPU activities are traced.
  5616. @end quotation
  5617. @end deffn
  5618. @deffn Command {etm info}
  5619. Displays information about the current target's ETM.
  5620. This includes resource counts from the @code{ETM_CONFIG} register,
  5621. as well as silicon capabilities (except on rather old modules).
  5622. from the @code{ETM_SYS_CONFIG} register.
  5623. @end deffn
  5624. @deffn Command {etm status}
  5625. Displays status of the current target's ETM and trace port driver:
  5626. is the ETM idle, or is it collecting data?
  5627. Did trace data overflow?
  5628. Was it triggered?
  5629. @end deffn
  5630. @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
  5631. Displays what data that ETM will collect.
  5632. If arguments are provided, first configures that data.
  5633. When the configuration changes, tracing is stopped
  5634. and any buffered trace data is invalidated.
  5635. @itemize
  5636. @item @var{type} ... describing how data accesses are traced,
  5637. when they pass any ViewData filtering that that was set up.
  5638. The value is one of
  5639. @option{none} (save nothing),
  5640. @option{data} (save data),
  5641. @option{address} (save addresses),
  5642. @option{all} (save data and addresses)
  5643. @item @var{context_id_bits} ... 0, 8, 16, or 32
  5644. @item @var{cycle_accurate} ... @option{enable} or @option{disable}
  5645. cycle-accurate instruction tracing.
  5646. Before ETMv3, enabling this causes much extra data to be recorded.
  5647. @item @var{branch_output} ... @option{enable} or @option{disable}.
  5648. Disable this unless you need to try reconstructing the instruction
  5649. trace stream without an image of the code.
  5650. @end itemize
  5651. @end deffn
  5652. @deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
  5653. Displays whether ETM triggering debug entry (like a breakpoint) is
  5654. enabled or disabled, after optionally modifying that configuration.
  5655. The default behaviour is @option{disable}.
  5656. Any change takes effect after the next @command{etm start}.
  5657. By using script commands to configure ETM registers, you can make the
  5658. processor enter debug state automatically when certain conditions,
  5659. more complex than supported by the breakpoint hardware, happen.
  5660. @end deffn
  5661. @subsection ETM Trace Operation
  5662. After setting up the ETM, you can use it to collect data.
  5663. That data can be exported to files for later analysis.
  5664. It can also be parsed with OpenOCD, for basic sanity checking.
  5665. To configure what is being traced, you will need to write
  5666. various trace registers using @command{reg ETM_*} commands.
  5667. For the definitions of these registers, read ARM publication
  5668. @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
  5669. Be aware that most of the relevant registers are write-only,
  5670. and that ETM resources are limited. There are only a handful
  5671. of address comparators, data comparators, counters, and so on.
  5672. Examples of scenarios you might arrange to trace include:
  5673. @itemize
  5674. @item Code flow within a function, @emph{excluding} subroutines
  5675. it calls. Use address range comparators to enable tracing
  5676. for instruction access within that function's body.
  5677. @item Code flow within a function, @emph{including} subroutines
  5678. it calls. Use the sequencer and address comparators to activate
  5679. tracing on an ``entered function'' state, then deactivate it by
  5680. exiting that state when the function's exit code is invoked.
  5681. @item Code flow starting at the fifth invocation of a function,
  5682. combining one of the above models with a counter.
  5683. @item CPU data accesses to the registers for a particular device,
  5684. using address range comparators and the ViewData logic.
  5685. @item Such data accesses only during IRQ handling, combining the above
  5686. model with sequencer triggers which on entry and exit to the IRQ handler.
  5687. @item @emph{... more}
  5688. @end itemize
  5689. At this writing, September 2009, there are no Tcl utility
  5690. procedures to help set up any common tracing scenarios.
  5691. @deffn Command {etm analyze}
  5692. Reads trace data into memory, if it wasn't already present.
  5693. Decodes and prints the data that was collected.
  5694. @end deffn
  5695. @deffn Command {etm dump} filename
  5696. Stores the captured trace data in @file{filename}.
  5697. @end deffn
  5698. @deffn Command {etm image} filename [base_address] [type]
  5699. Opens an image file.
  5700. @end deffn
  5701. @deffn Command {etm load} filename
  5702. Loads captured trace data from @file{filename}.
  5703. @end deffn
  5704. @deffn Command {etm start}
  5705. Starts trace data collection.
  5706. @end deffn
  5707. @deffn Command {etm stop}
  5708. Stops trace data collection.
  5709. @end deffn
  5710. @anchor{traceportdrivers}
  5711. @subsection Trace Port Drivers
  5712. To use an ETM trace port it must be associated with a driver.
  5713. @deffn {Trace Port Driver} dummy
  5714. Use the @option{dummy} driver if you are configuring an ETM that's
  5715. not connected to anything (on-chip ETB or off-chip trace connector).
  5716. @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
  5717. any trace data collection.}
  5718. @deffn {Config Command} {etm_dummy config} target
  5719. Associates the ETM for @var{target} with a dummy driver.
  5720. @end deffn
  5721. @end deffn
  5722. @deffn {Trace Port Driver} etb
  5723. Use the @option{etb} driver if you are configuring an ETM
  5724. to use on-chip ETB memory.
  5725. @deffn {Config Command} {etb config} target etb_tap
  5726. Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
  5727. You can see the ETB registers using the @command{reg} command.
  5728. @end deffn
  5729. @deffn Command {etb trigger_percent} [percent]
  5730. This displays, or optionally changes, ETB behavior after the
  5731. ETM's configured @emph{trigger} event fires.
  5732. It controls how much more trace data is saved after the (single)
  5733. trace trigger becomes active.
  5734. @itemize
  5735. @item The default corresponds to @emph{trace around} usage,
  5736. recording 50 percent data before the event and the rest
  5737. afterwards.
  5738. @item The minimum value of @var{percent} is 2 percent,
  5739. recording almost exclusively data before the trigger.
  5740. Such extreme @emph{trace before} usage can help figure out
  5741. what caused that event to happen.
  5742. @item The maximum value of @var{percent} is 100 percent,
  5743. recording data almost exclusively after the event.
  5744. This extreme @emph{trace after} usage might help sort out
  5745. how the event caused trouble.
  5746. @end itemize
  5747. @c REVISIT allow "break" too -- enter debug mode.
  5748. @end deffn
  5749. @end deffn
  5750. @deffn {Trace Port Driver} oocd_trace
  5751. This driver isn't available unless OpenOCD was explicitly configured
  5752. with the @option{--enable-oocd_trace} option. You probably don't want
  5753. to configure it unless you've built the appropriate prototype hardware;
  5754. it's @emph{proof-of-concept} software.
  5755. Use the @option{oocd_trace} driver if you are configuring an ETM that's
  5756. connected to an off-chip trace connector.
  5757. @deffn {Config Command} {oocd_trace config} target tty
  5758. Associates the ETM for @var{target} with a trace driver which
  5759. collects data through the serial port @var{tty}.
  5760. @end deffn
  5761. @deffn Command {oocd_trace resync}
  5762. Re-synchronizes with the capture clock.
  5763. @end deffn
  5764. @deffn Command {oocd_trace status}
  5765. Reports whether the capture clock is locked or not.
  5766. @end deffn
  5767. @end deffn
  5768. @section Generic ARM
  5769. @cindex ARM
  5770. These commands should be available on all ARM processors.
  5771. They are available in addition to other core-specific
  5772. commands that may be available.
  5773. @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
  5774. Displays the core_state, optionally changing it to process
  5775. either @option{arm} or @option{thumb} instructions.
  5776. The target may later be resumed in the currently set core_state.
  5777. (Processors may also support the Jazelle state, but
  5778. that is not currently supported in OpenOCD.)
  5779. @end deffn
  5780. @deffn Command {arm disassemble} address [count [@option{thumb}]]
  5781. @cindex disassemble
  5782. Disassembles @var{count} instructions starting at @var{address}.
  5783. If @var{count} is not specified, a single instruction is disassembled.
  5784. If @option{thumb} is specified, or the low bit of the address is set,
  5785. Thumb2 (mixed 16/32-bit) instructions are used;
  5786. else ARM (32-bit) instructions are used.
  5787. (Processors may also support the Jazelle state, but
  5788. those instructions are not currently understood by OpenOCD.)
  5789. Note that all Thumb instructions are Thumb2 instructions,
  5790. so older processors (without Thumb2 support) will still
  5791. see correct disassembly of Thumb code.
  5792. Also, ThumbEE opcodes are the same as Thumb2,
  5793. with a handful of exceptions.
  5794. ThumbEE disassembly currently has no explicit support.
  5795. @end deffn
  5796. @deffn Command {arm mcr} pX op1 CRn CRm op2 value
  5797. Write @var{value} to a coprocessor @var{pX} register
  5798. passing parameters @var{CRn},
  5799. @var{CRm}, opcodes @var{opc1} and @var{opc2},
  5800. and using the MCR instruction.
  5801. (Parameter sequence matches the ARM instruction, but omits
  5802. an ARM register.)
  5803. @end deffn
  5804. @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
  5805. Read a coprocessor @var{pX} register passing parameters @var{CRn},
  5806. @var{CRm}, opcodes @var{opc1} and @var{opc2},
  5807. and the MRC instruction.
  5808. Returns the result so it can be manipulated by Jim scripts.
  5809. (Parameter sequence matches the ARM instruction, but omits
  5810. an ARM register.)
  5811. @end deffn
  5812. @deffn Command {arm reg}
  5813. Display a table of all banked core registers, fetching the current value from every
  5814. core mode if necessary.
  5815. @end deffn
  5816. @deffn Command {arm semihosting} [@option{enable}|@option{disable}]
  5817. @cindex ARM semihosting
  5818. Display status of semihosting, after optionally changing that status.
  5819. Semihosting allows for code executing on an ARM target to use the
  5820. I/O facilities on the host computer i.e. the system where OpenOCD
  5821. is running. The target application must be linked against a library
  5822. implementing the ARM semihosting convention that forwards operation
  5823. requests by using a special SVC instruction that is trapped at the
  5824. Supervisor Call vector by OpenOCD.
  5825. @end deffn
  5826. @section ARMv4 and ARMv5 Architecture
  5827. @cindex ARMv4
  5828. @cindex ARMv5
  5829. The ARMv4 and ARMv5 architectures are widely used in embedded systems,
  5830. and introduced core parts of the instruction set in use today.
  5831. That includes the Thumb instruction set, introduced in the ARMv4T
  5832. variant.
  5833. @subsection ARM7 and ARM9 specific commands
  5834. @cindex ARM7
  5835. @cindex ARM9
  5836. These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
  5837. ARM9TDMI, ARM920T or ARM926EJ-S.
  5838. They are available in addition to the ARM commands,
  5839. and any other core-specific commands that may be available.
  5840. @deffn Command {arm7_9 dbgrq} [@option{enable}|@option{disable}]
  5841. Displays the value of the flag controlling use of the
  5842. the EmbeddedIce DBGRQ signal to force entry into debug mode,
  5843. instead of breakpoints.
  5844. If a boolean parameter is provided, first assigns that flag.
  5845. This should be
  5846. safe for all but ARM7TDMI-S cores (like NXP LPC).
  5847. This feature is enabled by default on most ARM9 cores,
  5848. including ARM9TDMI, ARM920T, and ARM926EJ-S.
  5849. @end deffn
  5850. @deffn Command {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
  5851. @cindex DCC
  5852. Displays the value of the flag controlling use of the debug communications
  5853. channel (DCC) to write larger (>128 byte) amounts of memory.
  5854. If a boolean parameter is provided, first assigns that flag.
  5855. DCC downloads offer a huge speed increase, but might be
  5856. unsafe, especially with targets running at very low speeds. This command was introduced
  5857. with OpenOCD rev. 60, and requires a few bytes of working area.
  5858. @end deffn
  5859. @deffn Command {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
  5860. Displays the value of the flag controlling use of memory writes and reads
  5861. that don't check completion of the operation.
  5862. If a boolean parameter is provided, first assigns that flag.
  5863. This provides a huge speed increase, especially with USB JTAG
  5864. cables (FT2232), but might be unsafe if used with targets running at very low
  5865. speeds, like the 32kHz startup clock of an AT91RM9200.
  5866. @end deffn
  5867. @subsection ARM720T specific commands
  5868. @cindex ARM720T
  5869. These commands are available to ARM720T based CPUs,
  5870. which are implementations of the ARMv4T architecture
  5871. based on the ARM7TDMI-S integer core.
  5872. They are available in addition to the ARM and ARM7/ARM9 commands.
  5873. @deffn Command {arm720t cp15} opcode [value]
  5874. @emph{DEPRECATED -- avoid using this.
  5875. Use the @command{arm mrc} or @command{arm mcr} commands instead.}
  5876. Display cp15 register returned by the ARM instruction @var{opcode};
  5877. else if a @var{value} is provided, that value is written to that register.
  5878. The @var{opcode} should be the value of either an MRC or MCR instruction.
  5879. @end deffn
  5880. @subsection ARM9 specific commands
  5881. @cindex ARM9
  5882. ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
  5883. integer processors.
  5884. Such cores include the ARM920T, ARM926EJ-S, and ARM966.
  5885. @c 9-june-2009: tried this on arm920t, it didn't work.
  5886. @c no-params always lists nothing caught, and that's how it acts.
  5887. @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
  5888. @c versions have different rules about when they commit writes.
  5889. @anchor{arm9vectorcatch}
  5890. @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
  5891. @cindex vector_catch
  5892. Vector Catch hardware provides a sort of dedicated breakpoint
  5893. for hardware events such as reset, interrupt, and abort.
  5894. You can use this to conserve normal breakpoint resources,
  5895. so long as you're not concerned with code that branches directly
  5896. to those hardware vectors.
  5897. This always finishes by listing the current configuration.
  5898. If parameters are provided, it first reconfigures the
  5899. vector catch hardware to intercept
  5900. @option{all} of the hardware vectors,
  5901. @option{none} of them,
  5902. or a list with one or more of the following:
  5903. @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
  5904. @option{irq} @option{fiq}.
  5905. @end deffn
  5906. @subsection ARM920T specific commands
  5907. @cindex ARM920T
  5908. These commands are available to ARM920T based CPUs,
  5909. which are implementations of the ARMv4T architecture
  5910. built using the ARM9TDMI integer core.
  5911. They are available in addition to the ARM, ARM7/ARM9,
  5912. and ARM9 commands.
  5913. @deffn Command {arm920t cache_info}
  5914. Print information about the caches found. This allows to see whether your target
  5915. is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
  5916. @end deffn
  5917. @deffn Command {arm920t cp15} regnum [value]
  5918. Display cp15 register @var{regnum};
  5919. else if a @var{value} is provided, that value is written to that register.
  5920. This uses "physical access" and the register number is as
  5921. shown in bits 38..33 of table 9-9 in the ARM920T TRM.
  5922. (Not all registers can be written.)
  5923. @end deffn
  5924. @deffn Command {arm920t cp15i} opcode [value [address]]
  5925. @emph{DEPRECATED -- avoid using this.
  5926. Use the @command{arm mrc} or @command{arm mcr} commands instead.}
  5927. Interpreted access using ARM instruction @var{opcode}, which should
  5928. be the value of either an MRC or MCR instruction
  5929. (as shown tables 9-11, 9-12, and 9-13 in the ARM920T TRM).
  5930. If no @var{value} is provided, the result is displayed.
  5931. Else if that value is written using the specified @var{address},
  5932. or using zero if no other address is provided.
  5933. @end deffn
  5934. @deffn Command {arm920t read_cache} filename
  5935. Dump the content of ICache and DCache to a file named @file{filename}.
  5936. @end deffn
  5937. @deffn Command {arm920t read_mmu} filename
  5938. Dump the content of the ITLB and DTLB to a file named @file{filename}.
  5939. @end deffn
  5940. @subsection ARM926ej-s specific commands
  5941. @cindex ARM926ej-s
  5942. These commands are available to ARM926ej-s based CPUs,
  5943. which are implementations of the ARMv5TEJ architecture
  5944. based on the ARM9EJ-S integer core.
  5945. They are available in addition to the ARM, ARM7/ARM9,
  5946. and ARM9 commands.
  5947. The Feroceon cores also support these commands, although
  5948. they are not built from ARM926ej-s designs.
  5949. @deffn Command {arm926ejs cache_info}
  5950. Print information about the caches found.
  5951. @end deffn
  5952. @subsection ARM966E specific commands
  5953. @cindex ARM966E
  5954. These commands are available to ARM966 based CPUs,
  5955. which are implementations of the ARMv5TE architecture.
  5956. They are available in addition to the ARM, ARM7/ARM9,
  5957. and ARM9 commands.
  5958. @deffn Command {arm966e cp15} regnum [value]
  5959. Display cp15 register @var{regnum};
  5960. else if a @var{value} is provided, that value is written to that register.
  5961. The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
  5962. ARM966E-S TRM.
  5963. There is no current control over bits 31..30 from that table,
  5964. as required for BIST support.
  5965. @end deffn
  5966. @subsection XScale specific commands
  5967. @cindex XScale
  5968. Some notes about the debug implementation on the XScale CPUs:
  5969. The XScale CPU provides a special debug-only mini-instruction cache
  5970. (mini-IC) in which exception vectors and target-resident debug handler
  5971. code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
  5972. must point vector 0 (the reset vector) to the entry of the debug
  5973. handler. However, this means that the complete first cacheline in the
  5974. mini-IC is marked valid, which makes the CPU fetch all exception
  5975. handlers from the mini-IC, ignoring the code in RAM.
  5976. To address this situation, OpenOCD provides the @code{xscale
  5977. vector_table} command, which allows the user to explicity write
  5978. individual entries to either the high or low vector table stored in
  5979. the mini-IC.
  5980. It is recommended to place a pc-relative indirect branch in the vector
  5981. table, and put the branch destination somewhere in memory. Doing so
  5982. makes sure the code in the vector table stays constant regardless of
  5983. code layout in memory:
  5984. @example
  5985. _vectors:
  5986. ldr pc,[pc,#0x100-8]
  5987. ldr pc,[pc,#0x100-8]
  5988. ldr pc,[pc,#0x100-8]
  5989. ldr pc,[pc,#0x100-8]
  5990. ldr pc,[pc,#0x100-8]
  5991. ldr pc,[pc,#0x100-8]
  5992. ldr pc,[pc,#0x100-8]
  5993. ldr pc,[pc,#0x100-8]
  5994. .org 0x100
  5995. .long real_reset_vector
  5996. .long real_ui_handler
  5997. .long real_swi_handler
  5998. .long real_pf_abort
  5999. .long real_data_abort
  6000. .long 0 /* unused */
  6001. .long real_irq_handler
  6002. .long real_fiq_handler
  6003. @end example
  6004. Alternatively, you may choose to keep some or all of the mini-IC
  6005. vector table entries synced with those written to memory by your
  6006. system software. The mini-IC can not be modified while the processor
  6007. is executing, but for each vector table entry not previously defined
  6008. using the @code{xscale vector_table} command, OpenOCD will copy the
  6009. value from memory to the mini-IC every time execution resumes from a
  6010. halt. This is done for both high and low vector tables (although the
  6011. table not in use may not be mapped to valid memory, and in this case
  6012. that copy operation will silently fail). This means that you will
  6013. need to briefly halt execution at some strategic point during system
  6014. start-up; e.g., after the software has initialized the vector table,
  6015. but before exceptions are enabled. A breakpoint can be used to
  6016. accomplish this once the appropriate location in the start-up code has
  6017. been identified. A watchpoint over the vector table region is helpful
  6018. in finding the location if you're not sure. Note that the same
  6019. situation exists any time the vector table is modified by the system
  6020. software.
  6021. The debug handler must be placed somewhere in the address space using
  6022. the @code{xscale debug_handler} command. The allowed locations for the
  6023. debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
  6024. 0xfffff800). The default value is 0xfe000800.
  6025. XScale has resources to support two hardware breakpoints and two
  6026. watchpoints. However, the following restrictions on watchpoint
  6027. functionality apply: (1) the value and mask arguments to the @code{wp}
  6028. command are not supported, (2) the watchpoint length must be a
  6029. power of two and not less than four, and can not be greater than the
  6030. watchpoint address, and (3) a watchpoint with a length greater than
  6031. four consumes all the watchpoint hardware resources. This means that
  6032. at any one time, you can have enabled either two watchpoints with a
  6033. length of four, or one watchpoint with a length greater than four.
  6034. These commands are available to XScale based CPUs,
  6035. which are implementations of the ARMv5TE architecture.
  6036. @deffn Command {xscale analyze_trace}
  6037. Displays the contents of the trace buffer.
  6038. @end deffn
  6039. @deffn Command {xscale cache_clean_address} address
  6040. Changes the address used when cleaning the data cache.
  6041. @end deffn
  6042. @deffn Command {xscale cache_info}
  6043. Displays information about the CPU caches.
  6044. @end deffn
  6045. @deffn Command {xscale cp15} regnum [value]
  6046. Display cp15 register @var{regnum};
  6047. else if a @var{value} is provided, that value is written to that register.
  6048. @end deffn
  6049. @deffn Command {xscale debug_handler} target address
  6050. Changes the address used for the specified target's debug handler.
  6051. @end deffn
  6052. @deffn Command {xscale dcache} [@option{enable}|@option{disable}]
  6053. Enables or disable the CPU's data cache.
  6054. @end deffn
  6055. @deffn Command {xscale dump_trace} filename
  6056. Dumps the raw contents of the trace buffer to @file{filename}.
  6057. @end deffn
  6058. @deffn Command {xscale icache} [@option{enable}|@option{disable}]
  6059. Enables or disable the CPU's instruction cache.
  6060. @end deffn
  6061. @deffn Command {xscale mmu} [@option{enable}|@option{disable}]
  6062. Enables or disable the CPU's memory management unit.
  6063. @end deffn
  6064. @deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
  6065. Displays the trace buffer status, after optionally
  6066. enabling or disabling the trace buffer
  6067. and modifying how it is emptied.
  6068. @end deffn
  6069. @deffn Command {xscale trace_image} filename [offset [type]]
  6070. Opens a trace image from @file{filename}, optionally rebasing
  6071. its segment addresses by @var{offset}.
  6072. The image @var{type} may be one of
  6073. @option{bin} (binary), @option{ihex} (Intel hex),
  6074. @option{elf} (ELF file), @option{s19} (Motorola s19),
  6075. @option{mem}, or @option{builder}.
  6076. @end deffn
  6077. @anchor{xscalevectorcatch}
  6078. @deffn Command {xscale vector_catch} [mask]
  6079. @cindex vector_catch
  6080. Display a bitmask showing the hardware vectors to catch.
  6081. If the optional parameter is provided, first set the bitmask to that value.
  6082. The mask bits correspond with bit 16..23 in the DCSR:
  6083. @example
  6084. 0x01 Trap Reset
  6085. 0x02 Trap Undefined Instructions
  6086. 0x04 Trap Software Interrupt
  6087. 0x08 Trap Prefetch Abort
  6088. 0x10 Trap Data Abort
  6089. 0x20 reserved
  6090. 0x40 Trap IRQ
  6091. 0x80 Trap FIQ
  6092. @end example
  6093. @end deffn
  6094. @deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
  6095. @cindex vector_table
  6096. Set an entry in the mini-IC vector table. There are two tables: one for
  6097. low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
  6098. holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
  6099. points to the debug handler entry and can not be overwritten.
  6100. @var{value} holds the 32-bit opcode that is placed in the mini-IC.
  6101. Without arguments, the current settings are displayed.
  6102. @end deffn
  6103. @section ARMv6 Architecture
  6104. @cindex ARMv6
  6105. @subsection ARM11 specific commands
  6106. @cindex ARM11
  6107. @deffn Command {arm11 memwrite burst} [@option{enable}|@option{disable}]
  6108. Displays the value of the memwrite burst-enable flag,
  6109. which is enabled by default.
  6110. If a boolean parameter is provided, first assigns that flag.
  6111. Burst writes are only used for memory writes larger than 1 word.
  6112. They improve performance by assuming that the CPU has read each data
  6113. word over JTAG and completed its write before the next word arrives,
  6114. instead of polling for a status flag to verify that completion.
  6115. This is usually safe, because JTAG runs much slower than the CPU.
  6116. @end deffn
  6117. @deffn Command {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
  6118. Displays the value of the memwrite error_fatal flag,
  6119. which is enabled by default.
  6120. If a boolean parameter is provided, first assigns that flag.
  6121. When set, certain memory write errors cause earlier transfer termination.
  6122. @end deffn
  6123. @deffn Command {arm11 step_irq_enable} [@option{enable}|@option{disable}]
  6124. Displays the value of the flag controlling whether
  6125. IRQs are enabled during single stepping;
  6126. they are disabled by default.
  6127. If a boolean parameter is provided, first assigns that.
  6128. @end deffn
  6129. @deffn Command {arm11 vcr} [value]
  6130. @cindex vector_catch
  6131. Displays the value of the @emph{Vector Catch Register (VCR)},
  6132. coprocessor 14 register 7.
  6133. If @var{value} is defined, first assigns that.
  6134. Vector Catch hardware provides dedicated breakpoints
  6135. for certain hardware events.
  6136. The specific bit values are core-specific (as in fact is using
  6137. coprocessor 14 register 7 itself) but all current ARM11
  6138. cores @emph{except the ARM1176} use the same six bits.
  6139. @end deffn
  6140. @section ARMv7 Architecture
  6141. @cindex ARMv7
  6142. @subsection ARMv7 Debug Access Port (DAP) specific commands
  6143. @cindex Debug Access Port
  6144. @cindex DAP
  6145. These commands are specific to ARM architecture v7 Debug Access Port (DAP),
  6146. included on Cortex-M3 and Cortex-A8 systems.
  6147. They are available in addition to other core-specific commands that may be available.
  6148. @deffn Command {dap apid} [num]
  6149. Displays ID register from AP @var{num},
  6150. defaulting to the currently selected AP.
  6151. @end deffn
  6152. @deffn Command {dap apsel} [num]
  6153. Select AP @var{num}, defaulting to 0.
  6154. @end deffn
  6155. @deffn Command {dap baseaddr} [num]
  6156. Displays debug base address from MEM-AP @var{num},
  6157. defaulting to the currently selected AP.
  6158. @end deffn
  6159. @deffn Command {dap info} [num]
  6160. Displays the ROM table for MEM-AP @var{num},
  6161. defaulting to the currently selected AP.
  6162. @end deffn
  6163. @deffn Command {dap memaccess} [value]
  6164. Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
  6165. memory bus access [0-255], giving additional time to respond to reads.
  6166. If @var{value} is defined, first assigns that.
  6167. @end deffn
  6168. @deffn Command {dap apcsw} [0 / 1]
  6169. fix CSW_SPROT from register AP_REG_CSW on selected dap.
  6170. Defaulting to 0.
  6171. @end deffn
  6172. @subsection Cortex-M3 specific commands
  6173. @cindex Cortex-M3
  6174. @deffn Command {cortex_m3 maskisr} (@option{auto}|@option{on}|@option{off})
  6175. Control masking (disabling) interrupts during target step/resume.
  6176. The @option{auto} option handles interrupts during stepping a way they get
  6177. served but don't disturb the program flow. The step command first allows
  6178. pending interrupt handlers to execute, then disables interrupts and steps over
  6179. the next instruction where the core was halted. After the step interrupts
  6180. are enabled again. If the interrupt handlers don't complete within 500ms,
  6181. the step command leaves with the core running.
  6182. Note that a free breakpoint is required for the @option{auto} option. If no
  6183. breakpoint is available at the time of the step, then the step is taken
  6184. with interrupts enabled, i.e. the same way the @option{off} option does.
  6185. Default is @option{auto}.
  6186. @end deffn
  6187. @deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
  6188. @cindex vector_catch
  6189. Vector Catch hardware provides dedicated breakpoints
  6190. for certain hardware events.
  6191. Parameters request interception of
  6192. @option{all} of these hardware event vectors,
  6193. @option{none} of them,
  6194. or one or more of the following:
  6195. @option{hard_err} for a HardFault exception;
  6196. @option{mm_err} for a MemManage exception;
  6197. @option{bus_err} for a BusFault exception;
  6198. @option{irq_err},
  6199. @option{state_err},
  6200. @option{chk_err}, or
  6201. @option{nocp_err} for various UsageFault exceptions; or
  6202. @option{reset}.
  6203. If NVIC setup code does not enable them,
  6204. MemManage, BusFault, and UsageFault exceptions
  6205. are mapped to HardFault.
  6206. UsageFault checks for
  6207. divide-by-zero and unaligned access
  6208. must also be explicitly enabled.
  6209. This finishes by listing the current vector catch configuration.
  6210. @end deffn
  6211. @deffn Command {cortex_m3 reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
  6212. Control reset handling. The default @option{srst} is to use srst if fitted,
  6213. otherwise fallback to @option{vectreset}.
  6214. @itemize @minus
  6215. @item @option{srst} use hardware srst if fitted otherwise fallback to @option{vectreset}.
  6216. @item @option{sysresetreq} use NVIC SYSRESETREQ to reset system.
  6217. @item @option{vectreset} use NVIC VECTRESET to reset system.
  6218. @end itemize
  6219. Using @option{vectreset} is a safe option for all current Cortex-M3 cores.
  6220. This however has the disadvantage of only resetting the core, all peripherals
  6221. are uneffected. A solution would be to use a @code{reset-init} event handler to manually reset
  6222. the peripherals.
  6223. @xref{targetevents,,Target Events}.
  6224. @end deffn
  6225. @anchor{softwaredebugmessagesandtracing}
  6226. @section Software Debug Messages and Tracing
  6227. @cindex Linux-ARM DCC support
  6228. @cindex tracing
  6229. @cindex libdcc
  6230. @cindex DCC
  6231. OpenOCD can process certain requests from target software, when
  6232. the target uses appropriate libraries.
  6233. The most powerful mechanism is semihosting, but there is also
  6234. a lighter weight mechanism using only the DCC channel.
  6235. Currently @command{target_request debugmsgs}
  6236. is supported only for @option{arm7_9} and @option{cortex_m3} cores.
  6237. These messages are received as part of target polling, so
  6238. you need to have @command{poll on} active to receive them.
  6239. They are intrusive in that they will affect program execution
  6240. times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
  6241. See @file{libdcc} in the contrib dir for more details.
  6242. In addition to sending strings, characters, and
  6243. arrays of various size integers from the target,
  6244. @file{libdcc} also exports a software trace point mechanism.
  6245. The target being debugged may
  6246. issue trace messages which include a 24-bit @dfn{trace point} number.
  6247. Trace point support includes two distinct mechanisms,
  6248. each supported by a command:
  6249. @itemize
  6250. @item @emph{History} ... A circular buffer of trace points
  6251. can be set up, and then displayed at any time.
  6252. This tracks where code has been, which can be invaluable in
  6253. finding out how some fault was triggered.
  6254. The buffer may overflow, since it collects records continuously.
  6255. It may be useful to use some of the 24 bits to represent a
  6256. particular event, and other bits to hold data.
  6257. @item @emph{Counting} ... An array of counters can be set up,
  6258. and then displayed at any time.
  6259. This can help establish code coverage and identify hot spots.
  6260. The array of counters is directly indexed by the trace point
  6261. number, so trace points with higher numbers are not counted.
  6262. @end itemize
  6263. Linux-ARM kernels have a ``Kernel low-level debugging
  6264. via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
  6265. depends on CONFIG_DEBUG_LL) which uses this mechanism to
  6266. deliver messages before a serial console can be activated.
  6267. This is not the same format used by @file{libdcc}.
  6268. Other software, such as the U-Boot boot loader, sometimes
  6269. does the same thing.
  6270. @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
  6271. Displays current handling of target DCC message requests.
  6272. These messages may be sent to the debugger while the target is running.
  6273. The optional @option{enable} and @option{charmsg} parameters
  6274. both enable the messages, while @option{disable} disables them.
  6275. With @option{charmsg} the DCC words each contain one character,
  6276. as used by Linux with CONFIG_DEBUG_ICEDCC;
  6277. otherwise the libdcc format is used.
  6278. @end deffn
  6279. @deffn Command {trace history} [@option{clear}|count]
  6280. With no parameter, displays all the trace points that have triggered
  6281. in the order they triggered.
  6282. With the parameter @option{clear}, erases all current trace history records.
  6283. With a @var{count} parameter, allocates space for that many
  6284. history records.
  6285. @end deffn
  6286. @deffn Command {trace point} [@option{clear}|identifier]
  6287. With no parameter, displays all trace point identifiers and how many times
  6288. they have been triggered.
  6289. With the parameter @option{clear}, erases all current trace point counters.
  6290. With a numeric @var{identifier} parameter, creates a new a trace point counter
  6291. and associates it with that identifier.
  6292. @emph{Important:} The identifier and the trace point number
  6293. are not related except by this command.
  6294. These trace point numbers always start at zero (from server startup,
  6295. or after @command{trace point clear}) and count up from there.
  6296. @end deffn
  6297. @node JTAG Commands
  6298. @chapter JTAG Commands
  6299. @cindex JTAG Commands
  6300. Most general purpose JTAG commands have been presented earlier.
  6301. (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
  6302. Lower level JTAG commands, as presented here,
  6303. may be needed to work with targets which require special
  6304. attention during operations such as reset or initialization.
  6305. To use these commands you will need to understand some
  6306. of the basics of JTAG, including:
  6307. @itemize @bullet
  6308. @item A JTAG scan chain consists of a sequence of individual TAP
  6309. devices such as a CPUs.
  6310. @item Control operations involve moving each TAP through the same
  6311. standard state machine (in parallel)
  6312. using their shared TMS and clock signals.
  6313. @item Data transfer involves shifting data through the chain of
  6314. instruction or data registers of each TAP, writing new register values
  6315. while the reading previous ones.
  6316. @item Data register sizes are a function of the instruction active in
  6317. a given TAP, while instruction register sizes are fixed for each TAP.
  6318. All TAPs support a BYPASS instruction with a single bit data register.
  6319. @item The way OpenOCD differentiates between TAP devices is by
  6320. shifting different instructions into (and out of) their instruction
  6321. registers.
  6322. @end itemize
  6323. @section Low Level JTAG Commands
  6324. These commands are used by developers who need to access
  6325. JTAG instruction or data registers, possibly controlling
  6326. the order of TAP state transitions.
  6327. If you're not debugging OpenOCD internals, or bringing up a
  6328. new JTAG adapter or a new type of TAP device (like a CPU or
  6329. JTAG router), you probably won't need to use these commands.
  6330. In a debug session that doesn't use JTAG for its transport protocol,
  6331. these commands are not available.
  6332. @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
  6333. Loads the data register of @var{tap} with a series of bit fields
  6334. that specify the entire register.
  6335. Each field is @var{numbits} bits long with
  6336. a numeric @var{value} (hexadecimal encouraged).
  6337. The return value holds the original value of each
  6338. of those fields.
  6339. For example, a 38 bit number might be specified as one
  6340. field of 32 bits then one of 6 bits.
  6341. @emph{For portability, never pass fields which are more
  6342. than 32 bits long. Many OpenOCD implementations do not
  6343. support 64-bit (or larger) integer values.}
  6344. All TAPs other than @var{tap} must be in BYPASS mode.
  6345. The single bit in their data registers does not matter.
  6346. When @var{tap_state} is specified, the JTAG state machine is left
  6347. in that state.
  6348. For example @sc{drpause} might be specified, so that more
  6349. instructions can be issued before re-entering the @sc{run/idle} state.
  6350. If the end state is not specified, the @sc{run/idle} state is entered.
  6351. @quotation Warning
  6352. OpenOCD does not record information about data register lengths,
  6353. so @emph{it is important that you get the bit field lengths right}.
  6354. Remember that different JTAG instructions refer to different
  6355. data registers, which may have different lengths.
  6356. Moreover, those lengths may not be fixed;
  6357. the SCAN_N instruction can change the length of
  6358. the register accessed by the INTEST instruction
  6359. (by connecting a different scan chain).
  6360. @end quotation
  6361. @end deffn
  6362. @deffn Command {flush_count}
  6363. Returns the number of times the JTAG queue has been flushed.
  6364. This may be used for performance tuning.
  6365. For example, flushing a queue over USB involves a
  6366. minimum latency, often several milliseconds, which does
  6367. not change with the amount of data which is written.
  6368. You may be able to identify performance problems by finding
  6369. tasks which waste bandwidth by flushing small transfers too often,
  6370. instead of batching them into larger operations.
  6371. @end deffn
  6372. @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
  6373. For each @var{tap} listed, loads the instruction register
  6374. with its associated numeric @var{instruction}.
  6375. (The number of bits in that instruction may be displayed
  6376. using the @command{scan_chain} command.)
  6377. For other TAPs, a BYPASS instruction is loaded.
  6378. When @var{tap_state} is specified, the JTAG state machine is left
  6379. in that state.
  6380. For example @sc{irpause} might be specified, so the data register
  6381. can be loaded before re-entering the @sc{run/idle} state.
  6382. If the end state is not specified, the @sc{run/idle} state is entered.
  6383. @quotation Note
  6384. OpenOCD currently supports only a single field for instruction
  6385. register values, unlike data register values.
  6386. For TAPs where the instruction register length is more than 32 bits,
  6387. portable scripts currently must issue only BYPASS instructions.
  6388. @end quotation
  6389. @end deffn
  6390. @deffn Command {jtag_reset} trst srst
  6391. Set values of reset signals.
  6392. The @var{trst} and @var{srst} parameter values may be
  6393. @option{0}, indicating that reset is inactive (pulled or driven high),
  6394. or @option{1}, indicating it is active (pulled or driven low).
  6395. The @command{reset_config} command should already have been used
  6396. to configure how the board and JTAG adapter treat these two
  6397. signals, and to say if either signal is even present.
  6398. @xref{Reset Configuration}.
  6399. Note that TRST is specially handled.
  6400. It actually signifies JTAG's @sc{reset} state.
  6401. So if the board doesn't support the optional TRST signal,
  6402. or it doesn't support it along with the specified SRST value,
  6403. JTAG reset is triggered with TMS and TCK signals
  6404. instead of the TRST signal.
  6405. And no matter how that JTAG reset is triggered, once
  6406. the scan chain enters @sc{reset} with TRST inactive,
  6407. TAP @code{post-reset} events are delivered to all TAPs
  6408. with handlers for that event.
  6409. @end deffn
  6410. @deffn Command {pathmove} start_state [next_state ...]
  6411. Start by moving to @var{start_state}, which
  6412. must be one of the @emph{stable} states.
  6413. Unless it is the only state given, this will often be the
  6414. current state, so that no TCK transitions are needed.
  6415. Then, in a series of single state transitions
  6416. (conforming to the JTAG state machine) shift to
  6417. each @var{next_state} in sequence, one per TCK cycle.
  6418. The final state must also be stable.
  6419. @end deffn
  6420. @deffn Command {runtest} @var{num_cycles}
  6421. Move to the @sc{run/idle} state, and execute at least
  6422. @var{num_cycles} of the JTAG clock (TCK).
  6423. Instructions often need some time
  6424. to execute before they take effect.
  6425. @end deffn
  6426. @c tms_sequence (short|long)
  6427. @c ... temporary, debug-only, other than USBprog bug workaround...
  6428. @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
  6429. Verify values captured during @sc{ircapture} and returned
  6430. during IR scans. Default is enabled, but this can be
  6431. overridden by @command{verify_jtag}.
  6432. This flag is ignored when validating JTAG chain configuration.
  6433. @end deffn
  6434. @deffn Command {verify_jtag} (@option{enable}|@option{disable})
  6435. Enables verification of DR and IR scans, to help detect
  6436. programming errors. For IR scans, @command{verify_ircapture}
  6437. must also be enabled.
  6438. Default is enabled.
  6439. @end deffn
  6440. @section TAP state names
  6441. @cindex TAP state names
  6442. The @var{tap_state} names used by OpenOCD in the @command{drscan},
  6443. @command{irscan}, and @command{pathmove} commands are the same
  6444. as those used in SVF boundary scan documents, except that
  6445. SVF uses @sc{idle} instead of @sc{run/idle}.
  6446. @itemize @bullet
  6447. @item @b{RESET} ... @emph{stable} (with TMS high);
  6448. acts as if TRST were pulsed
  6449. @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
  6450. @item @b{DRSELECT}
  6451. @item @b{DRCAPTURE}
  6452. @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
  6453. through the data register
  6454. @item @b{DREXIT1}
  6455. @item @b{DRPAUSE} ... @emph{stable}; data register ready
  6456. for update or more shifting
  6457. @item @b{DREXIT2}
  6458. @item @b{DRUPDATE}
  6459. @item @b{IRSELECT}
  6460. @item @b{IRCAPTURE}
  6461. @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
  6462. through the instruction register
  6463. @item @b{IREXIT1}
  6464. @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
  6465. for update or more shifting
  6466. @item @b{IREXIT2}
  6467. @item @b{IRUPDATE}
  6468. @end itemize
  6469. Note that only six of those states are fully ``stable'' in the
  6470. face of TMS fixed (low except for @sc{reset})
  6471. and a free-running JTAG clock. For all the
  6472. others, the next TCK transition changes to a new state.
  6473. @itemize @bullet
  6474. @item From @sc{drshift} and @sc{irshift}, clock transitions will
  6475. produce side effects by changing register contents. The values
  6476. to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
  6477. may not be as expected.
  6478. @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
  6479. choices after @command{drscan} or @command{irscan} commands,
  6480. since they are free of JTAG side effects.
  6481. @item @sc{run/idle} may have side effects that appear at non-JTAG
  6482. levels, such as advancing the ARM9E-S instruction pipeline.
  6483. Consult the documentation for the TAP(s) you are working with.
  6484. @end itemize
  6485. @node Boundary Scan Commands
  6486. @chapter Boundary Scan Commands
  6487. One of the original purposes of JTAG was to support
  6488. boundary scan based hardware testing.
  6489. Although its primary focus is to support On-Chip Debugging,
  6490. OpenOCD also includes some boundary scan commands.
  6491. @section SVF: Serial Vector Format
  6492. @cindex Serial Vector Format
  6493. @cindex SVF
  6494. The Serial Vector Format, better known as @dfn{SVF}, is a
  6495. way to represent JTAG test patterns in text files.
  6496. In a debug session using JTAG for its transport protocol,
  6497. OpenOCD supports running such test files.
  6498. @deffn Command {svf} filename [@option{quiet}]
  6499. This issues a JTAG reset (Test-Logic-Reset) and then
  6500. runs the SVF script from @file{filename}.
  6501. Unless the @option{quiet} option is specified,
  6502. each command is logged before it is executed.
  6503. @end deffn
  6504. @section XSVF: Xilinx Serial Vector Format
  6505. @cindex Xilinx Serial Vector Format
  6506. @cindex XSVF
  6507. The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
  6508. binary representation of SVF which is optimized for use with
  6509. Xilinx devices.
  6510. In a debug session using JTAG for its transport protocol,
  6511. OpenOCD supports running such test files.
  6512. @quotation Important
  6513. Not all XSVF commands are supported.
  6514. @end quotation
  6515. @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
  6516. This issues a JTAG reset (Test-Logic-Reset) and then
  6517. runs the XSVF script from @file{filename}.
  6518. When a @var{tapname} is specified, the commands are directed at
  6519. that TAP.
  6520. When @option{virt2} is specified, the @sc{xruntest} command counts
  6521. are interpreted as TCK cycles instead of microseconds.
  6522. Unless the @option{quiet} option is specified,
  6523. messages are logged for comments and some retries.
  6524. @end deffn
  6525. The OpenOCD sources also include two utility scripts
  6526. for working with XSVF; they are not currently installed
  6527. after building the software.
  6528. You may find them useful:
  6529. @itemize
  6530. @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
  6531. syntax understood by the @command{xsvf} command; see notes below.
  6532. @item @emph{xsvfdump} ... converts XSVF files into a text output format;
  6533. understands the OpenOCD extensions.
  6534. @end itemize
  6535. The input format accepts a handful of non-standard extensions.
  6536. These include three opcodes corresponding to SVF extensions
  6537. from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
  6538. two opcodes supporting a more accurate translation of SVF
  6539. (XTRST, XWAITSTATE).
  6540. If @emph{xsvfdump} shows a file is using those opcodes, it
  6541. probably will not be usable with other XSVF tools.
  6542. @node TFTP
  6543. @chapter TFTP
  6544. @cindex TFTP
  6545. If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
  6546. be used to access files on PCs (either the developer's PC or some other PC).
  6547. The way this works on the ZY1000 is to prefix a filename by
  6548. "/tftp/ip/" and append the TFTP path on the TFTP
  6549. server (tftpd). For example,
  6550. @example
  6551. load_image /tftp/10.0.0.96/c:\temp\abc.elf
  6552. @end example
  6553. will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
  6554. if the file was hosted on the embedded host.
  6555. In order to achieve decent performance, you must choose a TFTP server
  6556. that supports a packet size bigger than the default packet size (512 bytes). There
  6557. are numerous TFTP servers out there (free and commercial) and you will have to do
  6558. a bit of googling to find something that fits your requirements.
  6559. @node GDB and OpenOCD
  6560. @chapter GDB and OpenOCD
  6561. @cindex GDB
  6562. OpenOCD complies with the remote gdbserver protocol, and as such can be used
  6563. to debug remote targets.
  6564. Setting up GDB to work with OpenOCD can involve several components:
  6565. @itemize
  6566. @item The OpenOCD server support for GDB may need to be configured.
  6567. @xref{gdbconfiguration,,GDB Configuration}.
  6568. @item GDB's support for OpenOCD may need configuration,
  6569. as shown in this chapter.
  6570. @item If you have a GUI environment like Eclipse,
  6571. that also will probably need to be configured.
  6572. @end itemize
  6573. Of course, the version of GDB you use will need to be one which has
  6574. been built to know about the target CPU you're using. It's probably
  6575. part of the tool chain you're using. For example, if you are doing
  6576. cross-development for ARM on an x86 PC, instead of using the native
  6577. x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
  6578. if that's the tool chain used to compile your code.
  6579. @section Connecting to GDB
  6580. @cindex Connecting to GDB
  6581. Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
  6582. instance GDB 6.3 has a known bug that produces bogus memory access
  6583. errors, which has since been fixed; see
  6584. @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
  6585. OpenOCD can communicate with GDB in two ways:
  6586. @enumerate
  6587. @item
  6588. A socket (TCP/IP) connection is typically started as follows:
  6589. @example
  6590. target remote localhost:3333
  6591. @end example
  6592. This would cause GDB to connect to the gdbserver on the local pc using port 3333.
  6593. It is also possible to use the GDB extended remote protocol as follows:
  6594. @example
  6595. target extended-remote localhost:3333
  6596. @end example
  6597. @item
  6598. A pipe connection is typically started as follows:
  6599. @example
  6600. target remote | openocd -c "gdb_port pipe; log_output openocd.log"
  6601. @end example
  6602. This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
  6603. Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
  6604. session. log_output sends the log output to a file to ensure that the pipe is
  6605. not saturated when using higher debug level outputs.
  6606. @end enumerate
  6607. To list the available OpenOCD commands type @command{monitor help} on the
  6608. GDB command line.
  6609. @section Sample GDB session startup
  6610. With the remote protocol, GDB sessions start a little differently
  6611. than they do when you're debugging locally.
  6612. Here's an examples showing how to start a debug session with a
  6613. small ARM program.
  6614. In this case the program was linked to be loaded into SRAM on a Cortex-M3.
  6615. Most programs would be written into flash (address 0) and run from there.
  6616. @example
  6617. $ arm-none-eabi-gdb example.elf
  6618. (gdb) target remote localhost:3333
  6619. Remote debugging using localhost:3333
  6620. ...
  6621. (gdb) monitor reset halt
  6622. ...
  6623. (gdb) load
  6624. Loading section .vectors, size 0x100 lma 0x20000000
  6625. Loading section .text, size 0x5a0 lma 0x20000100
  6626. Loading section .data, size 0x18 lma 0x200006a0
  6627. Start address 0x2000061c, load size 1720
  6628. Transfer rate: 22 KB/sec, 573 bytes/write.
  6629. (gdb) continue
  6630. Continuing.
  6631. ...
  6632. @end example
  6633. You could then interrupt the GDB session to make the program break,
  6634. type @command{where} to show the stack, @command{list} to show the
  6635. code around the program counter, @command{step} through code,
  6636. set breakpoints or watchpoints, and so on.
  6637. @section Configuring GDB for OpenOCD
  6638. OpenOCD supports the gdb @option{qSupported} packet, this enables information
  6639. to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
  6640. packet size and the device's memory map.
  6641. You do not need to configure the packet size by hand,
  6642. and the relevant parts of the memory map should be automatically
  6643. set up when you declare (NOR) flash banks.
  6644. However, there are other things which GDB can't currently query.
  6645. You may need to set those up by hand.
  6646. As OpenOCD starts up, you will often see a line reporting
  6647. something like:
  6648. @example
  6649. Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
  6650. @end example
  6651. You can pass that information to GDB with these commands:
  6652. @example
  6653. set remote hardware-breakpoint-limit 6
  6654. set remote hardware-watchpoint-limit 4
  6655. @end example
  6656. With that particular hardware (Cortex-M3) the hardware breakpoints
  6657. only work for code running from flash memory. Most other ARM systems
  6658. do not have such restrictions.
  6659. Another example of useful GDB configuration came from a user who
  6660. found that single stepping his Cortex-M3 didn't work well with IRQs
  6661. and an RTOS until he told GDB to disable the IRQs while stepping:
  6662. @example
  6663. define hook-step
  6664. mon cortex_m3 maskisr on
  6665. end
  6666. define hookpost-step
  6667. mon cortex_m3 maskisr off
  6668. end
  6669. @end example
  6670. Rather than typing such commands interactively, you may prefer to
  6671. save them in a file and have GDB execute them as it starts, perhaps
  6672. using a @file{.gdbinit} in your project directory or starting GDB
  6673. using @command{gdb -x filename}.
  6674. @section Programming using GDB
  6675. @cindex Programming using GDB
  6676. @anchor{programmingusinggdb}
  6677. By default the target memory map is sent to GDB. This can be disabled by
  6678. the following OpenOCD configuration option:
  6679. @example
  6680. gdb_memory_map disable
  6681. @end example
  6682. For this to function correctly a valid flash configuration must also be set
  6683. in OpenOCD. For faster performance you should also configure a valid
  6684. working area.
  6685. Informing GDB of the memory map of the target will enable GDB to protect any
  6686. flash areas of the target and use hardware breakpoints by default. This means
  6687. that the OpenOCD option @command{gdb_breakpoint_override} is not required when
  6688. using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
  6689. To view the configured memory map in GDB, use the GDB command @option{info mem}
  6690. All other unassigned addresses within GDB are treated as RAM.
  6691. GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
  6692. This can be changed to the old behaviour by using the following GDB command
  6693. @example
  6694. set mem inaccessible-by-default off
  6695. @end example
  6696. If @command{gdb_flash_program enable} is also used, GDB will be able to
  6697. program any flash memory using the vFlash interface.
  6698. GDB will look at the target memory map when a load command is given, if any
  6699. areas to be programmed lie within the target flash area the vFlash packets
  6700. will be used.
  6701. If the target needs configuring before GDB programming, an event
  6702. script can be executed:
  6703. @example
  6704. $_TARGETNAME configure -event EVENTNAME BODY
  6705. @end example
  6706. To verify any flash programming the GDB command @option{compare-sections}
  6707. can be used.
  6708. @anchor{usingopenocdsmpwithgdb}
  6709. @section Using OpenOCD SMP with GDB
  6710. @cindex SMP
  6711. For SMP support following GDB serial protocol packet have been defined :
  6712. @itemize @bullet
  6713. @item j - smp status request
  6714. @item J - smp set request
  6715. @end itemize
  6716. OpenOCD implements :
  6717. @itemize @bullet
  6718. @item @option{jc} packet for reading core id displayed by
  6719. GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
  6720. @option{E01} for target not smp.
  6721. @item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
  6722. (core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
  6723. for target not smp or @option{OK} on success.
  6724. @end itemize
  6725. Handling of this packet within GDB can be done :
  6726. @itemize @bullet
  6727. @item by the creation of an internal variable (i.e @option{_core}) by mean
  6728. of function allocate_computed_value allowing following GDB command.
  6729. @example
  6730. set $_core 1
  6731. #Jc01 packet is sent
  6732. print $_core
  6733. #jc packet is sent and result is affected in $
  6734. @end example
  6735. @item by the usage of GDB maintenance command as described in following example (2 cpus in SMP with
  6736. core id 0 and 1 @pxref{definecputargetsworkinginsmp,,Define CPU targets working in SMP}).
  6737. @example
  6738. # toggle0 : force display of coreid 0
  6739. define toggle0
  6740. maint packet Jc0
  6741. continue
  6742. main packet Jc-1
  6743. end
  6744. # toggle1 : force display of coreid 1
  6745. define toggle1
  6746. maint packet Jc1
  6747. continue
  6748. main packet Jc-1
  6749. end
  6750. @end example
  6751. @end itemize
  6752. @node Tcl Scripting API
  6753. @chapter Tcl Scripting API
  6754. @cindex Tcl Scripting API
  6755. @cindex Tcl scripts
  6756. @section API rules
  6757. The commands are stateless. E.g. the telnet command line has a concept
  6758. of currently active target, the Tcl API proc's take this sort of state
  6759. information as an argument to each proc.
  6760. There are three main types of return values: single value, name value
  6761. pair list and lists.
  6762. Name value pair. The proc 'foo' below returns a name/value pair
  6763. list.
  6764. @verbatim
  6765. > set foo(me) Duane
  6766. > set foo(you) Oyvind
  6767. > set foo(mouse) Micky
  6768. > set foo(duck) Donald
  6769. If one does this:
  6770. > set foo
  6771. The result is:
  6772. me Duane you Oyvind mouse Micky duck Donald
  6773. Thus, to get the names of the associative array is easy:
  6774. foreach { name value } [set foo] {
  6775. puts "Name: $name, Value: $value"
  6776. }
  6777. @end verbatim
  6778. Lists returned must be relatively small. Otherwise a range
  6779. should be passed in to the proc in question.
  6780. @section Internal low-level Commands
  6781. By low-level, the intent is a human would not directly use these commands.
  6782. Low-level commands are (should be) prefixed with "ocd_", e.g.
  6783. @command{ocd_flash_banks}
  6784. is the low level API upon which @command{flash banks} is implemented.
  6785. @itemize @bullet
  6786. @item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
  6787. Read memory and return as a Tcl array for script processing
  6788. @item @b{array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
  6789. Convert a Tcl array to memory locations and write the values
  6790. @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
  6791. Return information about the flash banks
  6792. @end itemize
  6793. OpenOCD commands can consist of two words, e.g. "flash banks". The
  6794. @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
  6795. called "flash_banks".
  6796. @section OpenOCD specific Global Variables
  6797. Real Tcl has ::tcl_platform(), and platform::identify, and many other
  6798. variables. JimTCL, as implemented in OpenOCD creates $ocd_HOSTOS which
  6799. holds one of the following values:
  6800. @itemize @bullet
  6801. @item @b{cygwin} Running under Cygwin
  6802. @item @b{darwin} Darwin (Mac-OS) is the underlying operating sytem.
  6803. @item @b{freebsd} Running under FreeBSD
  6804. @item @b{linux} Linux is the underlying operating sytem
  6805. @item @b{mingw32} Running under MingW32
  6806. @item @b{winxx} Built using Microsoft Visual Studio
  6807. @item @b{other} Unknown, none of the above.
  6808. @end itemize
  6809. Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
  6810. @quotation Note
  6811. We should add support for a variable like Tcl variable
  6812. @code{tcl_platform(platform)}, it should be called
  6813. @code{jim_platform} (because it
  6814. is jim, not real tcl).
  6815. @end quotation
  6816. @node FAQ
  6817. @chapter FAQ
  6818. @cindex faq
  6819. @enumerate
  6820. @anchor{faqrtck}
  6821. @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
  6822. @cindex RTCK
  6823. @cindex adaptive clocking
  6824. @*
  6825. In digital circuit design it is often refered to as ``clock
  6826. synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
  6827. operating at some speed, your CPU target is operating at another.
  6828. The two clocks are not synchronised, they are ``asynchronous''
  6829. In order for the two to work together they must be synchronised
  6830. well enough to work; JTAG can't go ten times faster than the CPU,
  6831. for example. There are 2 basic options:
  6832. @enumerate
  6833. @item
  6834. Use a special "adaptive clocking" circuit to change the JTAG
  6835. clock rate to match what the CPU currently supports.
  6836. @item
  6837. The JTAG clock must be fixed at some speed that's enough slower than
  6838. the CPU clock that all TMS and TDI transitions can be detected.
  6839. @end enumerate
  6840. @b{Does this really matter?} For some chips and some situations, this
  6841. is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
  6842. the CPU has no difficulty keeping up with JTAG.
  6843. Startup sequences are often problematic though, as are other
  6844. situations where the CPU clock rate changes (perhaps to save
  6845. power).
  6846. For example, Atmel AT91SAM chips start operation from reset with
  6847. a 32kHz system clock. Boot firmware may activate the main oscillator
  6848. and PLL before switching to a faster clock (perhaps that 500 MHz
  6849. ARM926 scenario).
  6850. If you're using JTAG to debug that startup sequence, you must slow
  6851. the JTAG clock to sometimes 1 to 4kHz. After startup completes,
  6852. JTAG can use a faster clock.
  6853. Consider also debugging a 500MHz ARM926 hand held battery powered
  6854. device that enters a low power ``deep sleep'' mode, at 32kHz CPU
  6855. clock, between keystrokes unless it has work to do. When would
  6856. that 5 MHz JTAG clock be usable?
  6857. @b{Solution #1 - A special circuit}
  6858. In order to make use of this,
  6859. your CPU, board, and JTAG adapter must all support the RTCK
  6860. feature. Not all of them support this; keep reading!
  6861. The RTCK ("Return TCK") signal in some ARM chips is used to help with
  6862. this problem. ARM has a good description of the problem described at
  6863. this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
  6864. 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
  6865. work? / how does adaptive clocking work?''.
  6866. The nice thing about adaptive clocking is that ``battery powered hand
  6867. held device example'' - the adaptiveness works perfectly all the
  6868. time. One can set a break point or halt the system in the deep power
  6869. down code, slow step out until the system speeds up.
  6870. Note that adaptive clocking may also need to work at the board level,
  6871. when a board-level scan chain has multiple chips.
  6872. Parallel clock voting schemes are good way to implement this,
  6873. both within and between chips, and can easily be implemented
  6874. with a CPLD.
  6875. It's not difficult to have logic fan a module's input TCK signal out
  6876. to each TAP in the scan chain, and then wait until each TAP's RTCK comes
  6877. back with the right polarity before changing the output RTCK signal.
  6878. Texas Instruments makes some clock voting logic available
  6879. for free (with no support) in VHDL form; see
  6880. @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
  6881. @b{Solution #2 - Always works - but may be slower}
  6882. Often this is a perfectly acceptable solution.
  6883. In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
  6884. the target clock speed. But what that ``magic division'' is varies
  6885. depending on the chips on your board.
  6886. @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
  6887. ARM11 cores use an 8:1 division.
  6888. @b{Xilinx rule of thumb} is 1/12 the clock speed.
  6889. Note: most full speed FT2232 based JTAG adapters are limited to a
  6890. maximum of 6MHz. The ones using USB high speed chips (FT2232H)
  6891. often support faster clock rates (and adaptive clocking).
  6892. You can still debug the 'low power' situations - you just need to
  6893. either use a fixed and very slow JTAG clock rate ... or else
  6894. manually adjust the clock speed at every step. (Adjusting is painful
  6895. and tedious, and is not always practical.)
  6896. It is however easy to ``code your way around it'' - i.e.: Cheat a little,
  6897. have a special debug mode in your application that does a ``high power
  6898. sleep''. If you are careful - 98% of your problems can be debugged
  6899. this way.
  6900. Note that on ARM you may need to avoid using the @emph{wait for interrupt}
  6901. operation in your idle loops even if you don't otherwise change the CPU
  6902. clock rate.
  6903. That operation gates the CPU clock, and thus the JTAG clock; which
  6904. prevents JTAG access. One consequence is not being able to @command{halt}
  6905. cores which are executing that @emph{wait for interrupt} operation.
  6906. To set the JTAG frequency use the command:
  6907. @example
  6908. # Example: 1.234MHz
  6909. adapter_khz 1234
  6910. @end example
  6911. @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
  6912. OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
  6913. around Windows filenames.
  6914. @example
  6915. > echo \a
  6916. > echo @{\a@}
  6917. \a
  6918. > echo "\a"
  6919. >
  6920. @end example
  6921. @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
  6922. Make sure you have Cygwin installed, or at least a version of OpenOCD that
  6923. claims to come with all the necessary DLLs. When using Cygwin, try launching
  6924. OpenOCD from the Cygwin shell.
  6925. @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
  6926. Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
  6927. arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
  6928. GDB issues software breakpoints when a normal breakpoint is requested, or to implement
  6929. source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
  6930. software breakpoints consume one of the two available hardware breakpoints.
  6931. @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
  6932. Make sure the core frequency specified in the @option{flash lpc2000} line matches the
  6933. clock at the time you're programming the flash. If you've specified the crystal's
  6934. frequency, make sure the PLL is disabled. If you've specified the full core speed
  6935. (e.g. 60MHz), make sure the PLL is enabled.
  6936. @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
  6937. I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
  6938. out while waiting for end of scan, rtck was disabled".
  6939. Make sure your PC's parallel port operates in EPP mode. You might have to try several
  6940. settings in your PC BIOS (ECP, EPP, and different versions of those).
  6941. @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
  6942. I get lots of "Error: arm7_9_common.c:1771