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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * Copyright (C) 2008 by Oyvind Harboe *
  9. * oyvind.harboe@zylin.com *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  25. ***************************************************************************/
  26. #ifdef HAVE_CONFIG_H
  27. #include "config.h"
  28. #endif
  29. #include "arm.h"
  30. #include "armv4_5.h"
  31. #include "arm_jtag.h"
  32. #include "breakpoints.h"
  33. #include "arm_disassembler.h"
  34. #include <helper/binarybuffer.h>
  35. #include "algorithm.h"
  36. #include "register.h"
  37. /* offsets into armv4_5 core register cache */
  38. enum {
  39. /* ARMV4_5_CPSR = 31, */
  40. ARMV4_5_SPSR_FIQ = 32,
  41. ARMV4_5_SPSR_IRQ = 33,
  42. ARMV4_5_SPSR_SVC = 34,
  43. ARMV4_5_SPSR_ABT = 35,
  44. ARMV4_5_SPSR_UND = 36,
  45. ARM_SPSR_MON = 39,
  46. };
  47. static const uint8_t arm_usr_indices[17] = {
  48. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
  49. };
  50. static const uint8_t arm_fiq_indices[8] = {
  51. 16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
  52. };
  53. static const uint8_t arm_irq_indices[3] = {
  54. 23, 24, ARMV4_5_SPSR_IRQ,
  55. };
  56. static const uint8_t arm_svc_indices[3] = {
  57. 25, 26, ARMV4_5_SPSR_SVC,
  58. };
  59. static const uint8_t arm_abt_indices[3] = {
  60. 27, 28, ARMV4_5_SPSR_ABT,
  61. };
  62. static const uint8_t arm_und_indices[3] = {
  63. 29, 30, ARMV4_5_SPSR_UND,
  64. };
  65. static const uint8_t arm_mon_indices[3] = {
  66. 37, 38, ARM_SPSR_MON,
  67. };
  68. static const struct {
  69. const char *name;
  70. unsigned short psr;
  71. /* For user and system modes, these list indices for all registers.
  72. * otherwise they're just indices for the shadow registers and SPSR.
  73. */
  74. unsigned short n_indices;
  75. const uint8_t *indices;
  76. } arm_mode_data[] = {
  77. /* Seven modes are standard from ARM7 on. "System" and "User" share
  78. * the same registers; other modes shadow from 3 to 8 registers.
  79. */
  80. {
  81. .name = "User",
  82. .psr = ARM_MODE_USR,
  83. .n_indices = ARRAY_SIZE(arm_usr_indices),
  84. .indices = arm_usr_indices,
  85. },
  86. {
  87. .name = "FIQ",
  88. .psr = ARM_MODE_FIQ,
  89. .n_indices = ARRAY_SIZE(arm_fiq_indices),
  90. .indices = arm_fiq_indices,
  91. },
  92. {
  93. .name = "Supervisor",
  94. .psr = ARM_MODE_SVC,
  95. .n_indices = ARRAY_SIZE(arm_svc_indices),
  96. .indices = arm_svc_indices,
  97. },
  98. {
  99. .name = "Abort",
  100. .psr = ARM_MODE_ABT,
  101. .n_indices = ARRAY_SIZE(arm_abt_indices),
  102. .indices = arm_abt_indices,
  103. },
  104. {
  105. .name = "IRQ",
  106. .psr = ARM_MODE_IRQ,
  107. .n_indices = ARRAY_SIZE(arm_irq_indices),
  108. .indices = arm_irq_indices,
  109. },
  110. {
  111. .name = "Undefined instruction",
  112. .psr = ARM_MODE_UND,
  113. .n_indices = ARRAY_SIZE(arm_und_indices),
  114. .indices = arm_und_indices,
  115. },
  116. {
  117. .name = "System",
  118. .psr = ARM_MODE_SYS,
  119. .n_indices = ARRAY_SIZE(arm_usr_indices),
  120. .indices = arm_usr_indices,
  121. },
  122. /* TrustZone "Security Extensions" add a secure monitor mode.
  123. * This is distinct from a "debug monitor" which can support
  124. * non-halting debug, in conjunction with some debuggers.
  125. */
  126. {
  127. .name = "Secure Monitor",
  128. .psr = ARM_MODE_MON,
  129. .n_indices = ARRAY_SIZE(arm_mon_indices),
  130. .indices = arm_mon_indices,
  131. },
  132. };
  133. /** Map PSR mode bits to the name of an ARM processor operating mode. */
  134. const char *arm_mode_name(unsigned psr_mode)
  135. {
  136. for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
  137. if (arm_mode_data[i].psr == psr_mode)
  138. return arm_mode_data[i].name;
  139. }
  140. LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
  141. return "UNRECOGNIZED";
  142. }
  143. /** Return true iff the parameter denotes a valid ARM processor mode. */
  144. bool is_arm_mode(unsigned psr_mode)
  145. {
  146. for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
  147. if (arm_mode_data[i].psr == psr_mode)
  148. return true;
  149. }
  150. return false;
  151. }
  152. /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
  153. int arm_mode_to_number(enum arm_mode mode)
  154. {
  155. switch (mode) {
  156. case ARM_MODE_ANY:
  157. /* map MODE_ANY to user mode */
  158. case ARM_MODE_USR:
  159. return 0;
  160. case ARM_MODE_FIQ:
  161. return 1;
  162. case ARM_MODE_IRQ:
  163. return 2;
  164. case ARM_MODE_SVC:
  165. return 3;
  166. case ARM_MODE_ABT:
  167. return 4;
  168. case ARM_MODE_UND:
  169. return 5;
  170. case ARM_MODE_SYS:
  171. return 6;
  172. case ARM_MODE_MON:
  173. return 7;
  174. default:
  175. LOG_ERROR("invalid mode value encountered %d", mode);
  176. return -1;
  177. }
  178. }
  179. /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
  180. enum arm_mode armv4_5_number_to_mode(int number)
  181. {
  182. switch (number) {
  183. case 0:
  184. return ARM_MODE_USR;
  185. case 1:
  186. return ARM_MODE_FIQ;
  187. case 2:
  188. return ARM_MODE_IRQ;
  189. case 3:
  190. return ARM_MODE_SVC;
  191. case 4:
  192. return ARM_MODE_ABT;
  193. case 5:
  194. return ARM_MODE_UND;
  195. case 6:
  196. return ARM_MODE_SYS;
  197. case 7:
  198. return ARM_MODE_MON;
  199. default:
  200. LOG_ERROR("mode index out of bounds %d", number);
  201. return ARM_MODE_ANY;
  202. }
  203. }
  204. static const char *arm_state_strings[] = {
  205. "ARM", "Thumb", "Jazelle", "ThumbEE",
  206. };
  207. /* Templates for ARM core registers.
  208. *
  209. * NOTE: offsets in this table are coupled to the arm_mode_data
  210. * table above, the armv4_5_core_reg_map array below, and also to
  211. * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
  212. */
  213. static const struct {
  214. /* The name is used for e.g. the "regs" command. */
  215. const char *name;
  216. /* The {cookie, mode} tuple uniquely identifies one register.
  217. * In a given mode, cookies 0..15 map to registers R0..R15,
  218. * with R13..R15 usually called SP, LR, PC.
  219. *
  220. * MODE_ANY is used as *input* to the mapping, and indicates
  221. * various special cases (sigh) and errors.
  222. *
  223. * Cookie 16 is (currently) confusing, since it indicates
  224. * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
  225. * (Exception modes have both CPSR and SPSR registers ...)
  226. */
  227. unsigned cookie;
  228. enum arm_mode mode;
  229. } arm_core_regs[] = {
  230. /* IMPORTANT: we guarantee that the first eight cached registers
  231. * correspond to r0..r7, and the fifteenth to PC, so that callers
  232. * don't need to map them.
  233. */
  234. { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, },
  235. { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, },
  236. { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, },
  237. { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, },
  238. { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, },
  239. { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, },
  240. { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, },
  241. { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, },
  242. /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
  243. * them as MODE_ANY creates special cases. (ANY means
  244. * "not mapped" elsewhere; here it's "everything but FIQ".)
  245. */
  246. { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, },
  247. { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, },
  248. { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, },
  249. { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, },
  250. { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, },
  251. /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
  252. { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, },
  253. { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, },
  254. /* guaranteed to be at index 15 */
  255. { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, },
  256. { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, },
  257. { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, },
  258. { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, },
  259. { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, },
  260. { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, },
  261. { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, },
  262. { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, },
  263. { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, },
  264. { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, },
  265. { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, },
  266. { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, },
  267. { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, },
  268. { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, },
  269. { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, },
  270. { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, },
  271. { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, },
  272. { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, },
  273. { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, },
  274. { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, },
  275. { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, },
  276. { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, },
  277. { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, },
  278. { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, },
  279. { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, },
  280. };
  281. /* map core mode (USR, FIQ, ...) and register number to
  282. * indices into the register cache
  283. */
  284. const int armv4_5_core_reg_map[8][17] = {
  285. { /* USR */
  286. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
  287. },
  288. { /* FIQ (8 shadows of USR, vs normal 3) */
  289. 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
  290. },
  291. { /* IRQ */
  292. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
  293. },
  294. { /* SVC */
  295. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
  296. },
  297. { /* ABT */
  298. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
  299. },
  300. { /* UND */
  301. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
  302. },
  303. { /* SYS (same registers as USR) */
  304. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
  305. },
  306. { /* MON */
  307. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
  308. }
  309. };
  310. /**
  311. * Configures host-side ARM records to reflect the specified CPSR.
  312. * Later, code can use arm_reg_current() to map register numbers
  313. * according to how they are exposed by this mode.
  314. */
  315. void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
  316. {
  317. enum arm_mode mode = cpsr & 0x1f;
  318. int num;
  319. /* NOTE: this may be called very early, before the register
  320. * cache is set up. We can't defend against many errors, in
  321. * particular against CPSRs that aren't valid *here* ...
  322. */
  323. if (arm->cpsr) {
  324. buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
  325. arm->cpsr->valid = 1;
  326. arm->cpsr->dirty = 0;
  327. }
  328. arm->core_mode = mode;
  329. /* mode_to_number() warned; set up a somewhat-sane mapping */
  330. num = arm_mode_to_number(mode);
  331. if (num < 0) {
  332. mode = ARM_MODE_USR;
  333. num = 0;
  334. }
  335. arm->map = &armv4_5_core_reg_map[num][0];
  336. arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS)
  337. ? NULL
  338. : arm->core_cache->reg_list + arm->map[16];
  339. /* Older ARMs won't have the J bit */
  340. enum arm_state state;
  341. if (cpsr & (1 << 5)) { /* T */
  342. if (cpsr & (1 << 24)) { /* J */
  343. LOG_WARNING("ThumbEE -- incomplete support");
  344. state = ARM_STATE_THUMB_EE;
  345. } else
  346. state = ARM_STATE_THUMB;
  347. } else {
  348. if (cpsr & (1 << 24)) { /* J */
  349. LOG_ERROR("Jazelle state handling is BROKEN!");
  350. state = ARM_STATE_JAZELLE;
  351. } else
  352. state = ARM_STATE_ARM;
  353. }
  354. arm->core_state = state;
  355. LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
  356. arm_mode_name(mode),
  357. arm_state_strings[arm->core_state]);
  358. }
  359. /**
  360. * Returns handle to the register currently mapped to a given number.
  361. * Someone must have called arm_set_cpsr() before.
  362. *
  363. * \param arm This core's state and registers are used.
  364. * \param regnum From 0..15 corresponding to R0..R14 and PC.
  365. * Note that R0..R7 don't require mapping; you may access those
  366. * as the first eight entries in the register cache. Likewise
  367. * R15 (PC) doesn't need mapping; you may also access it directly.
  368. * However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
  369. * CPSR (arm->cpsr) is also not mapped.
  370. */
  371. struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
  372. {
  373. struct reg *r;
  374. if (regnum > 16)
  375. return NULL;
  376. r = arm->core_cache->reg_list + arm->map[regnum];
  377. /* e.g. invalid CPSR said "secure monitor" mode on a core
  378. * that doesn't support it...
  379. */
  380. if (!r) {
  381. LOG_ERROR("Invalid CPSR mode");
  382. r = arm->core_cache->reg_list + regnum;
  383. }
  384. return r;
  385. }
  386. static const uint8_t arm_gdb_dummy_fp_value[12];
  387. /**
  388. * Dummy FPA registers are required to support GDB on ARM.
  389. * Register packets require eight obsolete FPA register values.
  390. * Modern ARM cores use Vector Floating Point (VFP), if they
  391. * have any floating point support. VFP is not FPA-compatible.
  392. */
  393. struct reg arm_gdb_dummy_fp_reg = {
  394. .name = "GDB dummy FPA register",
  395. .value = (uint8_t *) arm_gdb_dummy_fp_value,
  396. .valid = 1,
  397. .size = 96,
  398. };
  399. static const uint8_t arm_gdb_dummy_fps_value[4];
  400. /**
  401. * Dummy FPA status registers are required to support GDB on ARM.
  402. * Register packets require an obsolete FPA status register.
  403. */
  404. struct reg arm_gdb_dummy_fps_reg = {
  405. .name = "GDB dummy FPA status register",
  406. .value = (uint8_t *) arm_gdb_dummy_fps_value,
  407. .valid = 1,
  408. .size = 32,
  409. };
  410. static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
  411. static void arm_gdb_dummy_init(void)
  412. {
  413. register_init_dummy(&arm_gdb_dummy_fp_reg);
  414. register_init_dummy(&arm_gdb_dummy_fps_reg);
  415. }
  416. static int armv4_5_get_core_reg(struct reg *reg)
  417. {
  418. int retval;
  419. struct arm_reg *reg_arch_info = reg->arch_info;
  420. struct target *target = reg_arch_info->target;
  421. if (target->state != TARGET_HALTED) {
  422. LOG_ERROR("Target not halted");
  423. return ERROR_TARGET_NOT_HALTED;
  424. }
  425. retval = reg_arch_info->arm->read_core_reg(target, reg,
  426. reg_arch_info->num, reg_arch_info->mode);
  427. if (retval == ERROR_OK) {
  428. reg->valid = 1;
  429. reg->dirty = 0;
  430. }
  431. return retval;
  432. }
  433. static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
  434. {
  435. struct arm_reg *reg_arch_info = reg->arch_info;
  436. struct target *target = reg_arch_info->target;
  437. struct arm *armv4_5_target = target_to_arm(target);
  438. uint32_t value = buf_get_u32(buf, 0, 32);
  439. if (target->state != TARGET_HALTED) {
  440. LOG_ERROR("Target not halted");
  441. return ERROR_TARGET_NOT_HALTED;
  442. }
  443. /* Except for CPSR, the "reg" command exposes a writeback model
  444. * for the register cache.
  445. */
  446. if (reg == armv4_5_target->cpsr) {
  447. arm_set_cpsr(armv4_5_target, value);
  448. /* Older cores need help to be in ARM mode during halt
  449. * mode debug, so we clear the J and T bits if we flush.
  450. * For newer cores (v6/v7a/v7r) we don't need that, but
  451. * it won't hurt since CPSR is always flushed anyway.
  452. */
  453. if (armv4_5_target->core_mode !=
  454. (enum arm_mode)(value & 0x1f)) {
  455. LOG_DEBUG("changing ARM core mode to '%s'",
  456. arm_mode_name(value & 0x1f));
  457. value &= ~((1 << 24) | (1 << 5));
  458. armv4_5_target->write_core_reg(target, reg,
  459. 16, ARM_MODE_ANY, value);
  460. }
  461. } else {
  462. buf_set_u32(reg->value, 0, 32, value);
  463. reg->valid = 1;
  464. }
  465. reg->dirty = 1;
  466. return ERROR_OK;
  467. }
  468. static const struct reg_arch_type arm_reg_type = {
  469. .get = armv4_5_get_core_reg,
  470. .set = armv4_5_set_core_reg,
  471. };
  472. struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
  473. {
  474. int num_regs = ARRAY_SIZE(arm_core_regs);
  475. struct reg_cache *cache = malloc(sizeof(struct reg_cache));
  476. struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
  477. struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg));
  478. int i;
  479. if (!cache || !reg_list || !reg_arch_info) {
  480. free(cache);
  481. free(reg_list);
  482. free(reg_arch_info);
  483. return NULL;
  484. }
  485. cache->name = "ARM registers";
  486. cache->next = NULL;
  487. cache->reg_list = reg_list;
  488. cache->num_regs = 0;
  489. for (i = 0; i < num_regs; i++) {
  490. /* Skip registers this core doesn't expose */
  491. if (arm_core_regs[i].mode == ARM_MODE_MON
  492. && arm->core_type != ARM_MODE_MON)
  493. continue;
  494. /* REVISIT handle Cortex-M, which only shadows R13/SP */
  495. reg_arch_info[i].num = arm_core_regs[i].cookie;
  496. reg_arch_info[i].mode = arm_core_regs[i].mode;
  497. reg_arch_info[i].target = target;
  498. reg_arch_info[i].arm = arm;
  499. reg_list[i].name = (char *) arm_core_regs[i].name;
  500. reg_list[i].size = 32;
  501. reg_list[i].value = &reg_arch_info[i].value;
  502. reg_list[i].type = &arm_reg_type;
  503. reg_list[i].arch_info = &reg_arch_info[i];
  504. cache->num_regs++;
  505. }
  506. arm->pc = reg_list + 15;
  507. arm->cpsr = reg_list + ARMV4_5_CPSR;
  508. arm->core_cache = cache;
  509. return cache;
  510. }
  511. int arm_arch_state(struct target *target)
  512. {
  513. struct arm *arm = target_to_arm(target);
  514. if (arm->common_magic != ARM_COMMON_MAGIC) {
  515. LOG_ERROR("BUG: called for a non-ARM target");
  516. return ERROR_FAIL;
  517. }
  518. LOG_USER("target halted in %s state due to %s, current mode: %s\n"
  519. "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
  520. arm_state_strings[arm->core_state],
  521. debug_reason_name(target),
  522. arm_mode_name(arm->core_mode),
  523. buf_get_u32(arm->cpsr->value, 0, 32),
  524. buf_get_u32(arm->pc->value, 0, 32),
  525. arm->is_semihosting ? ", semihosting" : "");
  526. return ERROR_OK;
  527. }
  528. #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
  529. (cache->reg_list[armv4_5_core_reg_map[mode][num]])
  530. COMMAND_HANDLER(handle_armv4_5_reg_command)
  531. {
  532. struct target *target = get_current_target(CMD_CTX);
  533. struct arm *arm = target_to_arm(target);
  534. struct reg *regs;
  535. if (!is_arm(arm)) {
  536. command_print(CMD_CTX, "current target isn't an ARM");
  537. return ERROR_FAIL;
  538. }
  539. if (target->state != TARGET_HALTED) {
  540. command_print(CMD_CTX, "error: target must be halted for register accesses");
  541. return ERROR_FAIL;
  542. }
  543. if (arm->core_type != ARM_MODE_ANY) {
  544. command_print(CMD_CTX,
  545. "Microcontroller Profile not supported - use standard reg cmd");
  546. return ERROR_OK;
  547. }
  548. if (!is_arm_mode(arm->core_mode)) {
  549. LOG_ERROR("not a valid arm core mode - communication failure?");
  550. return ERROR_FAIL;
  551. }
  552. if (!arm->full_context) {
  553. command_print(CMD_CTX, "error: target doesn't support %s",
  554. CMD_NAME);
  555. return ERROR_FAIL;
  556. }
  557. regs = arm->core_cache->reg_list;
  558. for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
  559. const char *name;
  560. char *sep = "\n";
  561. char *shadow = "";
  562. /* label this bank of registers (or shadows) */
  563. switch (arm_mode_data[mode].psr) {
  564. case ARM_MODE_SYS:
  565. continue;
  566. case ARM_MODE_USR:
  567. name = "System and User";
  568. sep = "";
  569. break;
  570. case ARM_MODE_MON:
  571. if (arm->core_type != ARM_MODE_MON)
  572. continue;
  573. /* FALLTHROUGH */
  574. default:
  575. name = arm_mode_data[mode].name;
  576. shadow = "shadow ";
  577. break;
  578. }
  579. command_print(CMD_CTX, "%s%s mode %sregisters",
  580. sep, name, shadow);
  581. /* display N rows of up to 4 registers each */
  582. for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) {
  583. char output[80];
  584. int output_len = 0;
  585. for (unsigned j = 0; j < 4; j++, i++) {
  586. uint32_t value;
  587. struct reg *reg = regs;
  588. if (i >= arm_mode_data[mode].n_indices)
  589. break;
  590. reg += arm_mode_data[mode].indices[i];
  591. /* REVISIT be smarter about faults... */
  592. if (!reg->valid)
  593. arm->full_context(target);
  594. value = buf_get_u32(reg->value, 0, 32);
  595. output_len += snprintf(output + output_len,
  596. sizeof(output) - output_len,
  597. "%8s: %8.8" PRIx32 " ",
  598. reg->name, value);
  599. }
  600. command_print(CMD_CTX, "%s", output);
  601. }
  602. }
  603. return ERROR_OK;
  604. }
  605. COMMAND_HANDLER(handle_armv4_5_core_state_command)
  606. {
  607. struct target *target = get_current_target(CMD_CTX);
  608. struct arm *arm = target_to_arm(target);
  609. if (!is_arm(arm)) {
  610. command_print(CMD_CTX, "current target isn't an ARM");
  611. return ERROR_FAIL;
  612. }
  613. if (arm->core_type == ARM_MODE_THREAD) {
  614. /* armv7m not supported */
  615. command_print(CMD_CTX, "Unsupported Command");
  616. return ERROR_OK;
  617. }
  618. if (CMD_ARGC > 0) {
  619. if (strcmp(CMD_ARGV[0], "arm") == 0)
  620. arm->core_state = ARM_STATE_ARM;
  621. if (strcmp(CMD_ARGV[0], "thumb") == 0)
  622. arm->core_state = ARM_STATE_THUMB;
  623. }
  624. command_print(CMD_CTX, "core state: %s", arm_state_strings[arm->core_state]);
  625. return ERROR_OK;
  626. }
  627. COMMAND_HANDLER(handle_arm_disassemble_command)
  628. {
  629. int retval = ERROR_OK;
  630. struct target *target = get_current_target(CMD_CTX);
  631. if (target == NULL) {
  632. LOG_ERROR("No target selected");
  633. return ERROR_FAIL;
  634. }
  635. struct arm *arm = target_to_arm(target);
  636. uint32_t address;
  637. int count = 1;
  638. int thumb = 0;
  639. if (!is_arm(arm)) {
  640. command_print(CMD_CTX, "current target isn't an ARM");
  641. return ERROR_FAIL;
  642. }
  643. if (arm->core_type == ARM_MODE_THREAD) {
  644. /* armv7m is always thumb mode */
  645. thumb = 1;
  646. }
  647. switch (CMD_ARGC) {
  648. case 3:
  649. if (strcmp(CMD_ARGV[2], "thumb") != 0)
  650. goto usage;
  651. thumb = 1;
  652. /* FALL THROUGH */
  653. case 2:
  654. COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
  655. /* FALL THROUGH */
  656. case 1:
  657. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
  658. if (address & 0x01) {
  659. if (!thumb) {
  660. command_print(CMD_CTX, "Disassemble as Thumb");
  661. thumb = 1;
  662. }
  663. address &= ~1;
  664. }
  665. break;
  666. default:
  667. usage:
  668. count = 0;
  669. retval = ERROR_COMMAND_SYNTAX_ERROR;
  670. }
  671. while (count-- > 0) {
  672. struct arm_instruction cur_instruction;
  673. if (thumb) {
  674. /* Always use Thumb2 disassembly for best handling
  675. * of 32-bit BL/BLX, and to work with newer cores
  676. * (some ARMv6, all ARMv7) that use Thumb2.
  677. */
  678. retval = thumb2_opcode(target, address,
  679. &cur_instruction);
  680. if (retval != ERROR_OK)
  681. break;
  682. } else {
  683. uint32_t opcode;
  684. retval = target_read_u32(target, address, &opcode);
  685. if (retval != ERROR_OK)
  686. break;
  687. retval = arm_evaluate_opcode(opcode, address,
  688. &cur_instruction) != ERROR_OK;
  689. if (retval != ERROR_OK)
  690. break;
  691. }
  692. command_print(CMD_CTX, "%s", cur_instruction.text);
  693. address += cur_instruction.instruction_size;
  694. }
  695. return retval;
  696. }
  697. static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
  698. {
  699. struct command_context *context;
  700. struct target *target;
  701. struct arm *arm;
  702. int retval;
  703. context = current_command_context(interp);
  704. assert(context != NULL);
  705. target = get_current_target(context);
  706. if (target == NULL) {
  707. LOG_ERROR("%s: no current target", __func__);
  708. return JIM_ERR;
  709. }
  710. if (!target_was_examined(target)) {
  711. LOG_ERROR("%s: not yet examined", target_name(target));
  712. return JIM_ERR;
  713. }
  714. arm = target_to_arm(target);
  715. if (!is_arm(arm)) {
  716. LOG_ERROR("%s: not an ARM", target_name(target));
  717. return JIM_ERR;
  718. }
  719. if ((argc < 6) || (argc > 7)) {
  720. /* FIXME use the command name to verify # params... */
  721. LOG_ERROR("%s: wrong number of arguments", __func__);
  722. return JIM_ERR;
  723. }
  724. int cpnum;
  725. uint32_t op1;
  726. uint32_t op2;
  727. uint32_t CRn;
  728. uint32_t CRm;
  729. uint32_t value;
  730. long l;
  731. /* NOTE: parameter sequence matches ARM instruction set usage:
  732. * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
  733. * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
  734. * The "rX" is necessarily omitted; it uses Tcl mechanisms.
  735. */
  736. retval = Jim_GetLong(interp, argv[1], &l);
  737. if (retval != JIM_OK)
  738. return retval;
  739. if (l & ~0xf) {
  740. LOG_ERROR("%s: %s %d out of range", __func__,
  741. "coprocessor", (int) l);
  742. return JIM_ERR;
  743. }
  744. cpnum = l;
  745. retval = Jim_GetLong(interp, argv[2], &l);
  746. if (retval != JIM_OK)
  747. return retval;
  748. if (l & ~0x7) {
  749. LOG_ERROR("%s: %s %d out of range", __func__,
  750. "op1", (int) l);
  751. return JIM_ERR;
  752. }
  753. op1 = l;
  754. retval = Jim_GetLong(interp, argv[3], &l);
  755. if (retval != JIM_OK)
  756. return retval;
  757. if (l & ~0xf) {
  758. LOG_ERROR("%s: %s %d out of range", __func__,
  759. "CRn", (int) l);
  760. return JIM_ERR;
  761. }
  762. CRn = l;
  763. retval = Jim_GetLong(interp, argv[4], &l);
  764. if (retval != JIM_OK)
  765. return retval;
  766. if (l & ~0xf) {
  767. LOG_ERROR("%s: %s %d out of range", __func__,
  768. "CRm", (int) l);
  769. return JIM_ERR;
  770. }
  771. CRm = l;
  772. retval = Jim_GetLong(interp, argv[5], &l);
  773. if (retval != JIM_OK)
  774. return retval;
  775. if (l & ~0x7) {
  776. LOG_ERROR("%s: %s %d out of range", __func__,
  777. "op2", (int) l);
  778. return JIM_ERR;
  779. }
  780. op2 = l;
  781. value = 0;
  782. /* FIXME don't assume "mrc" vs "mcr" from the number of params;
  783. * that could easily be a typo! Check both...
  784. *
  785. * FIXME change the call syntax here ... simplest to just pass
  786. * the MRC() or MCR() instruction to be executed. That will also
  787. * let us support the "mrc2" and "mcr2" opcodes (toggling one bit)
  788. * if that's ever needed.
  789. */
  790. if (argc == 7) {
  791. retval = Jim_GetLong(interp, argv[6], &l);
  792. if (retval != JIM_OK)
  793. return retval;
  794. value = l;
  795. /* NOTE: parameters reordered! */
  796. /* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */
  797. retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
  798. if (retval != ERROR_OK)
  799. return JIM_ERR;
  800. } else {
  801. /* NOTE: parameters reordered! */
  802. /* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */
  803. retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
  804. if (retval != ERROR_OK)
  805. return JIM_ERR;
  806. Jim_SetResult(interp, Jim_NewIntObj(interp, value));
  807. }
  808. return JIM_OK;
  809. }
  810. COMMAND_HANDLER(handle_arm_semihosting_command)
  811. {
  812. struct target *target = get_current_target(CMD_CTX);
  813. if (target == NULL) {
  814. LOG_ERROR("No target selected");
  815. return ERROR_FAIL;
  816. }
  817. struct arm *arm = target_to_arm(target);
  818. if (!is_arm(arm)) {
  819. command_print(CMD_CTX, "current target isn't an ARM");
  820. return ERROR_FAIL;
  821. }
  822. if (!arm->setup_semihosting) {
  823. command_print(CMD_CTX, "semihosting not supported for current target");
  824. return ERROR_FAIL;
  825. }
  826. if (CMD_ARGC > 0) {
  827. int semihosting;
  828. COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
  829. if (!target_was_examined(target)) {
  830. LOG_ERROR("Target not examined yet");
  831. return ERROR_FAIL;
  832. }
  833. if (arm->setup_semihosting(target, semihosting) != ERROR_OK) {
  834. LOG_ERROR("Failed to Configure semihosting");
  835. return ERROR_FAIL;
  836. }
  837. /* FIXME never let that "catch" be dropped! */
  838. arm->is_semihosting = semihosting;
  839. }
  840. command_print(CMD_CTX, "semihosting is %s",
  841. arm->is_semihosting
  842. ? "enabled" : "disabled");
  843. return ERROR_OK;
  844. }
  845. static const struct command_registration arm_exec_command_handlers[] = {
  846. {
  847. .name = "reg",
  848. .handler = handle_armv4_5_reg_command,
  849. .mode = COMMAND_EXEC,
  850. .help = "display ARM core registers",
  851. .usage = "",
  852. },
  853. {
  854. .name = "core_state",
  855. .handler = handle_armv4_5_core_state_command,
  856. .mode = COMMAND_EXEC,
  857. .usage = "['arm'|'thumb']",
  858. .help = "display/change ARM core state",
  859. },
  860. {
  861. .name = "disassemble",
  862. .handler = handle_arm_disassemble_command,
  863. .mode = COMMAND_EXEC,
  864. .usage = "address [count ['thumb']]",
  865. .help = "disassemble instructions ",
  866. },
  867. {
  868. .name = "mcr",
  869. .mode = COMMAND_EXEC,
  870. .jim_handler = &jim_mcrmrc,
  871. .help = "write coprocessor register",
  872. .usage = "cpnum op1 CRn op2 CRm value",
  873. },
  874. {
  875. .name = "mrc",
  876. .jim_handler = &jim_mcrmrc,
  877. .help = "read coprocessor register",
  878. .usage = "cpnum op1 CRn op2 CRm",
  879. },
  880. {
  881. "semihosting",
  882. .handler = handle_arm_semihosting_command,
  883. .mode = COMMAND_EXEC,
  884. .usage = "['enable'|'disable']",
  885. .help = "activate support for semihosting operations",
  886. },
  887. COMMAND_REGISTRATION_DONE
  888. };
  889. const struct command_registration arm_command_handlers[] = {
  890. {
  891. .name = "arm",
  892. .mode = COMMAND_ANY,
  893. .help = "ARM command group",
  894. .usage = "",
  895. .chain = arm_exec_command_handlers,
  896. },
  897. COMMAND_REGISTRATION_DONE
  898. };
  899. int arm_get_gdb_reg_list(struct target *target,
  900. struct reg **reg_list[], int *reg_list_size)
  901. {
  902. struct arm *arm = target_to_arm(target);
  903. int i;
  904. if (!is_arm_mode(arm->core_mode)) {
  905. LOG_ERROR("not a valid arm core mode - communication failure?");
  906. return ERROR_FAIL;
  907. }
  908. *reg_list_size = 26;
  909. *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
  910. for (i = 0; i < 16; i++)
  911. (*reg_list)[i] = arm_reg_current(arm, i);
  912. for (i = 16; i < 24; i++)
  913. (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
  914. (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
  915. (*reg_list)[25] = arm->cpsr;
  916. return ERROR_OK;
  917. }
  918. /* wait for execution to complete and check exit point */
  919. static int armv4_5_run_algorithm_completion(struct target *target,
  920. uint32_t exit_point,
  921. int timeout_ms,
  922. void *arch_info)
  923. {
  924. int retval;
  925. struct arm *arm = target_to_arm(target);
  926. retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
  927. if (retval != ERROR_OK)
  928. return retval;
  929. if (target->state != TARGET_HALTED) {
  930. retval = target_halt(target);
  931. if (retval != ERROR_OK)
  932. return retval;
  933. retval = target_wait_state(target, TARGET_HALTED, 500);
  934. if (retval != ERROR_OK)
  935. return retval;
  936. return ERROR_TARGET_TIMEOUT;
  937. }
  938. /* fast exit: ARMv5+ code can use BKPT */
  939. if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) {
  940. LOG_WARNING(
  941. "target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
  942. buf_get_u32(arm->pc->value, 0, 32));
  943. return ERROR_TARGET_TIMEOUT;
  944. }
  945. return ERROR_OK;
  946. }
  947. int armv4_5_run_algorithm_inner(struct target *target,
  948. int num_mem_params, struct mem_param *mem_params,
  949. int num_reg_params, struct reg_param *reg_params,
  950. uint32_t entry_point, uint32_t exit_point,
  951. int timeout_ms, void *arch_info,
  952. int (*run_it)(struct target *target, uint32_t exit_point,
  953. int timeout_ms, void *arch_info))
  954. {
  955. struct arm *arm = target_to_arm(target);
  956. struct arm_algorithm *arm_algorithm_info = arch_info;
  957. enum arm_state core_state = arm->core_state;
  958. uint32_t context[17];
  959. uint32_t cpsr;
  960. int exit_breakpoint_size = 0;
  961. int i;
  962. int retval = ERROR_OK;
  963. LOG_DEBUG("Running algorithm");
  964. if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) {
  965. LOG_ERROR("current target isn't an ARMV4/5 target");
  966. return ERROR_TARGET_INVALID;
  967. }
  968. if (target->state != TARGET_HALTED) {
  969. LOG_WARNING("target not halted");
  970. return ERROR_TARGET_NOT_HALTED;
  971. }
  972. if (!is_arm_mode(arm->core_mode)) {
  973. LOG_ERROR("not a valid arm core mode - communication failure?");
  974. return ERROR_FAIL;
  975. }
  976. /* armv5 and later can terminate with BKPT instruction; less overhead */
  977. if (!exit_point && arm->is_armv4) {
  978. LOG_ERROR("ARMv4 target needs HW breakpoint location");
  979. return ERROR_FAIL;
  980. }
  981. /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
  982. * they'll be restored later.
  983. */
  984. for (i = 0; i <= 16; i++) {
  985. struct reg *r;
  986. r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
  987. arm_algorithm_info->core_mode, i);
  988. if (!r->valid)
  989. arm->read_core_reg(target, r, i,
  990. arm_algorithm_info->core_mode);
  991. context[i] = buf_get_u32(r->value, 0, 32);
  992. }
  993. cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
  994. for (i = 0; i < num_mem_params; i++) {
  995. retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size,
  996. mem_params[i].value);
  997. if (retval != ERROR_OK)
  998. return retval;
  999. }
  1000. for (i = 0; i < num_reg_params; i++) {
  1001. struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
  1002. if (!reg) {
  1003. LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
  1004. return ERROR_COMMAND_SYNTAX_ERROR;
  1005. }
  1006. if (reg->size != reg_params[i].size) {
  1007. LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
  1008. reg_params[i].reg_name);
  1009. return ERROR_COMMAND_SYNTAX_ERROR;
  1010. }
  1011. retval = armv4_5_set_core_reg(reg, reg_params[i].value);
  1012. if (retval != ERROR_OK)
  1013. return retval;
  1014. }
  1015. arm->core_state = arm_algorithm_info->core_state;
  1016. if (arm->core_state == ARM_STATE_ARM)
  1017. exit_breakpoint_size = 4;
  1018. else if (arm->core_state == ARM_STATE_THUMB)
  1019. exit_breakpoint_size = 2;
  1020. else {
  1021. LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
  1022. return ERROR_COMMAND_SYNTAX_ERROR;
  1023. }
  1024. if (arm_algorithm_info->core_mode != ARM_MODE_ANY) {
  1025. LOG_DEBUG("setting core_mode: 0x%2.2x",
  1026. arm_algorithm_info->core_mode);
  1027. buf_set_u32(arm->cpsr->value, 0, 5,
  1028. arm_algorithm_info->core_mode);
  1029. arm->cpsr->dirty = 1;
  1030. arm->cpsr->valid = 1;
  1031. }
  1032. /* terminate using a hardware or (ARMv5+) software breakpoint */
  1033. if (exit_point) {
  1034. retval = breakpoint_add(target, exit_point,
  1035. exit_breakpoint_size, BKPT_HARD);
  1036. if (retval != ERROR_OK) {
  1037. LOG_ERROR("can't add HW breakpoint to terminate algorithm");
  1038. return ERROR_TARGET_FAILURE;
  1039. }
  1040. }
  1041. retval = target_resume(target, 0, entry_point, 1, 1);
  1042. if (retval != ERROR_OK)
  1043. return retval;
  1044. retval = run_it(target, exit_point, timeout_ms, arch_info);
  1045. if (exit_point)
  1046. breakpoint_remove(target, exit_point);
  1047. if (retval != ERROR_OK)
  1048. return retval;
  1049. for (i = 0; i < num_mem_params; i++) {
  1050. if (mem_params[i].direction != PARAM_OUT) {
  1051. int retvaltemp = target_read_buffer(target, mem_params[i].address,
  1052. mem_params[i].size,
  1053. mem_params[i].value);
  1054. if (retvaltemp != ERROR_OK)
  1055. retval = retvaltemp;
  1056. }
  1057. }
  1058. for (i = 0; i < num_reg_params; i++) {
  1059. if (reg_params[i].direction != PARAM_OUT) {
  1060. struct reg *reg = register_get_by_name(arm->core_cache,
  1061. reg_params[i].reg_name,
  1062. 0);
  1063. if (!reg) {
  1064. LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
  1065. retval = ERROR_COMMAND_SYNTAX_ERROR;
  1066. continue;
  1067. }
  1068. if (reg->size != reg_params[i].size) {
  1069. LOG_ERROR(
  1070. "BUG: register '%s' size doesn't match reg_params[i].size",
  1071. reg_params[i].reg_name);
  1072. retval = ERROR_COMMAND_SYNTAX_ERROR;
  1073. continue;
  1074. }
  1075. buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
  1076. }
  1077. }
  1078. /* restore everything we saved before (17 or 18 registers) */
  1079. for (i = 0; i <= 16; i++) {
  1080. uint32_t regvalue;
  1081. regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
  1082. arm_algorithm_info->core_mode, i).value, 0, 32);
  1083. if (regvalue != context[i]) {
  1084. LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
  1085. ARMV4_5_CORE_REG_MODE(arm->core_cache,
  1086. arm_algorithm_info->core_mode, i).name, context[i]);
  1087. buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
  1088. arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
  1089. ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
  1090. i).valid = 1;
  1091. ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
  1092. i).dirty = 1;
  1093. }
  1094. }
  1095. arm_set_cpsr(arm, cpsr);
  1096. arm->cpsr->dirty = 1;
  1097. arm->core_state = core_state;
  1098. return retval;
  1099. }
  1100. int armv4_5_run_algorithm(struct target *target,
  1101. int num_mem_params,
  1102. struct mem_param *mem_params,
  1103. int num_reg_params,
  1104. struct reg_param *reg_params,
  1105. uint32_t entry_point,
  1106. uint32_t exit_point,
  1107. int timeout_ms,
  1108. void *arch_info)
  1109. {
  1110. return armv4_5_run_algorithm_inner(target,
  1111. num_mem_params,
  1112. mem_params,
  1113. num_reg_params,
  1114. reg_params,
  1115. entry_point,
  1116. exit_point,
  1117. timeout_ms,
  1118. arch_info,
  1119. armv4_5_run_algorithm_completion);
  1120. }
  1121. /**
  1122. * Runs ARM code in the target to calculate a CRC32 checksum.
  1123. *
  1124. */
  1125. int arm_checksum_memory(struct target *target,
  1126. uint32_t address, uint32_t count, uint32_t *checksum)
  1127. {
  1128. struct working_area *crc_algorithm;
  1129. struct arm_algorithm armv4_5_info;
  1130. struct arm *arm = target_to_arm(target);
  1131. struct reg_param reg_params[2];
  1132. int retval;
  1133. uint32_t i;
  1134. uint32_t exit_var = 0;
  1135. /* see contrib/loaders/checksum/armv4_5_crc.s for src */
  1136. static const uint32_t arm_crc_code[] = {
  1137. 0xE1A02000, /* mov r2, r0 */
  1138. 0xE3E00000, /* mov r0, #0xffffffff */
  1139. 0xE1A03001, /* mov r3, r1 */
  1140. 0xE3A04000, /* mov r4, #0 */
  1141. 0xEA00000B, /* b ncomp */
  1142. /* nbyte: */
  1143. 0xE7D21004, /* ldrb r1, [r2, r4] */
  1144. 0xE59F7030, /* ldr r7, CRC32XOR */
  1145. 0xE0200C01, /* eor r0, r0, r1, asl 24 */
  1146. 0xE3A05000, /* mov r5, #0 */
  1147. /* loop: */
  1148. 0xE3500000, /* cmp r0, #0 */
  1149. 0xE1A06080, /* mov r6, r0, asl #1 */
  1150. 0xE2855001, /* add r5, r5, #1 */
  1151. 0xE1A00006, /* mov r0, r6 */
  1152. 0xB0260007, /* eorlt r0, r6, r7 */
  1153. 0xE3550008, /* cmp r5, #8 */
  1154. 0x1AFFFFF8, /* bne loop */
  1155. 0xE2844001, /* add r4, r4, #1 */
  1156. /* ncomp: */
  1157. 0xE1540003, /* cmp r4, r3 */
  1158. 0x1AFFFFF1, /* bne nbyte */
  1159. /* end: */
  1160. 0xe1200070, /* bkpt #0 */
  1161. /* CRC32XOR: */
  1162. 0x04C11DB7 /* .word 0x04C11DB7 */
  1163. };
  1164. retval = target_alloc_working_area(target,
  1165. sizeof(arm_crc_code), &crc_algorithm);
  1166. if (retval != ERROR_OK)
  1167. return retval;
  1168. /* convert code into a buffer in target endianness */
  1169. for (i = 0; i < ARRAY_SIZE(arm_crc_code); i++) {
  1170. retval = target_write_u32(target,
  1171. crc_algorithm->address + i * sizeof(uint32_t),
  1172. arm_crc_code[i]);
  1173. if (retval != ERROR_OK)
  1174. return retval;
  1175. }
  1176. armv4_5_info.common_magic = ARM_COMMON_MAGIC;
  1177. armv4_5_info.core_mode = ARM_MODE_SVC;
  1178. armv4_5_info.core_state = ARM_STATE_ARM;
  1179. init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
  1180. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  1181. buf_set_u32(reg_params[0].value, 0, 32, address);
  1182. buf_set_u32(reg_params[1].value, 0, 32, count);
  1183. /* 20 second timeout/megabyte */
  1184. int timeout = 20000 * (1 + (count / (1024 * 1024)));
  1185. /* armv4 must exit using a hardware breakpoint */
  1186. if (arm->is_armv4)
  1187. exit_var = crc_algorithm->address + sizeof(arm_crc_code) - 8;
  1188. retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
  1189. crc_algorithm->address,
  1190. exit_var,
  1191. timeout, &armv4_5_info);
  1192. if (retval != ERROR_OK) {
  1193. LOG_ERROR("error executing ARM crc algorithm");
  1194. destroy_reg_param(&reg_params[0]);
  1195. destroy_reg_param(&reg_params[1]);
  1196. target_free_working_area(target, crc_algorithm);
  1197. return retval;
  1198. }
  1199. *checksum = buf_get_u32(reg_params[0].value, 0, 32);
  1200. destroy_reg_param(&reg_params[0]);
  1201. destroy_reg_param(&reg_params[1]);
  1202. target_free_working_area(target, crc_algorithm);
  1203. return ERROR_OK;
  1204. }
  1205. /**
  1206. * Runs ARM code in the target to check whether a memory block holds
  1207. * all ones. NOR flash which has been erased, and thus may be written,
  1208. * holds all ones.
  1209. *
  1210. */
  1211. int arm_blank_check_memory(struct target *target,
  1212. uint32_t address, uint32_t count, uint32_t *blank)
  1213. {
  1214. struct working_area *check_algorithm;
  1215. struct reg_param reg_params[3];
  1216. struct arm_algorithm armv4_5_info;
  1217. struct arm *arm = target_to_arm(target);
  1218. int retval;
  1219. uint32_t i;
  1220. uint32_t exit_var = 0;
  1221. /* see contrib/loaders/erase_check/armv4_5_erase_check.s for src */
  1222. static const uint32_t check_code[] = {
  1223. /* loop: */
  1224. 0xe4d03001, /* ldrb r3, [r0], #1 */
  1225. 0xe0022003, /* and r2, r2, r3 */
  1226. 0xe2511001, /* subs r1, r1, #1 */
  1227. 0x1afffffb, /* bne loop */
  1228. /* end: */
  1229. 0xe1200070, /* bkpt #0 */
  1230. };
  1231. /* make sure we have a working area */
  1232. retval = target_alloc_working_area(target,
  1233. sizeof(check_code), &check_algorithm);
  1234. if (retval != ERROR_OK)
  1235. return retval;
  1236. /* convert code into a buffer in target endianness */
  1237. for (i = 0; i < ARRAY_SIZE(check_code); i++) {
  1238. retval = target_write_u32(target,
  1239. check_algorithm->address
  1240. + i * sizeof(uint32_t),
  1241. check_code[i]);
  1242. if (retval != ERROR_OK)
  1243. return retval;
  1244. }
  1245. armv4_5_info.common_magic = ARM_COMMON_MAGIC;
  1246. armv4_5_info.core_mode = ARM_MODE_SVC;
  1247. armv4_5_info.core_state = ARM_STATE_ARM;
  1248. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
  1249. buf_set_u32(reg_params[0].value, 0, 32, address);
  1250. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  1251. buf_set_u32(reg_params[1].value, 0, 32, count);
  1252. init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
  1253. buf_set_u32(reg_params[2].value, 0, 32, 0xff);
  1254. /* armv4 must exit using a hardware breakpoint */
  1255. if (arm->is_armv4)
  1256. exit_var = check_algorithm->address + sizeof(check_code) - 4;
  1257. retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
  1258. check_algorithm->address,
  1259. exit_var,
  1260. 10000, &armv4_5_info);
  1261. if (retval != ERROR_OK) {
  1262. destroy_reg_param(&reg_params[0]);
  1263. destroy_reg_param(&reg_params[1]);
  1264. destroy_reg_param(&reg_params[2]);
  1265. target_free_working_area(target, check_algorithm);
  1266. return retval;
  1267. }
  1268. *blank = buf_get_u32(reg_params[2].value, 0, 32);
  1269. destroy_reg_param(&reg_params[0]);
  1270. destroy_reg_param(&reg_params[1]);
  1271. destroy_reg_param(&reg_params[2]);
  1272. target_free_working_area(target, check_algorithm);
  1273. return ERROR_OK;
  1274. }
  1275. static int arm_full_context(struct target *target)
  1276. {
  1277. struct arm *arm = target_to_arm(target);
  1278. unsigned num_regs = arm->core_cache->num_regs;
  1279. struct reg *reg = arm->core_cache->reg_list;
  1280. int retval = ERROR_OK;
  1281. for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
  1282. if (reg->valid)
  1283. continue;
  1284. retval = armv4_5_get_core_reg(reg);
  1285. }
  1286. return retval;
  1287. }
  1288. static int arm_default_mrc(struct target *target, int cpnum,
  1289. uint32_t op1, uint32_t op2,
  1290. uint32_t CRn, uint32_t CRm,
  1291. uint32_t *value)
  1292. {
  1293. LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
  1294. return ERROR_FAIL;
  1295. }
  1296. static int arm_default_mcr(struct target *target, int cpnum,
  1297. uint32_t op1, uint32_t op2,
  1298. uint32_t CRn, uint32_t CRm,
  1299. uint32_t value)
  1300. {
  1301. LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
  1302. return ERROR_FAIL;
  1303. }
  1304. int arm_init_arch_info(struct target *target, struct arm *arm)
  1305. {
  1306. target->arch_info = arm;
  1307. arm->target = target;
  1308. arm->common_magic = ARM_COMMON_MAGIC;
  1309. /* core_type may be overridden by subtype logic */
  1310. if (arm->core_type != ARM_MODE_THREAD) {
  1311. arm->core_type = ARM_MODE_ANY;
  1312. arm_set_cpsr(arm, ARM_MODE_USR);
  1313. }
  1314. /* default full_context() has no core-specific optimizations */
  1315. if (!arm->full_context && arm->read_core_reg)
  1316. arm->full_context = arm_full_context;
  1317. if (!arm->mrc)
  1318. arm->mrc = arm_default_mrc;
  1319. if (!arm->mcr)
  1320. arm->mcr = arm_default_mcr;
  1321. return ERROR_OK;
  1322. }