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  1. /***************************************************************************
  2. * Copyright (C) 2009 by Duane Ellis *
  3. * openocd@duaneellis.com *
  4. * *
  5. * Copyright (C) 2010 by Olaf L√ľke (at91sam3s* support) *
  6. * olaf@uni-paderborn.de *
  7. * *
  8. * Copyright (C) 2011 by Olivier Schonken, Jim Norris *
  9. * (at91sam3x* & at91sam4 support)* *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
  19. * GNU General public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  25. ****************************************************************************/
  26. /* Some of the the lower level code was based on code supplied by
  27. * ATMEL under this copyright. */
  28. /* BEGIN ATMEL COPYRIGHT */
  29. /* ----------------------------------------------------------------------------
  30. * ATMEL Microcontroller Software Support
  31. * ----------------------------------------------------------------------------
  32. * Copyright (c) 2009, Atmel Corporation
  33. *
  34. * All rights reserved.
  35. *
  36. * Redistribution and use in source and binary forms, with or without
  37. * modification, are permitted provided that the following conditions are met:
  38. *
  39. * - Redistributions of source code must retain the above copyright notice,
  40. * this list of conditions and the disclaimer below.
  41. *
  42. * Atmel's name may not be used to endorse or promote products derived from
  43. * this software without specific prior written permission.
  44. *
  45. * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
  46. * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  47. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  48. * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
  49. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  50. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  51. * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  52. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  53. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  54. * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  55. * ----------------------------------------------------------------------------
  56. */
  57. /* END ATMEL COPYRIGHT */
  58. #ifdef HAVE_CONFIG_H
  59. #include "config.h"
  60. #endif
  61. #include "imp.h"
  62. #include <helper/time_support.h>
  63. #define REG_NAME_WIDTH (12)
  64. /* at91sam4s series (has always one flash bank)*/
  65. #define FLASH_BANK_BASE_S 0x00400000
  66. #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
  67. #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
  68. #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
  69. #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
  70. #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page
  71. * then Lock */
  72. #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
  73. /* cmd6 is not present int he at91sam4u4/2/1 data sheet table 19-2 */
  74. /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
  75. #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
  76. #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
  77. #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
  78. #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
  79. #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
  80. #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
  81. #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
  82. #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
  83. #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
  84. #define offset_EFC_FMR 0
  85. #define offset_EFC_FCR 4
  86. #define offset_EFC_FSR 8
  87. #define offset_EFC_FRR 12
  88. extern struct flash_driver at91sam4_flash;
  89. static float _tomhz(uint32_t freq_hz)
  90. {
  91. float f;
  92. f = ((float)(freq_hz)) / 1000000.0;
  93. return f;
  94. }
  95. /* How the chip is configured. */
  96. struct sam4_cfg {
  97. uint32_t unique_id[4];
  98. uint32_t slow_freq;
  99. uint32_t rc_freq;
  100. uint32_t mainosc_freq;
  101. uint32_t plla_freq;
  102. uint32_t mclk_freq;
  103. uint32_t cpu_freq;
  104. uint32_t fclk_freq;
  105. uint32_t pclk0_freq;
  106. uint32_t pclk1_freq;
  107. uint32_t pclk2_freq;
  108. #define SAM4_CHIPID_CIDR (0x400E0740)
  109. uint32_t CHIPID_CIDR;
  110. #define SAM4_CHIPID_EXID (0x400E0744)
  111. uint32_t CHIPID_EXID;
  112. #define SAM4_PMC_BASE (0x400E0400)
  113. #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
  114. uint32_t PMC_SCSR;
  115. #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
  116. uint32_t PMC_PCSR;
  117. #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
  118. uint32_t CKGR_UCKR;
  119. #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
  120. uint32_t CKGR_MOR;
  121. #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
  122. uint32_t CKGR_MCFR;
  123. #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
  124. uint32_t CKGR_PLLAR;
  125. #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
  126. uint32_t PMC_MCKR;
  127. #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
  128. uint32_t PMC_PCK0;
  129. #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
  130. uint32_t PMC_PCK1;
  131. #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
  132. uint32_t PMC_PCK2;
  133. #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
  134. uint32_t PMC_SR;
  135. #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
  136. uint32_t PMC_IMR;
  137. #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
  138. uint32_t PMC_FSMR;
  139. #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
  140. uint32_t PMC_FSPR;
  141. };
  142. struct sam4_bank_private {
  143. int probed;
  144. /* DANGER: THERE ARE DRAGONS HERE.. */
  145. /* NOTE: If you add more 'ghost' pointers */
  146. /* be aware that you must *manually* update */
  147. /* these pointers in the function sam4_GetDetails() */
  148. /* See the comment "Here there be dragons" */
  149. /* so we can find the chip we belong to */
  150. struct sam4_chip *pChip;
  151. /* so we can find the orginal bank pointer */
  152. struct flash_bank *pBank;
  153. unsigned bank_number;
  154. uint32_t controller_address;
  155. uint32_t base_address;
  156. uint32_t flash_wait_states;
  157. bool present;
  158. unsigned size_bytes;
  159. unsigned nsectors;
  160. unsigned sector_size;
  161. unsigned page_size;
  162. };
  163. struct sam4_chip_details {
  164. /* THERE ARE DRAGONS HERE.. */
  165. /* note: If you add pointers here */
  166. /* becareful about them as they */
  167. /* may need to be updated inside */
  168. /* the function: "sam4_GetDetails() */
  169. /* which copy/overwrites the */
  170. /* 'runtime' copy of this structure */
  171. uint32_t chipid_cidr;
  172. const char *name;
  173. unsigned n_gpnvms;
  174. #define SAM4_N_NVM_BITS 3
  175. unsigned gpnvm[SAM4_N_NVM_BITS];
  176. unsigned total_flash_size;
  177. unsigned total_sram_size;
  178. unsigned n_banks;
  179. #define SAM4_MAX_FLASH_BANKS 2
  180. /* these are "initialized" from the global const data */
  181. struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
  182. };
  183. struct sam4_chip {
  184. struct sam4_chip *next;
  185. int probed;
  186. /* this is "initialized" from the global const structure */
  187. struct sam4_chip_details details;
  188. struct target *target;
  189. struct sam4_cfg cfg;
  190. };
  191. struct sam4_reg_list {
  192. uint32_t address; size_t struct_offset; const char *name;
  193. void (*explain_func)(struct sam4_chip *pInfo);
  194. };
  195. static struct sam4_chip *all_sam4_chips;
  196. static struct sam4_chip *get_current_sam4(struct command_context *cmd_ctx)
  197. {
  198. struct target *t;
  199. static struct sam4_chip *p;
  200. t = get_current_target(cmd_ctx);
  201. if (!t) {
  202. command_print(cmd_ctx, "No current target?");
  203. return NULL;
  204. }
  205. p = all_sam4_chips;
  206. if (!p) {
  207. /* this should not happen */
  208. /* the command is not registered until the chip is created? */
  209. command_print(cmd_ctx, "No SAM4 chips exist?");
  210. return NULL;
  211. }
  212. while (p) {
  213. if (p->target == t)
  214. return p;
  215. p = p->next;
  216. }
  217. command_print(cmd_ctx, "Cannot find SAM4 chip?");
  218. return NULL;
  219. }
  220. /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
  221. /*The lockregions are 8KB per lock reqion, with a 1024KB device having 128 lock reqions. */
  222. /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
  223. /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
  224. /* these are used to *initialize* the "pChip->details" structure. */
  225. static const struct sam4_chip_details all_sam4_details[] = {
  226. /* Start at91sam4s* series */
  227. /*atsam4s16c - LQFP100/BGA100*/
  228. {
  229. .chipid_cidr = 0x28AC0CE0,
  230. .name = "at91sam4s16c",
  231. .total_flash_size = 1024 * 1024,
  232. .total_sram_size = 128 * 1024,
  233. .n_gpnvms = 2,
  234. .n_banks = 1,
  235. {
  236. /* .bank[0] = {*/
  237. {
  238. .probed = 0,
  239. .pChip = NULL,
  240. .pBank = NULL,
  241. .bank_number = 0,
  242. .base_address = FLASH_BANK_BASE_S,
  243. .controller_address = 0x400e0a00,
  244. .flash_wait_states = 6, /* workaround silicon bug */
  245. .present = 1,
  246. .size_bytes = 1024 * 1024,
  247. .nsectors = 128,
  248. .sector_size = 8192,
  249. .page_size = 512,
  250. },
  251. /* .bank[1] = {*/
  252. {
  253. .present = 0,
  254. .probed = 0,
  255. .bank_number = 1,
  256. },
  257. },
  258. },
  259. /*atsam4s16b - LQFP64/QFN64*/
  260. {
  261. .chipid_cidr = 0x289C0CE0,
  262. .name = "at91sam4s16b",
  263. .total_flash_size = 1024 * 1024,
  264. .total_sram_size = 128 * 1024,
  265. .n_gpnvms = 2,
  266. .n_banks = 1,
  267. {
  268. /* .bank[0] = {*/
  269. {
  270. .probed = 0,
  271. .pChip = NULL,
  272. .pBank = NULL,
  273. .bank_number = 0,
  274. .base_address = FLASH_BANK_BASE_S,
  275. .controller_address = 0x400e0a00,
  276. .flash_wait_states = 6, /* workaround silicon bug */
  277. .present = 1,
  278. .size_bytes = 1024 * 1024,
  279. .nsectors = 128,
  280. .sector_size = 8192,
  281. .page_size = 512,
  282. },
  283. /* .bank[1] = {*/
  284. {
  285. .present = 0,
  286. .probed = 0,
  287. .bank_number = 1,
  288. },
  289. },
  290. },
  291. /*atsam4s16a - LQFP48/QFN48*/
  292. {
  293. .chipid_cidr = 0x288C0CE0,
  294. .name = "at91sam4s16a",
  295. .total_flash_size = 1024 * 1024,
  296. .total_sram_size = 128 * 1024,
  297. .n_gpnvms = 2,
  298. .n_banks = 1,
  299. {
  300. /* .bank[0] = {*/
  301. {
  302. .probed = 0,
  303. .pChip = NULL,
  304. .pBank = NULL,
  305. .bank_number = 0,
  306. .base_address = FLASH_BANK_BASE_S,
  307. .controller_address = 0x400e0a00,
  308. .flash_wait_states = 6, /* workaround silicon bug */
  309. .present = 1,
  310. .size_bytes = 1024 * 1024,
  311. .nsectors = 128,
  312. .sector_size = 8192,
  313. .page_size = 512,
  314. },
  315. /* .bank[1] = {*/
  316. {
  317. .present = 0,
  318. .probed = 0,
  319. .bank_number = 1,
  320. },
  321. },
  322. },
  323. /*atsam4s8c - LQFP100/BGA100*/
  324. {
  325. .chipid_cidr = 0x28AC0AE0,
  326. .name = "at91sam4s8c",
  327. .total_flash_size = 512 * 1024,
  328. .total_sram_size = 128 * 1024,
  329. .n_gpnvms = 2,
  330. .n_banks = 1,
  331. {
  332. /* .bank[0] = {*/
  333. {
  334. .probed = 0,
  335. .pChip = NULL,
  336. .pBank = NULL,
  337. .bank_number = 0,
  338. .base_address = FLASH_BANK_BASE_S,
  339. .controller_address = 0x400e0a00,
  340. .flash_wait_states = 6, /* workaround silicon bug */
  341. .present = 1,
  342. .size_bytes = 512 * 1024,
  343. .nsectors = 64,
  344. .sector_size = 8192,
  345. .page_size = 512,
  346. },
  347. /* .bank[1] = {*/
  348. {
  349. .present = 0,
  350. .probed = 0,
  351. .bank_number = 1,
  352. },
  353. },
  354. },
  355. /*atsam4s8b - LQFP64/BGA64*/
  356. {
  357. .chipid_cidr = 0x289C0AE0,
  358. .name = "at91sam4s8b",
  359. .total_flash_size = 512 * 1024,
  360. .total_sram_size = 128 * 1024,
  361. .n_gpnvms = 2,
  362. .n_banks = 1,
  363. {
  364. /* .bank[0] = {*/
  365. {
  366. .probed = 0,
  367. .pChip = NULL,
  368. .pBank = NULL,
  369. .bank_number = 0,
  370. .base_address = FLASH_BANK_BASE_S,
  371. .controller_address = 0x400e0a00,
  372. .flash_wait_states = 6, /* workaround silicon bug */
  373. .present = 1,
  374. .size_bytes = 512 * 1024,
  375. .nsectors = 64,
  376. .sector_size = 8192,
  377. .page_size = 512,
  378. },
  379. /* .bank[1] = {*/
  380. {
  381. .present = 0,
  382. .probed = 0,
  383. .bank_number = 1,
  384. },
  385. },
  386. },
  387. /*atsam4s8a - LQFP48/BGA48*/
  388. {
  389. .chipid_cidr = 0x288C0AE0,
  390. .name = "at91sam4s8a",
  391. .total_flash_size = 512 * 1024,
  392. .total_sram_size = 128 * 1024,
  393. .n_gpnvms = 2,
  394. .n_banks = 1,
  395. {
  396. /* .bank[0] = {*/
  397. {
  398. .probed = 0,
  399. .pChip = NULL,
  400. .pBank = NULL,
  401. .bank_number = 0,
  402. .base_address = FLASH_BANK_BASE_S,
  403. .controller_address = 0x400e0a00,
  404. .flash_wait_states = 6, /* workaround silicon bug */
  405. .present = 1,
  406. .size_bytes = 512 * 1024,
  407. .nsectors = 64,
  408. .sector_size = 8192,
  409. .page_size = 512,
  410. },
  411. /* .bank[1] = {*/
  412. {
  413. .present = 0,
  414. .probed = 0,
  415. .bank_number = 1,
  416. },
  417. },
  418. },
  419. /* terminate */
  420. {
  421. .chipid_cidr = 0,
  422. .name = NULL,
  423. }
  424. };
  425. /* Globals above */
  426. /***********************************************************************
  427. **********************************************************************
  428. **********************************************************************
  429. **********************************************************************
  430. **********************************************************************
  431. **********************************************************************/
  432. /* *ATMEL* style code - from the SAM4 driver code */
  433. /**
  434. * Get the current status of the EEFC and
  435. * the value of some status bits (LOCKE, PROGE).
  436. * @param pPrivate - info about the bank
  437. * @param v - result goes here
  438. */
  439. static int EFC_GetStatus(struct sam4_bank_private *pPrivate, uint32_t *v)
  440. {
  441. int r;
  442. r = target_read_u32(pPrivate->pChip->target,
  443. pPrivate->controller_address + offset_EFC_FSR,
  444. v);
  445. LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
  446. (unsigned int)(*v),
  447. ((unsigned int)((*v >> 2) & 1)),
  448. ((unsigned int)((*v >> 1) & 1)),
  449. ((unsigned int)((*v >> 0) & 1)));
  450. return r;
  451. }
  452. /**
  453. * Get the result of the last executed command.
  454. * @param pPrivate - info about the bank
  455. * @param v - result goes here
  456. */
  457. static int EFC_GetResult(struct sam4_bank_private *pPrivate, uint32_t *v)
  458. {
  459. int r;
  460. uint32_t rv;
  461. r = target_read_u32(pPrivate->pChip->target,
  462. pPrivate->controller_address + offset_EFC_FRR,
  463. &rv);
  464. if (v)
  465. *v = rv;
  466. LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
  467. return r;
  468. }
  469. static int EFC_StartCommand(struct sam4_bank_private *pPrivate,
  470. unsigned command, unsigned argument)
  471. {
  472. uint32_t n, v;
  473. int r;
  474. int retry;
  475. retry = 0;
  476. do_retry:
  477. /* Check command & argument */
  478. switch (command) {
  479. case AT91C_EFC_FCMD_WP:
  480. case AT91C_EFC_FCMD_WPL:
  481. case AT91C_EFC_FCMD_EWP:
  482. case AT91C_EFC_FCMD_EWPL:
  483. /* case AT91C_EFC_FCMD_EPL: */
  484. case AT91C_EFC_FCMD_EPA:
  485. case AT91C_EFC_FCMD_SLB:
  486. case AT91C_EFC_FCMD_CLB:
  487. n = (pPrivate->size_bytes / pPrivate->page_size);
  488. if (argument >= n)
  489. LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
  490. break;
  491. case AT91C_EFC_FCMD_SFB:
  492. case AT91C_EFC_FCMD_CFB:
  493. if (argument >= pPrivate->pChip->details.n_gpnvms) {
  494. LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
  495. pPrivate->pChip->details.n_gpnvms);
  496. }
  497. break;
  498. case AT91C_EFC_FCMD_GETD:
  499. case AT91C_EFC_FCMD_EA:
  500. case AT91C_EFC_FCMD_GLB:
  501. case AT91C_EFC_FCMD_GFB:
  502. case AT91C_EFC_FCMD_STUI:
  503. case AT91C_EFC_FCMD_SPUI:
  504. if (argument != 0)
  505. LOG_ERROR("Argument is meaningless for cmd: %d", command);
  506. break;
  507. default:
  508. LOG_ERROR("Unknown command %d", command);
  509. break;
  510. }
  511. if (command == AT91C_EFC_FCMD_SPUI) {
  512. /* this is a very special situation. */
  513. /* Situation (1) - error/retry - see below */
  514. /* And we are being called recursively */
  515. /* Situation (2) - normal, finished reading unique id */
  516. } else {
  517. /* it should be "ready" */
  518. EFC_GetStatus(pPrivate, &v);
  519. if (v & 1) {
  520. /* then it is ready */
  521. /* we go on */
  522. } else {
  523. if (retry) {
  524. /* we have done this before */
  525. /* the controller is not responding. */
  526. LOG_ERROR("flash controller(%d) is not ready! Error",
  527. pPrivate->bank_number);
  528. return ERROR_FAIL;
  529. } else {
  530. retry++;
  531. LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
  532. pPrivate->bank_number);
  533. /* we do that by issuing the *STOP* command */
  534. EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
  535. /* above is recursive, and further recursion is blocked by */
  536. /* if (command == AT91C_EFC_FCMD_SPUI) above */
  537. goto do_retry;
  538. }
  539. }
  540. }
  541. v = (0x5A << 24) | (argument << 8) | command;
  542. LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
  543. r = target_write_u32(pPrivate->pBank->target,
  544. pPrivate->controller_address + offset_EFC_FCR, v);
  545. if (r != ERROR_OK)
  546. LOG_DEBUG("Error Write failed");
  547. return r;
  548. }
  549. /**
  550. * Performs the given command and wait until its completion (or an error).
  551. * @param pPrivate - info about the bank
  552. * @param command - Command to perform.
  553. * @param argument - Optional command argument.
  554. * @param status - put command status bits here
  555. */
  556. static int EFC_PerformCommand(struct sam4_bank_private *pPrivate,
  557. unsigned command,
  558. unsigned argument,
  559. uint32_t *status)
  560. {
  561. int r;
  562. uint32_t v;
  563. long long ms_now, ms_end;
  564. /* default */
  565. if (status)
  566. *status = 0;
  567. r = EFC_StartCommand(pPrivate, command, argument);
  568. if (r != ERROR_OK)
  569. return r;
  570. ms_end = 10000 + timeval_ms();
  571. do {
  572. r = EFC_GetStatus(pPrivate, &v);
  573. if (r != ERROR_OK)
  574. return r;
  575. ms_now = timeval_ms();
  576. if (ms_now > ms_end) {
  577. /* error */
  578. LOG_ERROR("Command timeout");
  579. return ERROR_FAIL;
  580. }
  581. } while ((v & 1) == 0);
  582. /* error bits.. */
  583. if (status)
  584. *status = (v & 0x6);
  585. return ERROR_OK;
  586. }
  587. /**
  588. * Read the unique ID.
  589. * @param pPrivate - info about the bank
  590. * The unique ID is stored in the 'pPrivate' structure.
  591. */
  592. static int FLASHD_ReadUniqueID(struct sam4_bank_private *pPrivate)
  593. {
  594. int r;
  595. uint32_t v;
  596. int x;
  597. /* assume 0 */
  598. pPrivate->pChip->cfg.unique_id[0] = 0;
  599. pPrivate->pChip->cfg.unique_id[1] = 0;
  600. pPrivate->pChip->cfg.unique_id[2] = 0;
  601. pPrivate->pChip->cfg.unique_id[3] = 0;
  602. LOG_DEBUG("Begin");
  603. r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
  604. if (r < 0)
  605. return r;
  606. for (x = 0; x < 4; x++) {
  607. r = target_read_u32(pPrivate->pChip->target,
  608. pPrivate->pBank->base + (x * 4),
  609. &v);
  610. if (r < 0)
  611. return r;
  612. pPrivate->pChip->cfg.unique_id[x] = v;
  613. }
  614. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
  615. LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
  616. r,
  617. (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
  618. (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
  619. (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
  620. (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
  621. return r;
  622. }
  623. /**
  624. * Erases the entire flash.
  625. * @param pPrivate - the info about the bank.
  626. */
  627. static int FLASHD_EraseEntireBank(struct sam4_bank_private *pPrivate)
  628. {
  629. LOG_DEBUG("Here");
  630. return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
  631. }
  632. /**
  633. * Erases the entire flash.
  634. * @param pPrivate - the info about the bank.
  635. */
  636. static int FLASHD_ErasePages(struct sam4_bank_private *pPrivate,
  637. int firstPage,
  638. int numPages,
  639. uint32_t *status)
  640. {
  641. LOG_DEBUG("Here");
  642. uint8_t erasePages;
  643. switch (numPages) {
  644. case 4:
  645. erasePages = 0x00;
  646. break;
  647. case 8:
  648. erasePages = 0x01;
  649. break;
  650. case 16:
  651. erasePages = 0x02;
  652. break;
  653. case 32:
  654. erasePages = 0x03;
  655. break;
  656. default:
  657. erasePages = 0x00;
  658. break;
  659. }
  660. /* AT91C_EFC_FCMD_EPA
  661. * According to the datasheet FARG[15:2] defines the page from which
  662. * the erase will start.This page must be modulo 4, 8, 16 or 32
  663. * according to the number of pages to erase. FARG[1:0] defines the
  664. * number of pages to be erased. Previously (firstpage << 2) was used
  665. * to conform to this, seems it should not be shifted...
  666. */
  667. return EFC_PerformCommand(pPrivate,
  668. /* send Erase Page */
  669. AT91C_EFC_FCMD_EPA,
  670. (firstPage) | erasePages,
  671. status);
  672. }
  673. /**
  674. * Gets current GPNVM state.
  675. * @param pPrivate - info about the bank.
  676. * @param gpnvm - GPNVM bit index.
  677. * @param puthere - result stored here.
  678. */
  679. /* ------------------------------------------------------------------------------ */
  680. static int FLASHD_GetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
  681. {
  682. uint32_t v;
  683. int r;
  684. LOG_DEBUG("Here");
  685. if (pPrivate->bank_number != 0) {
  686. LOG_ERROR("GPNVM only works with Bank0");
  687. return ERROR_FAIL;
  688. }
  689. if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
  690. LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
  691. gpnvm, pPrivate->pChip->details.n_gpnvms);
  692. return ERROR_FAIL;
  693. }
  694. /* Get GPNVMs status */
  695. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
  696. if (r != ERROR_OK) {
  697. LOG_ERROR("Failed");
  698. return r;
  699. }
  700. r = EFC_GetResult(pPrivate, &v);
  701. if (puthere) {
  702. /* Check if GPNVM is set */
  703. /* get the bit and make it a 0/1 */
  704. *puthere = (v >> gpnvm) & 1;
  705. }
  706. return r;
  707. }
  708. /**
  709. * Clears the selected GPNVM bit.
  710. * @param pPrivate info about the bank
  711. * @param gpnvm GPNVM index.
  712. * @returns 0 if successful; otherwise returns an error code.
  713. */
  714. static int FLASHD_ClrGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
  715. {
  716. int r;
  717. unsigned v;
  718. LOG_DEBUG("Here");
  719. if (pPrivate->bank_number != 0) {
  720. LOG_ERROR("GPNVM only works with Bank0");
  721. return ERROR_FAIL;
  722. }
  723. if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
  724. LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
  725. gpnvm, pPrivate->pChip->details.n_gpnvms);
  726. return ERROR_FAIL;
  727. }
  728. r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
  729. if (r != ERROR_OK) {
  730. LOG_DEBUG("Failed: %d", r);
  731. return r;
  732. }
  733. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
  734. LOG_DEBUG("End: %d", r);
  735. return r;
  736. }
  737. /**
  738. * Sets the selected GPNVM bit.
  739. * @param pPrivate info about the bank
  740. * @param gpnvm GPNVM index.
  741. */
  742. static int FLASHD_SetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
  743. {
  744. int r;
  745. unsigned v;
  746. if (pPrivate->bank_number != 0) {
  747. LOG_ERROR("GPNVM only works with Bank0");
  748. return ERROR_FAIL;
  749. }
  750. if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
  751. LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
  752. gpnvm, pPrivate->pChip->details.n_gpnvms);
  753. return ERROR_FAIL;
  754. }
  755. r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
  756. if (r != ERROR_OK)
  757. return r;
  758. if (v) {
  759. /* already set */
  760. r = ERROR_OK;
  761. } else {
  762. /* set it */
  763. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
  764. }
  765. return r;
  766. }
  767. /**
  768. * Returns a bit field (at most 64) of locked regions within a page.
  769. * @param pPrivate info about the bank
  770. * @param v where to store locked bits
  771. */
  772. static int FLASHD_GetLockBits(struct sam4_bank_private *pPrivate, uint32_t *v)
  773. {
  774. int r;
  775. LOG_DEBUG("Here");
  776. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
  777. if (r == ERROR_OK) {
  778. EFC_GetResult(pPrivate, v);
  779. EFC_GetResult(pPrivate, v);
  780. EFC_GetResult(pPrivate, v);
  781. r = EFC_GetResult(pPrivate, v);
  782. }
  783. LOG_DEBUG("End: %d", r);
  784. return r;
  785. }
  786. /**
  787. * Unlocks all the regions in the given address range.
  788. * @param pPrivate info about the bank
  789. * @param start_sector first sector to unlock
  790. * @param end_sector last (inclusive) to unlock
  791. */
  792. static int FLASHD_Unlock(struct sam4_bank_private *pPrivate,
  793. unsigned start_sector,
  794. unsigned end_sector)
  795. {
  796. int r;
  797. uint32_t status;
  798. uint32_t pg;
  799. uint32_t pages_per_sector;
  800. pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
  801. /* Unlock all pages */
  802. while (start_sector <= end_sector) {
  803. pg = start_sector * pages_per_sector;
  804. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
  805. if (r != ERROR_OK)
  806. return r;
  807. start_sector++;
  808. }
  809. return ERROR_OK;
  810. }
  811. /**
  812. * Locks regions
  813. * @param pPrivate - info about the bank
  814. * @param start_sector - first sector to lock
  815. * @param end_sector - last sector (inclusive) to lock
  816. */
  817. static int FLASHD_Lock(struct sam4_bank_private *pPrivate,
  818. unsigned start_sector,
  819. unsigned end_sector)
  820. {
  821. uint32_t status;
  822. uint32_t pg;
  823. uint32_t pages_per_sector;
  824. int r;
  825. pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
  826. /* Lock all pages */
  827. while (start_sector <= end_sector) {
  828. pg = start_sector * pages_per_sector;
  829. r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
  830. if (r != ERROR_OK)
  831. return r;
  832. start_sector++;
  833. }
  834. return ERROR_OK;
  835. }
  836. /****** END SAM4 CODE ********/
  837. /* begin helpful debug code */
  838. /* print the fieldname, the field value, in dec & hex, and return field value */
  839. static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip,
  840. const char *regname,
  841. uint32_t value,
  842. unsigned shift,
  843. unsigned width)
  844. {
  845. uint32_t v;
  846. int hwidth, dwidth;
  847. /* extract the field */
  848. v = value >> shift;
  849. v = v & ((1 << width)-1);
  850. if (width <= 16) {
  851. hwidth = 4;
  852. dwidth = 5;
  853. } else {
  854. hwidth = 8;
  855. dwidth = 12;
  856. }
  857. /* show the basics */
  858. LOG_USER_N("\t%*s: %*d [0x%0*x] ",
  859. REG_NAME_WIDTH, regname,
  860. dwidth, v,
  861. hwidth, v);
  862. return v;
  863. }
  864. static const char _unknown[] = "unknown";
  865. static const char *const eproc_names[] = {
  866. _unknown, /* 0 */
  867. "arm946es", /* 1 */
  868. "arm7tdmi", /* 2 */
  869. "cortex-m3", /* 3 */
  870. "arm920t", /* 4 */
  871. "arm926ejs", /* 5 */
  872. "cortex-a5", /* 6 */
  873. "cortex-m4", /* 7 */
  874. _unknown, /* 8 */
  875. _unknown, /* 9 */
  876. _unknown, /* 10 */
  877. _unknown, /* 11 */
  878. _unknown, /* 12 */
  879. _unknown, /* 13 */
  880. _unknown, /* 14 */
  881. _unknown, /* 15 */
  882. };
  883. #define nvpsize2 nvpsize /* these two tables are identical */
  884. static const char *const nvpsize[] = {
  885. "none", /* 0 */
  886. "8K bytes", /* 1 */
  887. "16K bytes", /* 2 */
  888. "32K bytes", /* 3 */
  889. _unknown, /* 4 */
  890. "64K bytes", /* 5 */
  891. _unknown, /* 6 */
  892. "128K bytes", /* 7 */
  893. _unknown, /* 8 */
  894. "256K bytes", /* 9 */
  895. "512K bytes", /* 10 */
  896. _unknown, /* 11 */
  897. "1024K bytes", /* 12 */
  898. _unknown, /* 13 */
  899. "2048K bytes", /* 14 */
  900. _unknown, /* 15 */
  901. };
  902. static const char *const sramsize[] = {
  903. "48K Bytes", /* 0 */
  904. "1K Bytes", /* 1 */
  905. "2K Bytes", /* 2 */
  906. "6K Bytes", /* 3 */
  907. "112K Bytes", /* 4 */
  908. "4K Bytes", /* 5 */
  909. "80K Bytes", /* 6 */
  910. "160K Bytes", /* 7 */
  911. "8K Bytes", /* 8 */
  912. "16K Bytes", /* 9 */
  913. "32K Bytes", /* 10 */
  914. "64K Bytes", /* 11 */
  915. "128K Bytes", /* 12 */
  916. "256K Bytes", /* 13 */
  917. "96K Bytes", /* 14 */
  918. "512K Bytes", /* 15 */
  919. };
  920. static const struct archnames { unsigned value; const char *name; } archnames[] = {
  921. { 0x19, "AT91SAM9xx Series" },
  922. { 0x29, "AT91SAM9XExx Series" },
  923. { 0x34, "AT91x34 Series" },
  924. { 0x37, "CAP7 Series" },
  925. { 0x39, "CAP9 Series" },
  926. { 0x3B, "CAP11 Series" },
  927. { 0x40, "AT91x40 Series" },
  928. { 0x42, "AT91x42 Series" },
  929. { 0x55, "AT91x55 Series" },
  930. { 0x60, "AT91SAM7Axx Series" },
  931. { 0x61, "AT91SAM7AQxx Series" },
  932. { 0x63, "AT91x63 Series" },
  933. { 0x70, "AT91SAM7Sxx Series" },
  934. { 0x71, "AT91SAM7XCxx Series" },
  935. { 0x72, "AT91SAM7SExx Series" },
  936. { 0x73, "AT91SAM7Lxx Series" },
  937. { 0x75, "AT91SAM7Xxx Series" },
  938. { 0x76, "AT91SAM7SLxx Series" },
  939. { 0x80, "ATSAM3UxC Series (100-pin version)" },
  940. { 0x81, "ATSAM3UxE Series (144-pin version)" },
  941. { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
  942. { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
  943. { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
  944. { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
  945. { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
  946. { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
  947. { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
  948. { 0x92, "AT91x92 Series" },
  949. { 0x93, "ATSAM3NxA Series (48-pin version)" },
  950. { 0x94, "ATSAM3NxB Series (64-pin version)" },
  951. { 0x95, "ATSAM3NxC Series (100-pin version)" },
  952. { 0x98, "ATSAM3SDxA Series (48-pin version)" },
  953. { 0x99, "ATSAM3SDxB Series (64-pin version)" },
  954. { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
  955. { 0xA5, "ATSAM5A" },
  956. { 0xF0, "AT75Cxx Series" },
  957. { -1, NULL },
  958. };
  959. static const char *const nvptype[] = {
  960. "rom", /* 0 */
  961. "romless or onchip flash", /* 1 */
  962. "embedded flash memory",/* 2 */
  963. "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
  964. "sram emulating flash", /* 4 */
  965. _unknown, /* 5 */
  966. _unknown, /* 6 */
  967. _unknown, /* 7 */
  968. };
  969. static const char *_yes_or_no(uint32_t v)
  970. {
  971. if (v)
  972. return "YES";
  973. else
  974. return "NO";
  975. }
  976. static const char *const _rc_freq[] = {
  977. "4 MHz", "8 MHz", "12 MHz", "reserved"
  978. };
  979. static void sam4_explain_ckgr_mor(struct sam4_chip *pChip)
  980. {
  981. uint32_t v;
  982. uint32_t rcen;
  983. v = sam4_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
  984. LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
  985. v = sam4_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
  986. LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
  987. rcen = sam4_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
  988. LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
  989. v = sam4_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
  990. LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
  991. pChip->cfg.rc_freq = 0;
  992. if (rcen) {
  993. switch (v) {
  994. default:
  995. pChip->cfg.rc_freq = 0;
  996. break;
  997. case 0:
  998. pChip->cfg.rc_freq = 4 * 1000 * 1000;
  999. break;
  1000. case 1:
  1001. pChip->cfg.rc_freq = 8 * 1000 * 1000;
  1002. break;
  1003. case 2:
  1004. pChip->cfg.rc_freq = 12 * 1000 * 1000;
  1005. break;
  1006. }
  1007. }
  1008. v = sam4_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
  1009. LOG_USER("(startup clks, time= %f uSecs)",
  1010. ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
  1011. v = sam4_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
  1012. LOG_USER("(mainosc source: %s)",
  1013. v ? "external xtal" : "internal RC");
  1014. v = sam4_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
  1015. LOG_USER("(clock failure enabled: %s)",
  1016. _yes_or_no(v));
  1017. }
  1018. static void sam4_explain_chipid_cidr(struct sam4_chip *pChip)
  1019. {
  1020. int x;
  1021. uint32_t v;
  1022. const char *cp;
  1023. sam4_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
  1024. LOG_USER_N("\n");
  1025. v = sam4_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
  1026. LOG_USER("%s", eproc_names[v]);
  1027. v = sam4_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
  1028. LOG_USER("%s", nvpsize[v]);
  1029. v = sam4_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
  1030. LOG_USER("%s", nvpsize2[v]);
  1031. v = sam4_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
  1032. LOG_USER("%s", sramsize[v]);
  1033. v = sam4_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
  1034. cp = _unknown;
  1035. for (x = 0; archnames[x].name; x++) {
  1036. if (v == archnames[x].value) {
  1037. cp = archnames[x].name;
  1038. break;
  1039. }
  1040. }
  1041. LOG_USER("%s", cp);
  1042. v = sam4_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
  1043. LOG_USER("%s", nvptype[v]);
  1044. v = sam4_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
  1045. LOG_USER("(exists: %s)", _yes_or_no(v));
  1046. }
  1047. static void sam4_explain_ckgr_mcfr(struct sam4_chip *pChip)
  1048. {
  1049. uint32_t v;
  1050. v = sam4_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
  1051. LOG_USER("(main ready: %s)", _yes_or_no(v));
  1052. v = sam4_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
  1053. v = (v * pChip->cfg.slow_freq) / 16;
  1054. pChip->cfg.mainosc_freq = v;
  1055. LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
  1056. _tomhz(v),
  1057. pChip->cfg.slow_freq / 1000,
  1058. pChip->cfg.slow_freq % 1000);
  1059. }
  1060. static void sam4_explain_ckgr_plla(struct sam4_chip *pChip)
  1061. {
  1062. uint32_t mula, diva;
  1063. diva = sam4_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
  1064. LOG_USER_N("\n");
  1065. mula = sam4_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
  1066. LOG_USER_N("\n");
  1067. pChip->cfg.plla_freq = 0;
  1068. if (mula == 0)
  1069. LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
  1070. else if (diva == 0)
  1071. LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
  1072. else if (diva == 1) {
  1073. pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
  1074. LOG_USER("\tPLLA Freq: %3.03f MHz",
  1075. _tomhz(pChip->cfg.plla_freq));
  1076. }
  1077. }
  1078. static void sam4_explain_mckr(struct sam4_chip *pChip)
  1079. {
  1080. uint32_t css, pres, fin = 0;
  1081. int pdiv = 0;
  1082. const char *cp = NULL;
  1083. css = sam4_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
  1084. switch (css & 3) {
  1085. case 0:
  1086. fin = pChip->cfg.slow_freq;
  1087. cp = "slowclk";
  1088. break;
  1089. case 1:
  1090. fin = pChip->cfg.mainosc_freq;
  1091. cp = "mainosc";
  1092. break;
  1093. case 2:
  1094. fin = pChip->cfg.plla_freq;
  1095. cp = "plla";
  1096. break;
  1097. case 3:
  1098. if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
  1099. fin = 480 * 1000 * 1000;
  1100. cp = "upll";
  1101. } else {
  1102. fin = 0;
  1103. cp = "upll (*ERROR* UPLL is disabled)";
  1104. }
  1105. break;
  1106. default:
  1107. assert(0);
  1108. break;
  1109. }
  1110. LOG_USER("%s (%3.03f Mhz)",
  1111. cp,
  1112. _tomhz(fin));
  1113. pres = sam4_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
  1114. switch (pres & 0x07) {
  1115. case 0:
  1116. pdiv = 1;
  1117. cp = "selected clock";
  1118. break;
  1119. case 1:
  1120. pdiv = 2;
  1121. cp = "clock/2";
  1122. break;
  1123. case 2:
  1124. pdiv = 4;
  1125. cp = "clock/4";
  1126. break;
  1127. case 3:
  1128. pdiv = 8;
  1129. cp = "clock/8";
  1130. break;
  1131. case 4:
  1132. pdiv = 16;
  1133. cp = "clock/16";
  1134. break;
  1135. case 5:
  1136. pdiv = 32;
  1137. cp = "clock/32";
  1138. break;
  1139. case 6:
  1140. pdiv = 64;
  1141. cp = "clock/64";
  1142. break;
  1143. case 7:
  1144. pdiv = 6;
  1145. cp = "clock/6";
  1146. break;
  1147. default:
  1148. assert(0);
  1149. break;
  1150. }
  1151. LOG_USER("(%s)", cp);
  1152. fin = fin / pdiv;
  1153. /* sam4 has a *SINGLE* clock - */
  1154. /* other at91 series parts have divisors for these. */
  1155. pChip->cfg.cpu_freq = fin;
  1156. pChip->cfg.mclk_freq = fin;
  1157. pChip->cfg.fclk_freq = fin;
  1158. LOG_USER("\t\tResult CPU Freq: %3.03f",
  1159. _tomhz(fin));
  1160. }
  1161. #if 0
  1162. static struct sam4_chip *target2sam4(struct target *pTarget)
  1163. {
  1164. struct sam4_chip *pChip;
  1165. if (pTarget == NULL)
  1166. return NULL;
  1167. pChip = all_sam4_chips;
  1168. while (pChip) {
  1169. if (pChip->target == pTarget)
  1170. break; /* return below */
  1171. else
  1172. pChip = pChip->next;
  1173. }
  1174. return pChip;
  1175. }
  1176. #endif
  1177. static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *pCfg, const struct sam4_reg_list *pList)
  1178. {
  1179. /* this function exists to help */
  1180. /* keep funky offsetof() errors */
  1181. /* and casting from causing bugs */
  1182. /* By using prototypes - we can detect what would */
  1183. /* be casting errors. */
  1184. return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
  1185. }
  1186. #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
  1187. struct sam4_cfg, \
  1188. NAME), # NAME, FUNC }
  1189. static const struct sam4_reg_list sam4_all_regs[] = {
  1190. SAM4_ENTRY(CKGR_MOR, sam4_explain_ckgr_mor),
  1191. SAM4_ENTRY(CKGR_MCFR, sam4_explain_ckgr_mcfr),
  1192. SAM4_ENTRY(CKGR_PLLAR, sam4_explain_ckgr_plla),
  1193. SAM4_ENTRY(CKGR_UCKR, NULL),
  1194. SAM4_ENTRY(PMC_FSMR, NULL),
  1195. SAM4_ENTRY(PMC_FSPR, NULL),
  1196. SAM4_ENTRY(PMC_IMR, NULL),
  1197. SAM4_ENTRY(PMC_MCKR, sam4_explain_mckr),
  1198. SAM4_ENTRY(PMC_PCK0, NULL),
  1199. SAM4_ENTRY(PMC_PCK1, NULL),
  1200. SAM4_ENTRY(PMC_PCK2, NULL),
  1201. SAM4_ENTRY(PMC_PCSR, NULL),
  1202. SAM4_ENTRY(PMC_SCSR, NULL),
  1203. SAM4_ENTRY(PMC_SR, NULL),
  1204. SAM4_ENTRY(CHIPID_CIDR, sam4_explain_chipid_cidr),
  1205. SAM4_ENTRY(CHIPID_EXID, NULL),
  1206. /* TERMINATE THE LIST */
  1207. { .name = NULL }
  1208. };
  1209. #undef SAM4_ENTRY
  1210. static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
  1211. {
  1212. return (struct sam4_bank_private *)(bank->driver_priv);
  1213. }
  1214. /**
  1215. * Given a pointer to where it goes in the structure,
  1216. * determine the register name, address from the all registers table.
  1217. */
  1218. static const struct sam4_reg_list *sam4_GetReg(struct sam4_chip *pChip, uint32_t *goes_here)
  1219. {
  1220. const struct sam4_reg_list *pReg;
  1221. pReg = &(sam4_all_regs[0]);
  1222. while (pReg->name) {
  1223. uint32_t *pPossible;
  1224. /* calculate where this one go.. */
  1225. /* it is "possibly" this register. */
  1226. pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
  1227. /* well? Is it this register */
  1228. if (pPossible == goes_here) {
  1229. /* Jump for joy! */
  1230. return pReg;
  1231. }
  1232. /* next... */
  1233. pReg++;
  1234. }
  1235. /* This is *TOTAL*PANIC* - we are totally screwed. */
  1236. LOG_ERROR("INVALID SAM4 REGISTER");
  1237. return NULL;
  1238. }
  1239. static int sam4_ReadThisReg(struct sam4_chip *pChip, uint32_t *goes_here)
  1240. {
  1241. const struct sam4_reg_list *pReg;
  1242. int r;
  1243. pReg = sam4_GetReg(pChip, goes_here);
  1244. if (!pReg)
  1245. return ERROR_FAIL;
  1246. r = target_read_u32(pChip->target, pReg->address, goes_here);
  1247. if (r != ERROR_OK) {
  1248. LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
  1249. pReg->name, (unsigned)(pReg->address), r);
  1250. }
  1251. return r;
  1252. }
  1253. static int sam4_ReadAllRegs(struct sam4_chip *pChip)
  1254. {
  1255. int r;
  1256. const struct sam4_reg_list *pReg;
  1257. pReg = &(sam4_all_regs[0]);
  1258. while (pReg->name) {
  1259. r = sam4_ReadThisReg(pChip,
  1260. sam4_get_reg_ptr(&(pChip->cfg), pReg));
  1261. if (r != ERROR_OK) {
  1262. LOG_ERROR("Cannot read SAM4 registere: %s @ 0x%08x, Error: %d",
  1263. pReg->name, ((unsigned)(pReg->address)), r);
  1264. return r;
  1265. }
  1266. pReg++;
  1267. }
  1268. return ERROR_OK;
  1269. }
  1270. static int sam4_GetInfo(struct sam4_chip *pChip)
  1271. {
  1272. const struct sam4_reg_list *pReg;
  1273. uint32_t regval;
  1274. pReg = &(sam4_all_regs[0]);
  1275. while (pReg->name) {
  1276. /* display all regs */
  1277. LOG_DEBUG("Start: %s", pReg->name);
  1278. regval = *sam4_get_reg_ptr(&(pChip->cfg), pReg);
  1279. LOG_USER("%*s: [0x%08x] -> 0x%08x",
  1280. REG_NAME_WIDTH,
  1281. pReg->name,
  1282. pReg->address,
  1283. regval);
  1284. if (pReg->explain_func)
  1285. (*(pReg->explain_func))(pChip);
  1286. LOG_DEBUG("End: %s", pReg->name);
  1287. pReg++;
  1288. }
  1289. LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
  1290. LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
  1291. LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
  1292. LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
  1293. LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
  1294. LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
  1295. pChip->cfg.unique_id[0],
  1296. pChip->cfg.unique_id[1],
  1297. pChip->cfg.unique_id[2],
  1298. pChip->cfg.unique_id[3]);
  1299. return ERROR_OK;
  1300. }
  1301. static int sam4_protect_check(struct flash_bank *bank)
  1302. {
  1303. int r;
  1304. uint32_t v[4] = {0};
  1305. unsigned x;
  1306. struct sam4_bank_private *pPrivate;
  1307. LOG_DEBUG("Begin");
  1308. if (bank->target->state != TARGET_HALTED) {
  1309. LOG_ERROR("Target not halted");
  1310. return ERROR_TARGET_NOT_HALTED;
  1311. }
  1312. pPrivate = get_sam4_bank_private(bank);
  1313. if (!pPrivate) {
  1314. LOG_ERROR("no private for this bank?");
  1315. return ERROR_FAIL;
  1316. }
  1317. if (!(pPrivate->probed))
  1318. return ERROR_FLASH_BANK_NOT_PROBED;
  1319. r = FLASHD_GetLockBits(pPrivate, v);
  1320. if (r != ERROR_OK) {
  1321. LOG_DEBUG("Failed: %d", r);
  1322. return r;
  1323. }
  1324. for (x = 0; x < pPrivate->nsectors; x++)
  1325. bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
  1326. LOG_DEBUG("Done");
  1327. return ERROR_OK;
  1328. }
  1329. FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
  1330. {
  1331. struct sam4_chip *pChip;
  1332. pChip = all_sam4_chips;
  1333. /* is this an existing chip? */
  1334. while (pChip) {
  1335. if (pChip->target == bank->target)
  1336. break;
  1337. pChip = pChip->next;
  1338. }
  1339. if (!pChip) {
  1340. /* this is a *NEW* chip */
  1341. pChip = calloc(1, sizeof(struct sam4_chip));
  1342. if (!pChip) {
  1343. LOG_ERROR("NO RAM!");
  1344. return ERROR_FAIL;
  1345. }
  1346. pChip->target = bank->target;
  1347. /* insert at head */
  1348. pChip->next = all_sam4_chips;
  1349. all_sam4_chips = pChip;
  1350. pChip->target = bank->target;
  1351. /* assumption is this runs at 32khz */
  1352. pChip->cfg.slow_freq = 32768;
  1353. pChip->probed = 0;
  1354. }
  1355. switch (bank->base) {
  1356. default:
  1357. LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
  1358. "[at91sam4s series] )",
  1359. ((unsigned int)(bank->base)),
  1360. ((unsigned int)(FLASH_BANK_BASE_S)));
  1361. return ERROR_FAIL;
  1362. break;
  1363. /* at91sam4s series only has bank 0*/
  1364. case FLASH_BANK_BASE_S:
  1365. bank->driver_priv = &(pChip->details.bank[0]);
  1366. bank->bank_number = 0;
  1367. pChip->details.bank[0].pChip = pChip;
  1368. pChip->details.bank[0].pBank = bank;
  1369. break;
  1370. }
  1371. /* we initialize after probing. */
  1372. return ERROR_OK;
  1373. }
  1374. static int sam4_GetDetails(struct sam4_bank_private *pPrivate)
  1375. {
  1376. const struct sam4_chip_details *pDetails;
  1377. struct sam4_chip *pChip;
  1378. struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
  1379. unsigned x;
  1380. LOG_DEBUG("Begin");
  1381. pDetails = all_sam4_details;
  1382. while (pDetails->name) {
  1383. /* Compare cidr without version bits */
  1384. if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
  1385. break;
  1386. else
  1387. pDetails++;
  1388. }
  1389. if (pDetails->name == NULL) {
  1390. LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
  1391. (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
  1392. /* Help the victim, print details about the chip */
  1393. LOG_INFO("SAM4 CHIPID_CIDR: 0x%08x decodes as follows",
  1394. pPrivate->pChip->cfg.CHIPID_CIDR);
  1395. sam4_explain_chipid_cidr(pPrivate->pChip);
  1396. return ERROR_FAIL;
  1397. }
  1398. /* DANGER: THERE ARE DRAGONS HERE */
  1399. /* get our pChip - it is going */
  1400. /* to be over-written shortly */
  1401. pChip = pPrivate->pChip;
  1402. /* Note that, in reality: */
  1403. /* */
  1404. /* pPrivate = &(pChip->details.bank[0]) */
  1405. /* or pPrivate = &(pChip->details.bank[1]) */
  1406. /* */
  1407. /* save the "bank" pointers */
  1408. for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
  1409. saved_banks[x] = pChip->details.bank[x].pBank;
  1410. /* Overwrite the "details" structure. */
  1411. memcpy(&(pPrivate->pChip->details),
  1412. pDetails,
  1413. sizeof(pPrivate->pChip->details));
  1414. /* now fix the ghosted pointers */
  1415. for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
  1416. pChip->details.bank[x].pChip = pChip;
  1417. pChip->details.bank[x].pBank = saved_banks[x];
  1418. }
  1419. /* update the *BANK*SIZE* */
  1420. LOG_DEBUG("End");
  1421. return ERROR_OK;
  1422. }
  1423. static int _sam4_probe(struct flash_bank *bank, int noise)
  1424. {
  1425. unsigned x;
  1426. int r;
  1427. struct sam4_bank_private *pPrivate;
  1428. LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
  1429. if (bank->target->state != TARGET_HALTED) {
  1430. LOG_ERROR("Target not halted");
  1431. return ERROR_TARGET_NOT_HALTED;
  1432. }
  1433. pPrivate = get_sam4_bank_private(bank);
  1434. if (!pPrivate) {
  1435. LOG_ERROR("Invalid/unknown bank number");
  1436. return ERROR_FAIL;
  1437. }
  1438. r = sam4_ReadAllRegs(pPrivate->pChip);
  1439. if (r != ERROR_OK)
  1440. return r;
  1441. LOG_DEBUG("Here");
  1442. if (pPrivate->pChip->probed)
  1443. r = sam4_GetInfo(pPrivate->pChip);
  1444. else
  1445. r = sam4_GetDetails(pPrivate);
  1446. if (r != ERROR_OK)
  1447. return r;
  1448. /* update the flash bank size */
  1449. for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
  1450. if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
  1451. bank->size = pPrivate->pChip->details.bank[x].size_bytes;
  1452. break;
  1453. }
  1454. }
  1455. if (bank->sectors == NULL) {
  1456. bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
  1457. if (bank->sectors == NULL) {
  1458. LOG_ERROR("No memory!");
  1459. return ERROR_FAIL;
  1460. }
  1461. bank->num_sectors = pPrivate->nsectors;
  1462. for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
  1463. bank->sectors[x].size = pPrivate->sector_size;
  1464. bank->sectors[x].offset = x * (pPrivate->sector_size);
  1465. /* mark as unknown */
  1466. bank->sectors[x].is_erased = -1;
  1467. bank->sectors[x].is_protected = -1;
  1468. }
  1469. }
  1470. pPrivate->probed = 1;
  1471. r = sam4_protect_check(bank);
  1472. if (r != ERROR_OK)
  1473. return r;
  1474. LOG_DEBUG("Bank = %d, nbanks = %d",
  1475. pPrivate->bank_number, pPrivate->pChip->details.n_banks);
  1476. if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
  1477. /* read unique id, */
  1478. /* it appears to be associated with the *last* flash bank. */
  1479. FLASHD_ReadUniqueID(pPrivate);
  1480. }
  1481. return r;
  1482. }
  1483. static int sam4_probe(struct flash_bank *bank)
  1484. {
  1485. return _sam4_probe(bank, 1);
  1486. }
  1487. static int sam4_auto_probe(struct flash_bank *bank)
  1488. {
  1489. return _sam4_probe(bank, 0);
  1490. }
  1491. static int sam4_erase(struct flash_bank *bank, int first, int last)
  1492. {
  1493. struct sam4_bank_private *pPrivate;
  1494. int r;
  1495. int i;
  1496. int pageCount;
  1497. /*16 pages equals 8KB - Same size as a lock region*/
  1498. pageCount = 16;
  1499. uint32_t status;
  1500. LOG_DEBUG("Here");
  1501. if (bank->target->state != TARGET_HALTED) {
  1502. LOG_ERROR("Target not halted");
  1503. return ERROR_TARGET_NOT_HALTED;
  1504. }
  1505. r = sam4_auto_probe(bank);
  1506. if (r != ERROR_OK) {
  1507. LOG_DEBUG("Here,r=%d", r);
  1508. return r;
  1509. }
  1510. pPrivate = get_sam4_bank_private(bank);
  1511. if (!(pPrivate->probed))
  1512. return ERROR_FLASH_BANK_NOT_PROBED;
  1513. if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
  1514. /* whole chip */
  1515. LOG_DEBUG("Here");
  1516. return FLASHD_EraseEntireBank(pPrivate);
  1517. }
  1518. LOG_INFO("sam4 does not auto-erase while programing (Erasing relevant sectors)");
  1519. LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", (unsigned int)(first), (unsigned int)(last));
  1520. for (i = first; i <= last; i++) {
  1521. /*16 pages equals 8KB - Same size as a lock region*/
  1522. r = FLASHD_ErasePages(pPrivate, (i * pageCount), pageCount, &status);
  1523. LOG_INFO("Erasing sector: 0x%08x", (unsigned int)(i));
  1524. if (r != ERROR_OK)
  1525. LOG_ERROR("SAM4: Error performing Erase page @ lock region number %d",
  1526. (unsigned int)(i));
  1527. if (status & (1 << 2)) {
  1528. LOG_ERROR("SAM4: Lock Reqion %d is locked", (unsigned int)(i));
  1529. return ERROR_FAIL;
  1530. }
  1531. if (status & (1 << 1)) {
  1532. LOG_ERROR("SAM4: Flash Command error @lock region %d", (unsigned int)(i));
  1533. return ERROR_FAIL;
  1534. }
  1535. }
  1536. return ERROR_OK;
  1537. }
  1538. static int sam4_protect(struct flash_bank *bank, int set, int first, int last)
  1539. {
  1540. struct sam4_bank_private *pPrivate;
  1541. int r;
  1542. LOG_DEBUG("Here");
  1543. if (bank->target->state != TARGET_HALTED) {
  1544. LOG_ERROR("Target not halted");
  1545. return ERROR_TARGET_NOT_HALTED;
  1546. }
  1547. pPrivate = get_sam4_bank_private(bank);
  1548. if (!(pPrivate->probed))
  1549. return ERROR_FLASH_BANK_NOT_PROBED;
  1550. if (set)
  1551. r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
  1552. else
  1553. r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
  1554. LOG_DEBUG("End: r=%d", r);
  1555. return r;
  1556. }
  1557. static int sam4_info(struct flash_bank *bank, char *buf, int buf_size)
  1558. {
  1559. if (bank->target->state != TARGET_HALTED) {
  1560. LOG_ERROR("Target not halted");
  1561. return ERROR_TARGET_NOT_HALTED;
  1562. }
  1563. buf[0] = 0;
  1564. return ERROR_OK;
  1565. }
  1566. static int sam4_page_read(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
  1567. {
  1568. uint32_t adr;
  1569. int r;
  1570. adr = pagenum * pPrivate->page_size;
  1571. adr = adr + pPrivate->base_address;
  1572. r = target_read_memory(pPrivate->pChip->target,
  1573. adr,
  1574. 4, /* THIS*MUST*BE* in 32bit values */
  1575. pPrivate->page_size / 4,
  1576. buf);
  1577. if (r != ERROR_OK)
  1578. LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
  1579. (unsigned int)(adr));
  1580. return r;
  1581. }
  1582. /* The code below is basically this: */
  1583. /* compiled with */
  1584. /* arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s */
  1585. /* */
  1586. /* Only the *CPU* can write to the flash buffer. */
  1587. /* the DAP cannot... so - we download this 28byte thing */
  1588. /* Run the algorithm - (below) */
  1589. /* to program the device */
  1590. /* */
  1591. /* ======================================== */
  1592. /* #include <stdint.h> */
  1593. /* */
  1594. /* struct foo { */
  1595. /* uint32_t *dst; */
  1596. /* const uint32_t *src; */
  1597. /* int n; */
  1598. /* volatile uint32_t *base; */
  1599. /* uint32_t cmd; */
  1600. /* }; */
  1601. /* */
  1602. /* */
  1603. /* uint32_t sam4_function(struct foo *p) */
  1604. /* { */
  1605. /* volatile uint32_t *v; */
  1606. /* uint32_t *d; */
  1607. /* const uint32_t *s; */
  1608. /* int n; */
  1609. /* uint32_t r; */
  1610. /* */
  1611. /* d = p->dst; */
  1612. /* s = p->src; */
  1613. /* n = p->n; */
  1614. /* */
  1615. /* do { */
  1616. /* *d++ = *s++; */
  1617. /* } while (--n) */
  1618. /* ; */
  1619. /* */
  1620. /* v = p->base; */
  1621. /* */
  1622. /* v[ 1 ] = p->cmd; */
  1623. /* do { */
  1624. /* r = v[8/4]; */
  1625. /* } while (!(r&1)) */
  1626. /* ; */
  1627. /* return r; */
  1628. /* } */
  1629. /* ======================================== */
  1630. static const uint8_t
  1631. sam4_page_write_opcodes[] = {
  1632. /* 24 0000 0446 mov r4, r0 */
  1633. 0x04, 0x46,
  1634. /* 25 0002 6168 ldr r1, [r4, #4] */
  1635. 0x61, 0x68,
  1636. /* 26 0004 0068 ldr r0, [r0, #0] */
  1637. 0x00, 0x68,
  1638. /* 27 0006 A268 ldr r2, [r4, #8] */
  1639. 0xa2, 0x68,
  1640. /* 28 @ lr needed for prologue */
  1641. /* 29 .L2: */
  1642. /* 30 0008 51F8043B ldr r3, [r1], #4 */
  1643. 0x51, 0xf8, 0x04, 0x3b,
  1644. /* 31 000c 12F1FF32 adds r2, r2, #-1 */
  1645. 0x12, 0xf1, 0xff, 0x32,
  1646. /* 32 0010 40F8043B str r3, [r0], #4 */
  1647. 0x40, 0xf8, 0x04, 0x3b,
  1648. /* 33 0014 F8D1 bne .L2 */
  1649. 0xf8, 0xd1,
  1650. /* 34 0016 E268 ldr r2, [r4, #12] */
  1651. 0xe2, 0x68,
  1652. /* 35 0018 2369 ldr r3, [r4, #16] */
  1653. 0x23, 0x69,
  1654. /* 36 001a 5360 str r3, [r2, #4] */
  1655. 0x53, 0x60,
  1656. /* 37 001c 0832 adds r2, r2, #8 */
  1657. 0x08, 0x32,
  1658. /* 38 .L4: */
  1659. /* 39 001e 1068 ldr r0, [r2, #0] */
  1660. 0x10, 0x68,
  1661. /* 40 0020 10F0010F tst r0, #1 */
  1662. 0x10, 0xf0, 0x01, 0x0f,
  1663. /* 41 0024 FBD0 beq .L4 */
  1664. 0xfb, 0xd0,
  1665. 0x00, 0xBE /* bkpt #0 */
  1666. };
  1667. static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
  1668. {
  1669. uint32_t adr;
  1670. uint32_t status;
  1671. uint32_t fmr; /* EEFC Flash Mode Register */
  1672. int r;
  1673. adr = pagenum * pPrivate->page_size;
  1674. adr = (adr + pPrivate->base_address);
  1675. /* Get flash mode register value */
  1676. r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
  1677. if (r != ERROR_OK)
  1678. LOG_DEBUG("Error Read failed: read flash mode register");
  1679. /* Clear flash wait state field */
  1680. fmr &= 0xfffff0ff;
  1681. /* set FWS (flash wait states) field in the FMR (flash mode register) */
  1682. fmr |= (pPrivate->flash_wait_states << 8);
  1683. LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
  1684. r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
  1685. if (r != ERROR_OK)
  1686. LOG_DEBUG("Error Write failed: set flash mode register");
  1687. /* 1st sector 8kBytes - page 0 - 15*/
  1688. /* 2nd sector 8kBytes - page 16 - 30*/
  1689. /* 3rd sector 48kBytes - page 31 - 127*/
  1690. LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
  1691. r = target_write_memory(pPrivate->pChip->target,
  1692. adr,
  1693. 4, /* THIS*MUST*BE* in 32bit values */
  1694. pPrivate->page_size / 4,
  1695. buf);
  1696. if (r != ERROR_OK) {
  1697. LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
  1698. (unsigned int)(adr));
  1699. return r;
  1700. }
  1701. r = EFC_PerformCommand(pPrivate,
  1702. /* send Erase & Write Page */
  1703. AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
  1704. pagenum,
  1705. &status);
  1706. if (r != ERROR_OK)
  1707. LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
  1708. (unsigned int)(adr));
  1709. if (status & (1 << 2)) {
  1710. LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
  1711. return ERROR_FAIL;
  1712. }
  1713. if (status & (1 << 1)) {
  1714. LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
  1715. return ERROR_FAIL;
  1716. }
  1717. return ERROR_OK;
  1718. }
  1719. static int sam4_write(struct flash_bank *bank,
  1720. uint8_t *buffer,
  1721. uint32_t offset,
  1722. uint32_t count)
  1723. {
  1724. int n;
  1725. unsigned page_cur;
  1726. unsigned page_end;
  1727. int r;
  1728. unsigned page_offset;
  1729. struct sam4_bank_private *pPrivate;
  1730. uint8_t *pagebuffer;
  1731. /* incase we bail further below, set this to null */
  1732. pagebuffer = NULL;
  1733. /* ignore dumb requests */
  1734. if (count == 0) {
  1735. r = ERROR_OK;
  1736. goto done;
  1737. }
  1738. if (bank->target->state != TARGET_HALTED) {
  1739. LOG_ERROR("Target not halted");
  1740. r = ERROR_TARGET_NOT_HALTED;
  1741. goto done;
  1742. }
  1743. pPrivate = get_sam4_bank_private(bank);
  1744. if (!(pPrivate->probed)) {
  1745. r = ERROR_FLASH_BANK_NOT_PROBED;
  1746. goto done;
  1747. }
  1748. if ((offset + count) > pPrivate->size_bytes) {
  1749. LOG_ERROR("Flash write error - past end of bank");
  1750. LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
  1751. (unsigned int)(offset),
  1752. (unsigned int)(count),
  1753. (unsigned int)(pPrivate->size_bytes));
  1754. r = ERROR_FAIL;
  1755. goto done;
  1756. }
  1757. pagebuffer = malloc(pPrivate->page_size);
  1758. if (!pagebuffer) {
  1759. LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
  1760. r = ERROR_FAIL;
  1761. goto done;
  1762. }
  1763. /* what page do we start & end in? */
  1764. page_cur = offset / pPrivate->page_size;
  1765. page_end = (offset + count - 1) / pPrivate->page_size;
  1766. LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
  1767. LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
  1768. /* Special case: all one page */
  1769. /* */
  1770. /* Otherwise: */
  1771. /* (1) non-aligned start */
  1772. /* (2) body pages */
  1773. /* (3) non-aligned end. */
  1774. /* Handle special case - all one page. */
  1775. if (page_cur == page_end) {
  1776. LOG_DEBUG("Special case, all in one page");
  1777. r = sam4_page_read(pPrivate, page_cur, pagebuffer);
  1778. if (r != ERROR_OK)
  1779. goto done;
  1780. page_offset = (offset & (pPrivate->page_size-1));
  1781. memcpy(pagebuffer + page_offset,
  1782. buffer,
  1783. count);
  1784. r = sam4_page_write(pPrivate, page_cur, pagebuffer);
  1785. if (r != ERROR_OK)
  1786. goto done;
  1787. r = ERROR_OK;
  1788. goto done;
  1789. }
  1790. /* non-aligned start */
  1791. page_offset = offset & (pPrivate->page_size - 1);
  1792. if (page_offset) {
  1793. LOG_DEBUG("Not-Aligned start");
  1794. /* read the partial */
  1795. r = sam4_page_read(pPrivate, page_cur, pagebuffer);
  1796. if (r != ERROR_OK)
  1797. goto done;
  1798. /* over-write with new data */
  1799. n = (pPrivate->page_size - page_offset);
  1800. memcpy(pagebuffer + page_offset,
  1801. buffer,
  1802. n);
  1803. r = sam4_page_write(pPrivate, page_cur, pagebuffer);
  1804. if (r != ERROR_OK)
  1805. goto done;
  1806. count -= n;
  1807. offset += n;
  1808. buffer += n;
  1809. page_cur++;
  1810. }
  1811. /* By checking that offset is correct here, we also
  1812. fix a clang warning */
  1813. assert(offset % pPrivate->page_size == 0);
  1814. /* intermediate large pages */
  1815. /* also - the final *terminal* */
  1816. /* if that terminal page is a full page */
  1817. LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
  1818. (int)page_cur, (int)page_end, (unsigned int)(count));
  1819. while ((page_cur < page_end) &&
  1820. (count >= pPrivate->page_size)) {
  1821. r = sam4_page_write(pPrivate, page_cur, buffer);
  1822. if (r != ERROR_OK)
  1823. goto done;
  1824. count -= pPrivate->page_size;
  1825. buffer += pPrivate->page_size;
  1826. page_cur += 1;
  1827. }
  1828. /* terminal partial page? */
  1829. if (count) {
  1830. LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
  1831. /* we have a partial page */
  1832. r = sam4_page_read(pPrivate, page_cur, pagebuffer);
  1833. if (r != ERROR_OK)
  1834. goto done;
  1835. /* data goes at start */
  1836. memcpy(pagebuffer, buffer, count);
  1837. r = sam4_page_write(pPrivate, page_cur, pagebuffer);
  1838. if (r != ERROR_OK)
  1839. goto done;
  1840. }
  1841. LOG_DEBUG("Done!");
  1842. r = ERROR_OK;
  1843. done:
  1844. if (pagebuffer)
  1845. free(pagebuffer);
  1846. return r;
  1847. }
  1848. COMMAND_HANDLER(sam4_handle_info_command)
  1849. {
  1850. struct sam4_chip *pChip;
  1851. pChip = get_current_sam4(CMD_CTX);
  1852. if (!pChip)
  1853. return ERROR_OK;
  1854. unsigned x;
  1855. int r;
  1856. /* bank0 must exist before we can do anything */
  1857. if (pChip->details.bank[0].pBank == NULL) {
  1858. x = 0;
  1859. need_define:
  1860. command_print(CMD_CTX,
  1861. "Please define bank %d via command: flash bank %s ... ",
  1862. x,
  1863. at91sam4_flash.name);
  1864. return ERROR_FAIL;
  1865. }
  1866. /* if bank 0 is not probed, then probe it */
  1867. if (!(pChip->details.bank[0].probed)) {
  1868. r = sam4_auto_probe(pChip->details.bank[0].pBank);
  1869. if (r != ERROR_OK)
  1870. return ERROR_FAIL;
  1871. }
  1872. /* above guarantees the "chip details" structure is valid */
  1873. /* and thus, bank private areas are valid */
  1874. /* and we have a SAM4 chip, what a concept! */
  1875. /* auto-probe other banks, 0 done above */
  1876. for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
  1877. /* skip banks not present */
  1878. if (!(pChip->details.bank[x].present))
  1879. continue;
  1880. if (pChip->details.bank[x].pBank == NULL)
  1881. goto need_define;
  1882. if (pChip->details.bank[x].probed)
  1883. continue;
  1884. r = sam4_auto_probe(pChip->details.bank[x].pBank);
  1885. if (r != ERROR_OK)
  1886. return r;
  1887. }
  1888. r = sam4_GetInfo(pChip);
  1889. if (r != ERROR_OK) {
  1890. LOG_DEBUG("Sam4Info, Failed %d", r);
  1891. return r;
  1892. }
  1893. return ERROR_OK;
  1894. }
  1895. COMMAND_HANDLER(sam4_handle_gpnvm_command)
  1896. {
  1897. unsigned x, v;
  1898. int r, who;
  1899. struct sam4_chip *pChip;
  1900. pChip = get_current_sam4(CMD_CTX);
  1901. if (!pChip)
  1902. return ERROR_OK;
  1903. if (pChip->target->state != TARGET_HALTED) {
  1904. LOG_ERROR("sam4 - target not halted");
  1905. return ERROR_TARGET_NOT_HALTED;
  1906. }
  1907. if (pChip->details.bank[0].pBank == NULL) {
  1908. command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
  1909. at91sam4_flash.name);
  1910. return ERROR_FAIL;
  1911. }
  1912. if (!pChip->details.bank[0].probed) {
  1913. r = sam4_auto_probe(pChip->details.bank[0].pBank);
  1914. if (r != ERROR_OK)
  1915. return r;
  1916. }
  1917. switch (CMD_ARGC) {
  1918. default:
  1919. return ERROR_COMMAND_SYNTAX_ERROR;
  1920. break;
  1921. case 0:
  1922. goto showall;
  1923. break;
  1924. case 1:
  1925. who = -1;
  1926. break;
  1927. case 2:
  1928. if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
  1929. who = -1;
  1930. else {
  1931. uint32_t v32;
  1932. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
  1933. who = v32;
  1934. }
  1935. break;
  1936. }
  1937. if (0 == strcmp("show", CMD_ARGV[0])) {
  1938. if (who == -1) {
  1939. showall:
  1940. r = ERROR_OK;
  1941. for (x = 0; x < pChip->details.n_gpnvms; x++) {
  1942. r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
  1943. if (r != ERROR_OK)
  1944. break;
  1945. command_print(CMD_CTX, "sam4-gpnvm%u: %u", x, v);
  1946. }
  1947. return r;
  1948. }
  1949. if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
  1950. r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
  1951. command_print(CMD_CTX, "sam4-gpnvm%u: %u", who, v);
  1952. return r;
  1953. } else {
  1954. command_print(CMD_CTX, "sam4-gpnvm invalid GPNVM: %u", who);
  1955. return ERROR_COMMAND_SYNTAX_ERROR;
  1956. }
  1957. }
  1958. if (who == -1) {
  1959. command_print(CMD_CTX, "Missing GPNVM number");
  1960. return ERROR_COMMAND_SYNTAX_ERROR;
  1961. }
  1962. if (0 == strcmp("set", CMD_ARGV[0]))
  1963. r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
  1964. else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
  1965. (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
  1966. r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
  1967. else {
  1968. command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
  1969. r = ERROR_COMMAND_SYNTAX_ERROR;
  1970. }
  1971. return r;
  1972. }
  1973. COMMAND_HANDLER(sam4_handle_slowclk_command)
  1974. {
  1975. struct sam4_chip *pChip;
  1976. pChip = get_current_sam4(CMD_CTX);
  1977. if (!pChip)
  1978. return ERROR_OK;
  1979. switch (CMD_ARGC) {
  1980. case 0:
  1981. /* show */
  1982. break;
  1983. case 1:
  1984. {
  1985. /* set */
  1986. uint32_t v;
  1987. COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
  1988. if (v > 200000) {
  1989. /* absurd slow clock of 200Khz? */
  1990. command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
  1991. return ERROR_COMMAND_SYNTAX_ERROR;
  1992. }
  1993. pChip->cfg.slow_freq = v;
  1994. break;
  1995. }
  1996. default:
  1997. /* error */
  1998. command_print(CMD_CTX, "Too many parameters");
  1999. return ERROR_COMMAND_SYNTAX_ERROR;
  2000. break;
  2001. }
  2002. command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
  2003. (int)(pChip->cfg.slow_freq / 1000),
  2004. (int)(pChip->cfg.slow_freq % 1000));
  2005. return ERROR_OK;
  2006. }
  2007. static const struct command_registration at91sam4_exec_command_handlers[] = {
  2008. {
  2009. .name = "gpnvm",
  2010. .handler = sam4_handle_gpnvm_command,
  2011. .mode = COMMAND_EXEC,
  2012. .usage = "[('clr'|'set'|'show') bitnum]",
  2013. .help = "Without arguments, shows all bits in the gpnvm "
  2014. "register. Otherwise, clears, sets, or shows one "
  2015. "General Purpose Non-Volatile Memory (gpnvm) bit.",
  2016. },
  2017. {
  2018. .name = "info",
  2019. .handler = sam4_handle_info_command,
  2020. .mode = COMMAND_EXEC,
  2021. .help = "Print information about the current at91sam4 chip"
  2022. "and its flash configuration.",
  2023. },
  2024. {
  2025. .name = "slowclk",
  2026. .handler = sam4_handle_slowclk_command,
  2027. .mode = COMMAND_EXEC,
  2028. .usage = "[clock_hz]",
  2029. .help = "Display or set the slowclock frequency "
  2030. "(default 32768 Hz).",
  2031. },
  2032. COMMAND_REGISTRATION_DONE
  2033. };
  2034. static const struct command_registration at91sam4_command_handlers[] = {
  2035. {
  2036. .name = "at91sam4",
  2037. .mode = COMMAND_ANY,
  2038. .help = "at91sam4 flash command group",
  2039. .usage = "",
  2040. .chain = at91sam4_exec_command_handlers,
  2041. },
  2042. COMMAND_REGISTRATION_DONE
  2043. };
  2044. struct flash_driver at91sam4_flash = {
  2045. .name = "at91sam4",
  2046. .commands = at91sam4_command_handlers,
  2047. .flash_bank_command = sam4_flash_bank_command,
  2048. .erase = sam4_erase,
  2049. .protect = sam4_protect,
  2050. .write = sam4_write,
  2051. .read = default_flash_read,
  2052. .probe = sam4_probe,
  2053. .auto_probe = sam4_auto_probe,
  2054. .erase_check = default_flash_blank_check,
  2055. .protect_check = sam4_protect_check,
  2056. .info = sam4_info,
  2057. };