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  1. /***************************************************************************
  2. * Copyright (C) 2006 by Magnus Lundin *
  3. * lundin@mlu.mine.nu *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * This program is free software; you can redistribute it and/or modify *
  9. * it under the terms of the GNU General Public License as published by *
  10. * the Free Software Foundation; either version 2 of the License, or *
  11. * (at your option) any later version. *
  12. * *
  13. * This program is distributed in the hope that it will be useful, *
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  16. * GNU General Public License for more details. *
  17. * *
  18. * You should have received a copy of the GNU General Public License *
  19. * along with this program; if not, write to the *
  20. * Free Software Foundation, Inc., *
  21. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  22. ***************************************************************************/
  23. /***************************************************************************
  24. * STELLARIS flash is tested on LM3S811, LM3S6965, LM3s3748, more.
  25. ***************************************************************************/
  26. #ifdef HAVE_CONFIG_H
  27. #include "config.h"
  28. #endif
  29. #include "imp.h"
  30. #include <target/algorithm.h>
  31. #include <target/armv7m.h>
  32. #define DID0_VER(did0) ((did0 >> 28)&0x07)
  33. /* STELLARIS control registers */
  34. #define SCB_BASE 0x400FE000
  35. #define DID0 0x000
  36. #define DID1 0x004
  37. #define DC0 0x008
  38. #define DC1 0x010
  39. #define DC2 0x014
  40. #define DC3 0x018
  41. #define DC4 0x01C
  42. #define RIS 0x050
  43. #define RCC 0x060
  44. #define PLLCFG 0x064
  45. #define RCC2 0x070
  46. #define NVMSTAT 0x1a0
  47. /* "legacy" flash memory protection registers (64KB max) */
  48. #define FMPRE 0x130
  49. #define FMPPE 0x134
  50. /* new flash memory protection registers (for more than 64KB) */
  51. #define FMPRE0 0x200 /* PRE1 = PRE0 + 4, etc */
  52. #define FMPPE0 0x400 /* PPE1 = PPE0 + 4, etc */
  53. #define USECRL 0x140
  54. #define FLASH_CONTROL_BASE 0x400FD000
  55. #define FLASH_FMA (FLASH_CONTROL_BASE | 0x000)
  56. #define FLASH_FMD (FLASH_CONTROL_BASE | 0x004)
  57. #define FLASH_FMC (FLASH_CONTROL_BASE | 0x008)
  58. #define FLASH_CRIS (FLASH_CONTROL_BASE | 0x00C)
  59. #define FLASH_CIM (FLASH_CONTROL_BASE | 0x010)
  60. #define FLASH_MISC (FLASH_CONTROL_BASE | 0x014)
  61. #define AMISC 1
  62. #define PMISC 2
  63. #define AMASK 1
  64. #define PMASK 2
  65. /* Flash Controller Command bits */
  66. #define FMC_WRKEY (0xA442 << 16)
  67. #define FMC_COMT (1 << 3)
  68. #define FMC_MERASE (1 << 2)
  69. #define FMC_ERASE (1 << 1)
  70. #define FMC_WRITE (1 << 0)
  71. /* STELLARIS constants */
  72. /* values to write in FMA to commit write-"once" values */
  73. #define FLASH_FMA_PRE(x) (2 * (x)) /* for FMPPREx */
  74. #define FLASH_FMA_PPE(x) (2 * (x) + 1) /* for FMPPPEx */
  75. static void stellaris_read_clock_info(struct flash_bank *bank);
  76. static int stellaris_mass_erase(struct flash_bank *bank);
  77. struct stellaris_flash_bank
  78. {
  79. /* chip id register */
  80. uint32_t did0;
  81. uint32_t did1;
  82. uint32_t dc0;
  83. uint32_t dc1;
  84. const char * target_name;
  85. uint32_t sramsiz;
  86. uint32_t flshsz;
  87. /* flash geometry */
  88. uint32_t num_pages;
  89. uint32_t pagesize;
  90. uint32_t pages_in_lockregion;
  91. /* nv memory bits */
  92. uint16_t num_lockbits;
  93. /* main clock status */
  94. uint32_t rcc;
  95. uint32_t rcc2;
  96. uint8_t mck_valid;
  97. uint8_t xtal_mask;
  98. uint32_t iosc_freq;
  99. uint32_t mck_freq;
  100. const char *iosc_desc;
  101. const char *mck_desc;
  102. };
  103. // Autogenerated by contrib/gen-stellaris-part-header.pl
  104. // From Stellaris Firmware Development Package revision 8049
  105. static struct {
  106. uint8_t class;
  107. uint8_t partno;
  108. const char *partname;
  109. } StellarisParts[] = {
  110. {0x00, 0x01, "LM3S101"},
  111. {0x00, 0x02, "LM3S102"},
  112. {0x01, 0xBF, "LM3S1110"},
  113. {0x01, 0xC3, "LM3S1133"},
  114. {0x01, 0xC5, "LM3S1138"},
  115. {0x01, 0xC1, "LM3S1150"},
  116. {0x01, 0xC4, "LM3S1162"},
  117. {0x01, 0xC2, "LM3S1165"},
  118. {0x01, 0xEC, "LM3S1166"},
  119. {0x01, 0xC6, "LM3S1332"},
  120. {0x01, 0xBC, "LM3S1435"},
  121. {0x01, 0xBA, "LM3S1439"},
  122. {0x01, 0xBB, "LM3S1512"},
  123. {0x01, 0xC7, "LM3S1538"},
  124. {0x01, 0xDB, "LM3S1601"},
  125. {0x03, 0x06, "LM3S1607"},
  126. {0x01, 0xDA, "LM3S1608"},
  127. {0x01, 0xC0, "LM3S1620"},
  128. {0x04, 0xCD, "LM3S1621"},
  129. {0x03, 0x03, "LM3S1625"},
  130. {0x03, 0x04, "LM3S1626"},
  131. {0x03, 0x05, "LM3S1627"},
  132. {0x01, 0xB3, "LM3S1635"},
  133. {0x01, 0xEB, "LM3S1636"},
  134. {0x01, 0xBD, "LM3S1637"},
  135. {0x04, 0xB1, "LM3S1651"},
  136. {0x01, 0xB9, "LM3S1751"},
  137. {0x03, 0x10, "LM3S1776"},
  138. {0x04, 0x16, "LM3S1811"},
  139. {0x04, 0x3D, "LM3S1816"},
  140. {0x01, 0xB4, "LM3S1850"},
  141. {0x01, 0xDD, "LM3S1911"},
  142. {0x01, 0xDC, "LM3S1918"},
  143. {0x01, 0xB7, "LM3S1937"},
  144. {0x01, 0xBE, "LM3S1958"},
  145. {0x01, 0xB5, "LM3S1960"},
  146. {0x01, 0xB8, "LM3S1968"},
  147. {0x01, 0xEA, "LM3S1969"},
  148. {0x04, 0xCE, "LM3S1B21"},
  149. {0x06, 0xCA, "LM3S1C21"},
  150. {0x06, 0xCB, "LM3S1C26"},
  151. {0x06, 0x98, "LM3S1C58"},
  152. {0x06, 0xB0, "LM3S1D21"},
  153. {0x06, 0xCC, "LM3S1D26"},
  154. {0x06, 0x1D, "LM3S1F11"},
  155. {0x06, 0x1B, "LM3S1F16"},
  156. {0x06, 0xAF, "LM3S1G21"},
  157. {0x06, 0x95, "LM3S1G58"},
  158. {0x06, 0x1E, "LM3S1H11"},
  159. {0x06, 0x1C, "LM3S1H16"},
  160. {0x04, 0x0F, "LM3S1J11"},
  161. {0x04, 0x3C, "LM3S1J16"},
  162. {0x04, 0x0E, "LM3S1N11"},
  163. {0x04, 0x3B, "LM3S1N16"},
  164. {0x04, 0xB2, "LM3S1P51"},
  165. {0x04, 0x9E, "LM3S1R21"},
  166. {0x04, 0xC9, "LM3S1R26"},
  167. {0x04, 0x30, "LM3S1W16"},
  168. {0x04, 0x2F, "LM3S1Z16"},
  169. {0x01, 0xD4, "LM3S2016"},
  170. {0x01, 0x51, "LM3S2110"},
  171. {0x01, 0x84, "LM3S2139"},
  172. {0x03, 0x39, "LM3S2276"},
  173. {0x01, 0xA2, "LM3S2410"},
  174. {0x01, 0x59, "LM3S2412"},
  175. {0x01, 0x56, "LM3S2432"},
  176. {0x01, 0x5A, "LM3S2533"},
  177. {0x01, 0xE1, "LM3S2601"},
  178. {0x01, 0xE0, "LM3S2608"},
  179. {0x03, 0x33, "LM3S2616"},
  180. {0x01, 0x57, "LM3S2620"},
  181. {0x01, 0x85, "LM3S2637"},
  182. {0x01, 0x53, "LM3S2651"},
  183. {0x03, 0x80, "LM3S2671"},
  184. {0x03, 0x50, "LM3S2678"},
  185. {0x01, 0xA4, "LM3S2730"},
  186. {0x01, 0x52, "LM3S2739"},
  187. {0x03, 0x3A, "LM3S2776"},
  188. {0x04, 0x6D, "LM3S2793"},
  189. {0x01, 0xE3, "LM3S2911"},
  190. {0x01, 0xE2, "LM3S2918"},
  191. {0x01, 0xED, "LM3S2919"},
  192. {0x01, 0x54, "LM3S2939"},
  193. {0x01, 0x8F, "LM3S2948"},
  194. {0x01, 0x58, "LM3S2950"},
  195. {0x01, 0x55, "LM3S2965"},
  196. {0x04, 0x6C, "LM3S2B93"},
  197. {0x06, 0x94, "LM3S2D93"},
  198. {0x06, 0x93, "LM3S2U93"},
  199. {0x00, 0x19, "LM3S300"},
  200. {0x00, 0x11, "LM3S301"},
  201. {0x00, 0x1A, "LM3S308"},
  202. {0x00, 0x12, "LM3S310"},
  203. {0x00, 0x13, "LM3S315"},
  204. {0x00, 0x14, "LM3S316"},
  205. {0x00, 0x17, "LM3S317"},
  206. {0x00, 0x15, "LM3S328"},
  207. {0x03, 0x08, "LM3S3634"},
  208. {0x03, 0x43, "LM3S3651"},
  209. {0x04, 0xC8, "LM3S3654"},
  210. {0x03, 0x44, "LM3S3739"},
  211. {0x03, 0x49, "LM3S3748"},
  212. {0x03, 0x45, "LM3S3749"},
  213. {0x04, 0x42, "LM3S3826"},
  214. {0x04, 0x41, "LM3S3J26"},
  215. {0x04, 0x40, "LM3S3N26"},
  216. {0x04, 0x3F, "LM3S3W26"},
  217. {0x04, 0x3E, "LM3S3Z26"},
  218. {0x03, 0x81, "LM3S5632"},
  219. {0x04, 0x0C, "LM3S5651"},
  220. {0x03, 0x8A, "LM3S5652"},
  221. {0x04, 0x4D, "LM3S5656"},
  222. {0x03, 0x91, "LM3S5662"},
  223. {0x03, 0x96, "LM3S5732"},
  224. {0x03, 0x97, "LM3S5737"},
  225. {0x03, 0xA0, "LM3S5739"},
  226. {0x03, 0x99, "LM3S5747"},
  227. {0x03, 0xA7, "LM3S5749"},
  228. {0x03, 0x9A, "LM3S5752"},
  229. {0x03, 0x9C, "LM3S5762"},
  230. {0x04, 0x69, "LM3S5791"},
  231. {0x04, 0x0B, "LM3S5951"},
  232. {0x04, 0x4E, "LM3S5956"},
  233. {0x04, 0x68, "LM3S5B91"},
  234. {0x06, 0x2E, "LM3S5C31"},
  235. {0x06, 0x2C, "LM3S5C36"},
  236. {0x06, 0x5E, "LM3S5C51"},
  237. {0x06, 0x5B, "LM3S5C56"},
  238. {0x06, 0x5F, "LM3S5D51"},
  239. {0x06, 0x5C, "LM3S5D56"},
  240. {0x06, 0x87, "LM3S5D91"},
  241. {0x06, 0x2D, "LM3S5G31"},
  242. {0x06, 0x1F, "LM3S5G36"},
  243. {0x06, 0x5D, "LM3S5G51"},
  244. {0x06, 0x4F, "LM3S5G56"},
  245. {0x04, 0x09, "LM3S5K31"},
  246. {0x04, 0x4A, "LM3S5K36"},
  247. {0x04, 0x0A, "LM3S5P31"},
  248. {0x04, 0x48, "LM3S5P36"},
  249. {0x04, 0xB6, "LM3S5P3B"},
  250. {0x04, 0x0D, "LM3S5P51"},
  251. {0x04, 0x4C, "LM3S5P56"},
  252. {0x04, 0x07, "LM3S5R31"},
  253. {0x04, 0x4B, "LM3S5R36"},
  254. {0x04, 0x47, "LM3S5T36"},
  255. {0x06, 0x7F, "LM3S5U91"},
  256. {0x04, 0x46, "LM3S5Y36"},
  257. {0x00, 0x2A, "LM3S600"},
  258. {0x00, 0x21, "LM3S601"},
  259. {0x00, 0x2B, "LM3S608"},
  260. {0x00, 0x22, "LM3S610"},
  261. {0x01, 0xA1, "LM3S6100"},
  262. {0x00, 0x23, "LM3S611"},
  263. {0x01, 0x74, "LM3S6110"},
  264. {0x00, 0x24, "LM3S612"},
  265. {0x00, 0x25, "LM3S613"},
  266. {0x00, 0x26, "LM3S615"},
  267. {0x00, 0x28, "LM3S617"},
  268. {0x00, 0x29, "LM3S618"},
  269. {0x00, 0x27, "LM3S628"},
  270. {0x01, 0xA5, "LM3S6420"},
  271. {0x01, 0x82, "LM3S6422"},
  272. {0x01, 0x75, "LM3S6432"},
  273. {0x01, 0x76, "LM3S6537"},
  274. {0x01, 0x71, "LM3S6610"},
  275. {0x01, 0xE7, "LM3S6611"},
  276. {0x01, 0xE6, "LM3S6618"},
  277. {0x01, 0x83, "LM3S6633"},
  278. {0x01, 0x8B, "LM3S6637"},
  279. {0x01, 0xA3, "LM3S6730"},
  280. {0x01, 0x77, "LM3S6753"},
  281. {0x01, 0xD1, "LM3S6816"},
  282. {0x01, 0xE9, "LM3S6911"},
  283. {0x01, 0xD3, "LM3S6916"},
  284. {0x01, 0xE8, "LM3S6918"},
  285. {0x01, 0x89, "LM3S6938"},
  286. {0x01, 0x72, "LM3S6950"},
  287. {0x01, 0x78, "LM3S6952"},
  288. {0x01, 0x73, "LM3S6965"},
  289. {0x06, 0xAA, "LM3S6C11"},
  290. {0x06, 0xAC, "LM3S6C65"},
  291. {0x06, 0x9F, "LM3S6G11"},
  292. {0x06, 0xAB, "LM3S6G65"},
  293. {0x00, 0x38, "LM3S800"},
  294. {0x00, 0x31, "LM3S801"},
  295. {0x00, 0x39, "LM3S808"},
  296. {0x00, 0x32, "LM3S811"},
  297. {0x00, 0x33, "LM3S812"},
  298. {0x00, 0x34, "LM3S815"},
  299. {0x00, 0x36, "LM3S817"},
  300. {0x00, 0x37, "LM3S818"},
  301. {0x00, 0x35, "LM3S828"},
  302. {0x01, 0x64, "LM3S8530"},
  303. {0x01, 0x8E, "LM3S8538"},
  304. {0x01, 0x61, "LM3S8630"},
  305. {0x01, 0x63, "LM3S8730"},
  306. {0x01, 0x8D, "LM3S8733"},
  307. {0x01, 0x86, "LM3S8738"},
  308. {0x01, 0x65, "LM3S8930"},
  309. {0x01, 0x8C, "LM3S8933"},
  310. {0x01, 0x88, "LM3S8938"},
  311. {0x01, 0xA6, "LM3S8962"},
  312. {0x01, 0x62, "LM3S8970"},
  313. {0x01, 0xD7, "LM3S8971"},
  314. {0x06, 0xAE, "LM3S8C62"},
  315. {0x06, 0xAD, "LM3S8G62"},
  316. {0x04, 0xCF, "LM3S9781"},
  317. {0x04, 0x67, "LM3S9790"},
  318. {0x04, 0x6B, "LM3S9792"},
  319. {0x04, 0x2D, "LM3S9971"},
  320. {0x04, 0x20, "LM3S9997"},
  321. {0x04, 0xD0, "LM3S9B81"},
  322. {0x04, 0x66, "LM3S9B90"},
  323. {0x04, 0x6A, "LM3S9B92"},
  324. {0x04, 0x6E, "LM3S9B95"},
  325. {0x04, 0x6F, "LM3S9B96"},
  326. {0x04, 0x1D, "LM3S9BN2"},
  327. {0x04, 0x1E, "LM3S9BN5"},
  328. {0x04, 0x1F, "LM3S9BN6"},
  329. {0x06, 0x70, "LM3S9C97"},
  330. {0x06, 0x7A, "LM3S9CN5"},
  331. {0x06, 0xA9, "LM3S9D81"},
  332. {0x06, 0x7E, "LM3S9D90"},
  333. {0x06, 0x92, "LM3S9D92"},
  334. {0x06, 0xC8, "LM3S9D95"},
  335. {0x06, 0x9D, "LM3S9D96"},
  336. {0x06, 0x7B, "LM3S9DN5"},
  337. {0x06, 0x7C, "LM3S9DN6"},
  338. {0x06, 0x60, "LM3S9G97"},
  339. {0x06, 0x79, "LM3S9GN5"},
  340. {0x04, 0x1B, "LM3S9L71"},
  341. {0x04, 0x18, "LM3S9L97"},
  342. {0x06, 0xA8, "LM3S9U81"},
  343. {0x06, 0x7D, "LM3S9U90"},
  344. {0x06, 0x90, "LM3S9U92"},
  345. {0x06, 0xB7, "LM3S9U95"},
  346. {0x06, 0x9B, "LM3S9U96"},
  347. {0x05, 0x18, "LM4F110B2QR"},
  348. {0x05, 0x19, "LM4F110C4QR"},
  349. {0x05, 0x10, "LM4F110E5QR"},
  350. {0x05, 0x11, "LM4F110H5QR"},
  351. {0x05, 0x22, "LM4F111B2QR"},
  352. {0x05, 0x23, "LM4F111C4QR"},
  353. {0x05, 0x20, "LM4F111E5QR"},
  354. {0x05, 0x21, "LM4F111H5QR"},
  355. {0x05, 0x36, "LM4F112C4QC"},
  356. {0x05, 0x30, "LM4F112E5QC"},
  357. {0x05, 0x31, "LM4F112H5QC"},
  358. {0x05, 0x35, "LM4F112H5QD"},
  359. {0x05, 0x01, "LM4F120B2QR"},
  360. {0x05, 0x02, "LM4F120C4QR"},
  361. {0x05, 0x03, "LM4F120E5QR"},
  362. {0x05, 0x04, "LM4F120H5QR"},
  363. {0x05, 0x08, "LM4F121B2QR"},
  364. {0x05, 0x09, "LM4F121C4QR"},
  365. {0x05, 0x0A, "LM4F121E5QR"},
  366. {0x05, 0x0B, "LM4F121H5QR"},
  367. {0x05, 0xD0, "LM4F122C4QC"},
  368. {0x05, 0xD1, "LM4F122E5QC"},
  369. {0x05, 0xD2, "LM4F122H5QC"},
  370. {0x05, 0xD6, "LM4F122H5QD"},
  371. {0x05, 0x48, "LM4F130C4QR"},
  372. {0x05, 0x40, "LM4F130E5QR"},
  373. {0x05, 0x41, "LM4F130H5QR"},
  374. {0x05, 0x52, "LM4F131C4QR"},
  375. {0x05, 0x50, "LM4F131E5QR"},
  376. {0x05, 0x51, "LM4F131H5QR"},
  377. {0x05, 0x66, "LM4F132C4QC"},
  378. {0x05, 0x60, "LM4F132E5QC"},
  379. {0x05, 0x61, "LM4F132H5QC"},
  380. {0x05, 0x65, "LM4F132H5QD"},
  381. {0x05, 0xA0, "LM4F230E5QR"},
  382. {0x05, 0xA1, "LM4F230H5QR"},
  383. {0x05, 0xB0, "LM4F231E5QR"},
  384. {0x05, 0xB1, "LM4F231H5QR"},
  385. {0x05, 0xC0, "LM4F232E5QC"},
  386. {0x05, 0xE3, "LM4F232H5BB"},
  387. {0x05, 0xC1, "LM4F232H5QC"},
  388. {0x05, 0xC5, "LM4F232H5QD"},
  389. {0x05, 0xE5, "LM4FS1AH5BB"},
  390. {0x05, 0xE4, "LM4FS99H5BB"},
  391. {0x05, 0xE0, "LM4FSXAH5BB"},
  392. {0xFF, 0x00, "Unknown Part"}
  393. };
  394. static char * StellarisClassname[7] =
  395. {
  396. "Sandstorm",
  397. "Fury",
  398. "Unknown",
  399. "DustDevil",
  400. "Tempest",
  401. "Blizzard",
  402. "Firestorm"
  403. };
  404. /***************************************************************************
  405. * openocd command interface *
  406. ***************************************************************************/
  407. /* flash_bank stellaris <base> <size> 0 0 <target#>
  408. */
  409. FLASH_BANK_COMMAND_HANDLER(stellaris_flash_bank_command)
  410. {
  411. struct stellaris_flash_bank *stellaris_info;
  412. if (CMD_ARGC < 6)
  413. {
  414. LOG_WARNING("incomplete flash_bank stellaris configuration");
  415. return ERROR_FLASH_BANK_INVALID;
  416. }
  417. stellaris_info = calloc(sizeof(struct stellaris_flash_bank), 1);
  418. bank->base = 0x0;
  419. bank->driver_priv = stellaris_info;
  420. stellaris_info->target_name = "Unknown target";
  421. /* part wasn't probed for info yet */
  422. stellaris_info->did1 = 0;
  423. /* TODO Specify the main crystal speed in kHz using an optional
  424. * argument; ditto, the speed of an external oscillator used
  425. * instead of a crystal. Avoid programming flash using IOSC.
  426. */
  427. return ERROR_OK;
  428. }
  429. static int get_stellaris_info(struct flash_bank *bank, char *buf, int buf_size)
  430. {
  431. int printed, device_class;
  432. struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
  433. if (stellaris_info->did1 == 0)
  434. return ERROR_FLASH_BANK_NOT_PROBED;
  435. /* Read main and master clock freqency register */
  436. stellaris_read_clock_info(bank);
  437. if (DID0_VER(stellaris_info->did0) > 0)
  438. {
  439. device_class = (stellaris_info->did0 >> 16) & 0xFF;
  440. }
  441. else
  442. {
  443. device_class = 0;
  444. }
  445. printed = snprintf(buf,
  446. buf_size,
  447. "\nTI/LMI Stellaris information: Chip is "
  448. "class %i (%s) %s rev %c%i\n",
  449. device_class,
  450. StellarisClassname[device_class],
  451. stellaris_info->target_name,
  452. (int)('A' + ((stellaris_info->did0 >> 8) & 0xFF)),
  453. (int)((stellaris_info->did0) & 0xFF));
  454. buf += printed;
  455. buf_size -= printed;
  456. printed = snprintf(buf,
  457. buf_size,
  458. "did1: 0x%8.8" PRIx32 ", arch: 0x%4.4" PRIx32
  459. ", eproc: %s, ramsize: %ik, flashsize: %ik\n",
  460. stellaris_info->did1,
  461. stellaris_info->did1,
  462. "ARMv7M",
  463. (int)((1 + ((stellaris_info->dc0 >> 16) & 0xFFFF))/4),
  464. (int)((1 + (stellaris_info->dc0 & 0xFFFF))*2));
  465. buf += printed;
  466. buf_size -= printed;
  467. printed = snprintf(buf,
  468. buf_size,
  469. "master clock: %ikHz%s, "
  470. "rcc is 0x%" PRIx32 ", rcc2 is 0x%" PRIx32 "\n",
  471. (int)(stellaris_info->mck_freq / 1000),
  472. stellaris_info->mck_desc,
  473. stellaris_info->rcc,
  474. stellaris_info->rcc2);
  475. buf += printed;
  476. buf_size -= printed;
  477. if (stellaris_info->num_lockbits > 0)
  478. {
  479. printed = snprintf(buf,
  480. buf_size,
  481. "pagesize: %" PRIi32 ", pages: %d, "
  482. "lockbits: %i, pages per lockbit: %i\n",
  483. stellaris_info->pagesize,
  484. (unsigned) stellaris_info->num_pages,
  485. stellaris_info->num_lockbits,
  486. (unsigned) stellaris_info->pages_in_lockregion);
  487. buf += printed;
  488. buf_size -= printed;
  489. }
  490. return ERROR_OK;
  491. }
  492. /***************************************************************************
  493. * chip identification and status *
  494. ***************************************************************************/
  495. /* Set the flash timimg register to match current clocking */
  496. static void stellaris_set_flash_timing(struct flash_bank *bank)
  497. {
  498. struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
  499. struct target *target = bank->target;
  500. uint32_t usecrl = (stellaris_info->mck_freq/1000000ul-1);
  501. LOG_DEBUG("usecrl = %i",(int)(usecrl));
  502. target_write_u32(target, SCB_BASE | USECRL, usecrl);
  503. }
  504. static const unsigned rcc_xtal[32] = {
  505. [0x00] = 1000000, /* no pll */
  506. [0x01] = 1843200, /* no pll */
  507. [0x02] = 2000000, /* no pll */
  508. [0x03] = 2457600, /* no pll */
  509. [0x04] = 3579545,
  510. [0x05] = 3686400,
  511. [0x06] = 4000000, /* usb */
  512. [0x07] = 4096000,
  513. [0x08] = 4915200,
  514. [0x09] = 5000000, /* usb */
  515. [0x0a] = 5120000,
  516. [0x0b] = 6000000, /* (reset) usb */
  517. [0x0c] = 6144000,
  518. [0x0d] = 7372800,
  519. [0x0e] = 8000000, /* usb */
  520. [0x0f] = 8192000,
  521. /* parts before DustDevil use just 4 bits for xtal spec */
  522. [0x10] = 10000000, /* usb */
  523. [0x11] = 12000000, /* usb */
  524. [0x12] = 12288000,
  525. [0x13] = 13560000,
  526. [0x14] = 14318180,
  527. [0x15] = 16000000, /* usb */
  528. [0x16] = 16384000,
  529. };
  530. /** Read clock configuration and set stellaris_info->usec_clocks. */
  531. static void stellaris_read_clock_info(struct flash_bank *bank)
  532. {
  533. struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
  534. struct target *target = bank->target;
  535. uint32_t rcc, rcc2, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;
  536. unsigned xtal;
  537. unsigned long mainfreq;
  538. target_read_u32(target, SCB_BASE | RCC, &rcc);
  539. LOG_DEBUG("Stellaris RCC %" PRIx32 "", rcc);
  540. target_read_u32(target, SCB_BASE | RCC2, &rcc2);
  541. LOG_DEBUG("Stellaris RCC2 %" PRIx32 "", rcc);
  542. target_read_u32(target, SCB_BASE | PLLCFG, &pllcfg);
  543. LOG_DEBUG("Stellaris PLLCFG %" PRIx32 "", pllcfg);
  544. stellaris_info->rcc = rcc;
  545. stellaris_info->rcc = rcc2;
  546. sysdiv = (rcc >> 23) & 0xF;
  547. usesysdiv = (rcc >> 22) & 0x1;
  548. bypass = (rcc >> 11) & 0x1;
  549. oscsrc = (rcc >> 4) & 0x3;
  550. xtal = (rcc >> 6) & stellaris_info->xtal_mask;
  551. /* NOTE: post-Sandstorm parts have RCC2 which may override
  552. * parts of RCC ... with more sysdiv options, option for
  553. * 32768 Hz mainfreq, PLL controls. On Sandstorm it reads
  554. * as zero, so the "use RCC2" flag is always clear.
  555. */
  556. if (rcc2 & (1 << 31)) {
  557. sysdiv = (rcc2 >> 23) & 0x3F;
  558. bypass = (rcc2 >> 11) & 0x1;
  559. oscsrc = (rcc2 >> 4) & 0x7;
  560. /* FIXME Tempest parts have an additional lsb for
  561. * fractional sysdiv (200 MHz / 2.5 == 80 MHz)
  562. */
  563. }
  564. stellaris_info->mck_desc = "";
  565. switch (oscsrc)
  566. {
  567. case 0: /* MOSC */
  568. mainfreq = rcc_xtal[xtal];
  569. break;
  570. case 1: /* IOSC */
  571. mainfreq = stellaris_info->iosc_freq;
  572. stellaris_info->mck_desc = stellaris_info->iosc_desc;
  573. break;
  574. case 2: /* IOSC/4 */
  575. mainfreq = stellaris_info->iosc_freq / 4;
  576. stellaris_info->mck_desc = stellaris_info->iosc_desc;
  577. break;
  578. case 3: /* lowspeed */
  579. /* Sandstorm doesn't have this 30K +/- 30% osc */
  580. mainfreq = 30000;
  581. stellaris_info->mck_desc = " (±30%)";
  582. break;
  583. case 8: /* hibernation osc */
  584. /* not all parts support hibernation */
  585. mainfreq = 32768;
  586. break;
  587. default: /* NOTREACHED */
  588. mainfreq = 0;
  589. break;
  590. }
  591. /* PLL is used if it's not bypassed; its output is 200 MHz
  592. * even when it runs at 400 MHz (adds divide-by-two stage).
  593. */
  594. if (!bypass)
  595. mainfreq = 200000000;
  596. if (usesysdiv)
  597. stellaris_info->mck_freq = mainfreq/(1 + sysdiv);
  598. else
  599. stellaris_info->mck_freq = mainfreq;
  600. }
  601. /* Read device id register, main clock frequency register and fill in driver info structure */
  602. static int stellaris_read_part_info(struct flash_bank *bank)
  603. {
  604. struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
  605. struct target *target = bank->target;
  606. uint32_t did0, did1, ver, fam;
  607. int i;
  608. /* Read and parse chip identification register */
  609. target_read_u32(target, SCB_BASE | DID0, &did0);
  610. target_read_u32(target, SCB_BASE | DID1, &did1);
  611. target_read_u32(target, SCB_BASE | DC0, &stellaris_info->dc0);
  612. target_read_u32(target, SCB_BASE | DC1, &stellaris_info->dc1);
  613. LOG_DEBUG("did0 0x%" PRIx32 ", did1 0x%" PRIx32 ", dc0 0x%" PRIx32 ", dc1 0x%" PRIx32 "",
  614. did0, did1, stellaris_info->dc0, stellaris_info->dc1);
  615. ver = did0 >> 28;
  616. if ((ver != 0) && (ver != 1))
  617. {
  618. LOG_WARNING("Unknown did0 version, cannot identify target");
  619. return ERROR_FLASH_OPERATION_FAILED;
  620. }
  621. if (did1 == 0)
  622. {
  623. LOG_WARNING("Cannot identify target as a Stellaris");
  624. return ERROR_FLASH_OPERATION_FAILED;
  625. }
  626. ver = did1 >> 28;
  627. fam = (did1 >> 24) & 0xF;
  628. if (((ver != 0) && (ver != 1)) || (fam != 0))
  629. {
  630. LOG_WARNING("Unknown did1 version/family.");
  631. return ERROR_FLASH_OPERATION_FAILED;
  632. }
  633. /* For Sandstorm, Fury, DustDevil: current data sheets say IOSC
  634. * is 12 MHz, but some older parts have 15 MHz. A few data sheets
  635. * even give _both_ numbers! We'll use current numbers; IOSC is
  636. * always approximate.
  637. *
  638. * For Tempest: IOSC is calibrated, 16 MHz
  639. */
  640. stellaris_info->iosc_freq = 12000000;
  641. stellaris_info->iosc_desc = " (±30%)";
  642. stellaris_info->xtal_mask = 0x0f;
  643. switch ((did0 >> 28) & 0x7) {
  644. case 0: /* Sandstorm */
  645. /*
  646. * Current (2009-August) parts seem to be rev C2 and use 12 MHz.
  647. * Parts before rev C0 used 15 MHz; some C0 parts use 15 MHz
  648. * (LM3S618), but some other C0 parts are 12 MHz (LM3S811).
  649. */
  650. if (((did0 >> 8) & 0xff) < 2) {
  651. stellaris_info->iosc_freq = 15000000;
  652. stellaris_info->iosc_desc = " (±50%)";
  653. }
  654. break;
  655. case 1:
  656. switch ((did0 >> 16) & 0xff) {
  657. case 1: /* Fury */
  658. break;
  659. case 4: /* Tempest */
  660. stellaris_info->iosc_freq = 16000000; /* +/- 1% */
  661. stellaris_info->iosc_desc = " (±1%)";
  662. /* FALL THROUGH */
  663. case 3: /* DustDevil */
  664. stellaris_info->xtal_mask = 0x1f;
  665. break;
  666. default:
  667. LOG_WARNING("Unknown did0 class");
  668. }
  669. break;
  670. default:
  671. LOG_WARNING("Unknown did0 version");
  672. break;
  673. }
  674. for (i = 0; StellarisParts[i].partno; i++)
  675. {
  676. if ((StellarisParts[i].partno == ((did1 >> 16) & 0xFF)) &&
  677. (StellarisParts[i].class == ((did0 >> 16) & 0xFF)))
  678. break;
  679. }
  680. stellaris_info->target_name = StellarisParts[i].partname;
  681. stellaris_info->did0 = did0;
  682. stellaris_info->did1 = did1;
  683. stellaris_info->num_lockbits = 1 + (stellaris_info->dc0 & 0xFFFF);
  684. stellaris_info->num_pages = 2 *(1 + (stellaris_info->dc0 & 0xFFFF));
  685. stellaris_info->pagesize = 1024;
  686. stellaris_info->pages_in_lockregion = 2;
  687. /* REVISIT for at least Tempest parts, read NVMSTAT.FWB too.
  688. * That exposes a 32-word Flash Write Buffer ... enabling
  689. * writes of more than one word at a time.
  690. */
  691. return ERROR_OK;
  692. }
  693. /***************************************************************************
  694. * flash operations *
  695. ***************************************************************************/
  696. static int stellaris_protect_check(struct flash_bank *bank)
  697. {
  698. struct stellaris_flash_bank *stellaris = bank->driver_priv;
  699. int status = ERROR_OK;
  700. unsigned i;
  701. unsigned page;
  702. if (stellaris->did1 == 0)
  703. return ERROR_FLASH_BANK_NOT_PROBED;
  704. for (i = 0; i < (unsigned) bank->num_sectors; i++)
  705. bank->sectors[i].is_protected = -1;
  706. /* Read each Flash Memory Protection Program Enable (FMPPE) register
  707. * to report any pages that we can't write. Ignore the Read Enable
  708. * register (FMPRE).
  709. */
  710. for (i = 0, page = 0;
  711. i < DIV_ROUND_UP(stellaris->num_lockbits, 32u);
  712. i++) {
  713. uint32_t lockbits;
  714. status = target_read_u32(bank->target,
  715. SCB_BASE + (i ? (FMPPE0 + 4 * i) : FMPPE),
  716. &lockbits);
  717. LOG_DEBUG("FMPPE%d = %#8.8x (status %d)", i,
  718. (unsigned) lockbits, status);
  719. if (status != ERROR_OK)
  720. goto done;
  721. for (unsigned j = 0; j < 32; j++) {
  722. unsigned k;
  723. for (k = 0; k < stellaris->pages_in_lockregion; k++) {
  724. if (page >= (unsigned) bank->num_sectors)
  725. goto done;
  726. bank->sectors[page++].is_protected =
  727. !(lockbits & (1 << j));
  728. }
  729. }
  730. }
  731. done:
  732. return status;
  733. }
  734. static int stellaris_erase(struct flash_bank *bank, int first, int last)
  735. {
  736. int banknr;
  737. uint32_t flash_fmc, flash_cris;
  738. struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
  739. struct target *target = bank->target;
  740. if (bank->target->state != TARGET_HALTED)
  741. {
  742. LOG_ERROR("Target not halted");
  743. return ERROR_TARGET_NOT_HALTED;
  744. }
  745. if (stellaris_info->did1 == 0)
  746. return ERROR_FLASH_BANK_NOT_PROBED;
  747. if ((first < 0) || (last < first) || (last >= (int)stellaris_info->num_pages))
  748. {
  749. return ERROR_FLASH_SECTOR_INVALID;
  750. }
  751. if ((first == 0) && (last == ((int)stellaris_info->num_pages-1)))
  752. {
  753. return stellaris_mass_erase(bank);
  754. }
  755. /* Refresh flash controller timing */
  756. stellaris_read_clock_info(bank);
  757. stellaris_set_flash_timing(bank);
  758. /* Clear and disable flash programming interrupts */
  759. target_write_u32(target, FLASH_CIM, 0);
  760. target_write_u32(target, FLASH_MISC, PMISC | AMISC);
  761. /* REVISIT this clobbers state set by any halted firmware ...
  762. * it might want to process those IRQs.
  763. */
  764. for (banknr = first; banknr <= last; banknr++)
  765. {
  766. /* Address is first word in page */
  767. target_write_u32(target, FLASH_FMA, banknr * stellaris_info->pagesize);
  768. /* Write erase command */
  769. target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_ERASE);
  770. /* Wait until erase complete */
  771. do
  772. {
  773. target_read_u32(target, FLASH_FMC, &flash_fmc);
  774. }
  775. while (flash_fmc & FMC_ERASE);
  776. /* Check acess violations */
  777. target_read_u32(target, FLASH_CRIS, &flash_cris);
  778. if (flash_cris & (AMASK))
  779. {
  780. LOG_WARNING("Error erasing flash page %i, flash_cris 0x%" PRIx32 "", banknr, flash_cris);
  781. target_write_u32(target, FLASH_CRIS, 0);
  782. return ERROR_FLASH_OPERATION_FAILED;
  783. }
  784. bank->sectors[banknr].is_erased = 1;
  785. }
  786. return ERROR_OK;
  787. }
  788. static int stellaris_protect(struct flash_bank *bank, int set, int first, int last)
  789. {
  790. uint32_t fmppe, flash_fmc, flash_cris;
  791. int lockregion;
  792. struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
  793. struct target *target = bank->target;
  794. if (bank->target->state != TARGET_HALTED)
  795. {
  796. LOG_ERROR("Target not halted");
  797. return ERROR_TARGET_NOT_HALTED;
  798. }
  799. if (!set)
  800. {
  801. LOG_ERROR("Hardware doesn't support page-level unprotect. "
  802. "Try the 'recover' command.");
  803. return ERROR_INVALID_ARGUMENTS;
  804. }
  805. if (stellaris_info->did1 == 0)
  806. return ERROR_FLASH_BANK_NOT_PROBED;
  807. /* lockregions are 2 pages ... must protect [even..odd] */
  808. if ((first < 0) || (first & 1)
  809. || (last < first) || !(last & 1)
  810. || (last >= 2 * stellaris_info->num_lockbits))
  811. {
  812. LOG_ERROR("Can't protect unaligned or out-of-range pages.");
  813. return ERROR_FLASH_SECTOR_INVALID;
  814. }
  815. /* Refresh flash controller timing */
  816. stellaris_read_clock_info(bank);
  817. stellaris_set_flash_timing(bank);
  818. /* convert from pages to lockregions */
  819. first /= 2;
  820. last /= 2;
  821. /* FIXME this assumes single FMPPE, for a max of 64K of flash!!
  822. * Current parts can be much bigger.
  823. */
  824. if (last >= 32) {
  825. LOG_ERROR("No support yet for protection > 64K");
  826. return ERROR_FLASH_OPERATION_FAILED;
  827. }
  828. target_read_u32(target, SCB_BASE | FMPPE, &fmppe);
  829. for (lockregion = first; lockregion <= last; lockregion++)
  830. fmppe &= ~(1 << lockregion);
  831. /* Clear and disable flash programming interrupts */
  832. target_write_u32(target, FLASH_CIM, 0);
  833. target_write_u32(target, FLASH_MISC, PMISC | AMISC);
  834. /* REVISIT this clobbers state set by any halted firmware ...
  835. * it might want to process those IRQs.
  836. */
  837. LOG_DEBUG("fmppe 0x%" PRIx32 "",fmppe);
  838. target_write_u32(target, SCB_BASE | FMPPE, fmppe);
  839. /* Commit FMPPE */
  840. target_write_u32(target, FLASH_FMA, 1);
  841. /* Write commit command */
  842. /* REVISIT safety check, since this cannot be undone
  843. * except by the "Recover a locked device" procedure.
  844. * REVISIT DustDevil-A0 parts have an erratum making FMPPE commits
  845. * inadvisable ... it makes future mass erase operations fail.
  846. */
  847. LOG_WARNING("Flash protection cannot be removed once committed, commit is NOT executed !");
  848. /* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */
  849. /* Wait until erase complete */
  850. do
  851. {
  852. target_read_u32(target, FLASH_FMC, &flash_fmc);
  853. }
  854. while (flash_fmc & FMC_COMT);
  855. /* Check acess violations */
  856. target_read_u32(target, FLASH_CRIS, &flash_cris);
  857. if (flash_cris & (AMASK))
  858. {
  859. LOG_WARNING("Error setting flash page protection, flash_cris 0x%" PRIx32 "", flash_cris);
  860. target_write_u32(target, FLASH_CRIS, 0);
  861. return ERROR_FLASH_OPERATION_FAILED;
  862. }
  863. return ERROR_OK;
  864. }
  865. /* see contib/loaders/flash/stellaris.s for src */
  866. static const uint8_t stellaris_write_code[] =
  867. {
  868. /*
  869. Call with :
  870. r0 = buffer address
  871. r1 = destination address
  872. r2 = bytecount (in) - endaddr (work)
  873. Used registers:
  874. r3 = pFLASH_CTRL_BASE
  875. r4 = FLASHWRITECMD
  876. r5 = #1
  877. r6 = bytes written
  878. r7 = temp reg
  879. */
  880. 0x07,0x4B, /* ldr r3,pFLASH_CTRL_BASE */
  881. 0x08,0x4C, /* ldr r4,FLASHWRITECMD */
  882. 0x01,0x25, /* movs r5, 1 */
  883. 0x00,0x26, /* movs r6, #0 */
  884. /* mainloop: */
  885. 0x19,0x60, /* str r1, [r3, #0] */
  886. 0x87,0x59, /* ldr r7, [r0, r6] */
  887. 0x5F,0x60, /* str r7, [r3, #4] */
  888. 0x9C,0x60, /* str r4, [r3, #8] */
  889. /* waitloop: */
  890. 0x9F,0x68, /* ldr r7, [r3, #8] */
  891. 0x2F,0x42, /* tst r7, r5 */
  892. 0xFC,0xD1, /* bne waitloop */
  893. 0x04,0x31, /* adds r1, r1, #4 */
  894. 0x04,0x36, /* adds r6, r6, #4 */
  895. 0x96,0x42, /* cmp r6, r2 */
  896. 0xF4,0xD1, /* bne mainloop */
  897. 0x00,0xBE, /* bkpt #0 */
  898. /* pFLASH_CTRL_BASE: */
  899. 0x00,0xD0,0x0F,0x40, /* .word 0x400FD000 */
  900. /* FLASHWRITECMD: */
  901. 0x01,0x00,0x42,0xA4 /* .word 0xA4420001 */
  902. };
  903. static int stellaris_write_block(struct flash_bank *bank,
  904. uint8_t *buffer, uint32_t offset, uint32_t wcount)
  905. {
  906. struct target *target = bank->target;
  907. uint32_t buffer_size = 16384;
  908. struct working_area *source;
  909. struct working_area *write_algorithm;
  910. uint32_t address = bank->base + offset;
  911. struct reg_param reg_params[3];
  912. struct armv7m_algorithm armv7m_info;
  913. int retval = ERROR_OK;
  914. /* power of two, and multiple of word size */
  915. static const unsigned buf_min = 128;
  916. /* for small buffers it's faster not to download an algorithm */
  917. if (wcount * 4 < buf_min)
  918. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  919. LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32 "",
  920. bank, buffer, offset, wcount);
  921. /* flash write code */
  922. if (target_alloc_working_area(target, sizeof(stellaris_write_code), &write_algorithm) != ERROR_OK)
  923. {
  924. LOG_DEBUG("no working area for block memory writes");
  925. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  926. };
  927. /* plus a buffer big enough for this data */
  928. if (wcount * 4 < buffer_size)
  929. buffer_size = wcount * 4;
  930. /* memory buffer */
  931. while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
  932. {
  933. buffer_size /= 2;
  934. if (buffer_size <= buf_min)
  935. {
  936. target_free_working_area(target, write_algorithm);
  937. return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
  938. }
  939. LOG_DEBUG("retry target_alloc_working_area(%s, size=%u)",
  940. target_name(target), (unsigned) buffer_size);
  941. };
  942. retval = target_write_buffer(target, write_algorithm->address,
  943. sizeof(stellaris_write_code),
  944. (uint8_t *) stellaris_write_code);
  945. armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
  946. armv7m_info.core_mode = ARMV7M_MODE_ANY;
  947. init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
  948. init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
  949. init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
  950. while (wcount > 0)
  951. {
  952. uint32_t thisrun_count = (wcount > (buffer_size / 4)) ? (buffer_size / 4) : wcount;
  953. target_write_buffer(target, source->address, thisrun_count * 4, buffer);
  954. buf_set_u32(reg_params[0].value, 0, 32, source->address);
  955. buf_set_u32(reg_params[1].value, 0, 32, address);
  956. buf_set_u32(reg_params[2].value, 0, 32, 4*thisrun_count);
  957. LOG_DEBUG("Algorithm flash write %u words to 0x%" PRIx32
  958. ", %u remaining",
  959. (unsigned) thisrun_count, address,
  960. (unsigned) (wcount - thisrun_count));
  961. retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
  962. write_algorithm->address,
  963. 0,
  964. 10000, &armv7m_info);
  965. if (retval != ERROR_OK)
  966. {
  967. LOG_ERROR("error %d executing stellaris "
  968. "flash write algorithm",
  969. retval);
  970. retval = ERROR_FLASH_OPERATION_FAILED;
  971. break;
  972. }
  973. buffer += thisrun_count * 4;
  974. address += thisrun_count * 4;
  975. wcount -= thisrun_count;
  976. }
  977. /* REVISIT we could speed up writing multi-section images by
  978. * not freeing the initialized write_algorithm this way.
  979. */
  980. target_free_working_area(target, write_algorithm);
  981. target_free_working_area(target, source);
  982. destroy_reg_param(&reg_params[0]);
  983. destroy_reg_param(&reg_params[1]);
  984. destroy_reg_param(&reg_params[2]);
  985. return retval;
  986. }
  987. static int stellaris_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
  988. {
  989. struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
  990. struct target *target = bank->target;
  991. uint32_t address = offset;
  992. uint32_t flash_cris, flash_fmc;
  993. uint32_t words_remaining = (count / 4);
  994. uint32_t bytes_remaining = (count & 0x00000003);
  995. uint32_t bytes_written = 0;
  996. int retval;
  997. if (bank->target->state != TARGET_HALTED)
  998. {
  999. LOG_ERROR("Target not halted");
  1000. return ERROR_TARGET_NOT_HALTED;
  1001. }
  1002. LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " count=%08" PRIx32 "",
  1003. bank, buffer, offset, count);
  1004. if (stellaris_info->did1 == 0)
  1005. return ERROR_FLASH_BANK_NOT_PROBED;
  1006. if (offset & 0x3)
  1007. {
  1008. LOG_WARNING("offset size must be word aligned");
  1009. return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
  1010. }
  1011. if (offset + count > bank->size)
  1012. return ERROR_FLASH_DST_OUT_OF_BANK;
  1013. /* Refresh flash controller timing */
  1014. stellaris_read_clock_info(bank);
  1015. stellaris_set_flash_timing(bank);
  1016. /* Clear and disable flash programming interrupts */
  1017. target_write_u32(target, FLASH_CIM, 0);
  1018. target_write_u32(target, FLASH_MISC, PMISC | AMISC);
  1019. /* REVISIT this clobbers state set by any halted firmware ...
  1020. * it might want to process those IRQs.
  1021. */
  1022. /* multiple words to be programmed? */
  1023. if (words_remaining > 0)
  1024. {
  1025. /* try using a block write */
  1026. retval = stellaris_write_block(bank, buffer, offset,
  1027. words_remaining);
  1028. if (retval != ERROR_OK)
  1029. {
  1030. if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
  1031. {
  1032. LOG_DEBUG("writing flash word-at-a-time");
  1033. }
  1034. else if (retval == ERROR_FLASH_OPERATION_FAILED)
  1035. {
  1036. /* if an error occured, we examine the reason, and quit */
  1037. target_read_u32(target, FLASH_CRIS, &flash_cris);
  1038. LOG_ERROR("flash writing failed with CRIS: 0x%" PRIx32 "", flash_cris);
  1039. return ERROR_FLASH_OPERATION_FAILED;
  1040. }
  1041. }
  1042. else
  1043. {
  1044. buffer += words_remaining * 4;
  1045. address += words_remaining * 4;
  1046. words_remaining = 0;
  1047. }
  1048. }
  1049. while (words_remaining > 0)
  1050. {
  1051. if (!(address & 0xff))
  1052. LOG_DEBUG("0x%" PRIx32 "", address);
  1053. /* Program one word */
  1054. target_write_u32(target, FLASH_FMA, address);
  1055. target_write_buffer(target, FLASH_FMD, 4, buffer);
  1056. target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);
  1057. /* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
  1058. /* Wait until write complete */
  1059. do
  1060. {
  1061. target_read_u32(target, FLASH_FMC, &flash_fmc);
  1062. } while (flash_fmc & FMC_WRITE);
  1063. buffer += 4;
  1064. address += 4;
  1065. words_remaining--;
  1066. }
  1067. if (bytes_remaining)
  1068. {
  1069. uint8_t last_word[4] = {0xff, 0xff, 0xff, 0xff};
  1070. int i = 0;
  1071. while (bytes_remaining > 0)
  1072. {
  1073. last_word[i++] = *(buffer + bytes_written);
  1074. bytes_remaining--;
  1075. bytes_written++;
  1076. }
  1077. if (!(address & 0xff))
  1078. LOG_DEBUG("0x%" PRIx32 "", address);
  1079. /* Program one word */
  1080. target_write_u32(target, FLASH_FMA, address);
  1081. target_write_buffer(target, FLASH_FMD, 4, last_word);
  1082. target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);
  1083. /* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
  1084. /* Wait until write complete */
  1085. do
  1086. {
  1087. target_read_u32(target, FLASH_FMC, &flash_fmc);
  1088. } while (flash_fmc & FMC_WRITE);
  1089. }
  1090. /* Check access violations */
  1091. target_read_u32(target, FLASH_CRIS, &flash_cris);
  1092. if (flash_cris & (AMASK))
  1093. {
  1094. LOG_DEBUG("flash_cris 0x%" PRIx32 "", flash_cris);
  1095. return ERROR_FLASH_OPERATION_FAILED;
  1096. }
  1097. return ERROR_OK;
  1098. }
  1099. static int stellaris_probe(struct flash_bank *bank)
  1100. {
  1101. struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
  1102. int retval;
  1103. /* If this is a stellaris chip, it has flash; probe() is just
  1104. * to figure out how much is present. Only do it once.
  1105. */
  1106. if (stellaris_info->did1 != 0)
  1107. return ERROR_OK;
  1108. /* stellaris_read_part_info() already handled error checking and
  1109. * reporting. Note that it doesn't write, so we don't care about
  1110. * whether the target is halted or not.
  1111. */
  1112. retval = stellaris_read_part_info(bank);
  1113. if (retval != ERROR_OK)
  1114. return retval;
  1115. if (bank->sectors)
  1116. {
  1117. free(bank->sectors);
  1118. bank->sectors = NULL;
  1119. }
  1120. /* provide this for the benefit of the NOR flash framework */
  1121. bank->size = 1024 * stellaris_info->num_pages;
  1122. bank->num_sectors = stellaris_info->num_pages;
  1123. bank->sectors = calloc(bank->num_sectors, sizeof(struct flash_sector));
  1124. for (int i = 0; i < bank->num_sectors; i++)
  1125. {
  1126. bank->sectors[i].offset = i * stellaris_info->pagesize;
  1127. bank->sectors[i].size = stellaris_info->pagesize;
  1128. bank->sectors[i].is_erased = -1;
  1129. bank->sectors[i].is_protected = -1;
  1130. }
  1131. return retval;
  1132. }
  1133. static int stellaris_mass_erase(struct flash_bank *bank)
  1134. {
  1135. struct target *target = NULL;
  1136. struct stellaris_flash_bank *stellaris_info = NULL;
  1137. uint32_t flash_fmc;
  1138. stellaris_info = bank->driver_priv;
  1139. target = bank->target;
  1140. if (target->state != TARGET_HALTED)
  1141. {
  1142. LOG_ERROR("Target not halted");
  1143. return ERROR_TARGET_NOT_HALTED;
  1144. }
  1145. if (stellaris_info->did1 == 0)
  1146. return ERROR_FLASH_BANK_NOT_PROBED;
  1147. /* Refresh flash controller timing */
  1148. stellaris_read_clock_info(bank);
  1149. stellaris_set_flash_timing(bank);
  1150. /* Clear and disable flash programming interrupts */
  1151. target_write_u32(target, FLASH_CIM, 0);
  1152. target_write_u32(target, FLASH_MISC, PMISC | AMISC);
  1153. /* REVISIT this clobbers state set by any halted firmware ...
  1154. * it might want to process those IRQs.
  1155. */
  1156. target_write_u32(target, FLASH_FMA, 0);
  1157. target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
  1158. /* Wait until erase complete */
  1159. do
  1160. {
  1161. target_read_u32(target, FLASH_FMC, &flash_fmc);
  1162. }
  1163. while (flash_fmc & FMC_MERASE);
  1164. /* if device has > 128k, then second erase cycle is needed
  1165. * this is only valid for older devices, but will not hurt */
  1166. if (stellaris_info->num_pages * stellaris_info->pagesize > 0x20000)
  1167. {
  1168. target_write_u32(target, FLASH_FMA, 0x20000);
  1169. target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
  1170. /* Wait until erase complete */
  1171. do
  1172. {
  1173. target_read_u32(target, FLASH_FMC, &flash_fmc);
  1174. }
  1175. while (flash_fmc & FMC_MERASE);
  1176. }
  1177. return ERROR_OK;
  1178. }
  1179. COMMAND_HANDLER(stellaris_handle_mass_erase_command)
  1180. {
  1181. int i;
  1182. if (CMD_ARGC < 1)
  1183. {
  1184. command_print(CMD_CTX, "stellaris mass_erase <bank>");
  1185. return ERROR_OK;
  1186. }
  1187. struct flash_bank *bank;
  1188. int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  1189. if (ERROR_OK != retval)
  1190. return retval;
  1191. if (stellaris_mass_erase(bank) == ERROR_OK)
  1192. {
  1193. /* set all sectors as erased */
  1194. for (i = 0; i < bank->num_sectors; i++)
  1195. {
  1196. bank->sectors[i].is_erased = 1;
  1197. }
  1198. command_print(CMD_CTX, "stellaris mass erase complete");
  1199. }
  1200. else
  1201. {
  1202. command_print(CMD_CTX, "stellaris mass erase failed");
  1203. }
  1204. return ERROR_OK;
  1205. }
  1206. /**
  1207. * Perform the Stellaris "Recovering a 'Locked' Device procedure.
  1208. * This performs a mass erase and then restores all nonvolatile registers
  1209. * (including USER_* registers and flash lock bits) to their defaults.
  1210. * Accordingly, flash can be reprogrammed, and JTAG can be used.
  1211. *
  1212. * NOTE that DustDevil parts (at least rev A0 silicon) have errata which
  1213. * can affect this operation if flash protection has been enabled.
  1214. */
  1215. COMMAND_HANDLER(stellaris_handle_recover_command)
  1216. {
  1217. struct flash_bank *bank;
  1218. int retval;
  1219. retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
  1220. if (retval != ERROR_OK)
  1221. return retval;
  1222. /* REVISIT ... it may be worth sanity checking that the AP is
  1223. * inactive before we start. ARM documents that switching a DP's
  1224. * mode while it's active can cause fault modes that need a power
  1225. * cycle to recover.
  1226. */
  1227. /* assert SRST */
  1228. if (!(jtag_get_reset_config() & RESET_HAS_SRST)) {
  1229. LOG_ERROR("Can't recover Stellaris flash without SRST");
  1230. return ERROR_FAIL;
  1231. }
  1232. jtag_add_reset(0, 1);
  1233. for (int i = 0; i < 5; i++) {
  1234. retval = dap_to_swd(bank->target);
  1235. if (retval != ERROR_OK)
  1236. goto done;
  1237. retval = dap_to_jtag(bank->target);
  1238. if (retval != ERROR_OK)
  1239. goto done;
  1240. }
  1241. /* de-assert SRST */
  1242. jtag_add_reset(0, 0);
  1243. retval = jtag_execute_queue();
  1244. /* wait 400+ msec ... OK, "1+ second" is simpler */
  1245. usleep(1000);
  1246. /* USER INTERVENTION required for the power cycle
  1247. * Restarting OpenOCD is likely needed because of mode switching.
  1248. */
  1249. LOG_INFO("USER ACTION: "
  1250. "power cycle Stellaris chip, then restart OpenOCD.");
  1251. done:
  1252. return retval;
  1253. }
  1254. static const struct command_registration stellaris_exec_command_handlers[] = {
  1255. {
  1256. .name = "mass_erase",
  1257. .handler = stellaris_handle_mass_erase_command,
  1258. .mode = COMMAND_EXEC,
  1259. .usage = "bank_id",
  1260. .help = "erase entire device",
  1261. },
  1262. {
  1263. .name = "recover",
  1264. .handler = stellaris_handle_recover_command,
  1265. .mode = COMMAND_EXEC,
  1266. .usage = "bank_id",
  1267. .help = "recover (and erase) locked device",
  1268. },
  1269. COMMAND_REGISTRATION_DONE
  1270. };
  1271. static const struct command_registration stellaris_command_handlers[] = {
  1272. {
  1273. .name = "stellaris",
  1274. .mode = COMMAND_EXEC,
  1275. .help = "Stellaris flash command group",
  1276. .chain = stellaris_exec_command_handlers,
  1277. },
  1278. COMMAND_REGISTRATION_DONE
  1279. };
  1280. struct flash_driver stellaris_flash = {
  1281. .name = "stellaris",
  1282. .commands = stellaris_command_handlers,
  1283. .flash_bank_command = stellaris_flash_bank_command,
  1284. .erase = stellaris_erase,
  1285. .protect = stellaris_protect,
  1286. .write = stellaris_write,
  1287. .read = default_flash_read,
  1288. .probe = stellaris_probe,
  1289. .auto_probe = stellaris_probe,
  1290. .erase_check = default_flash_mem_blank_check,
  1291. .protect_check = stellaris_protect_check,
  1292. .info = get_stellaris_info,
  1293. };