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89 lines
2.0 KiB

  1. source [find target/lpc3250.cfg]
  2. adapter_nsrst_delay 200
  3. jtag_ntrst_delay 1
  4. adapter_khz 200
  5. reset_config trst_and_srst separate
  6. arm7_9 dcc_downloads enable
  7. $_TARGETNAME configure -event gdb-attach { reset init }
  8. $_TARGETNAME configure -event reset-start {
  9. arm7_9 fast_memory_access disable
  10. adapter_khz 200
  11. }
  12. $_TARGETNAME configure -event reset-end {
  13. adapter_khz 6000
  14. arm7_9 fast_memory_access enable
  15. }
  16. $_TARGETNAME configure -event reset-init { phytec_lpc3250_init }
  17. # Bare-bones initialization of core clocks and SDRAM
  18. proc phytec_lpc3250_init { } {
  19. # Set clock dividers
  20. # ARMCLK = 266.5 MHz
  21. # HCLK = 133.25 MHz
  22. # PERIPHCLK = 13.325 MHz
  23. mww 0x400040BC 0
  24. mww 0x40004050 0x140
  25. mww 0x40004040 0x4D
  26. mww 0x40004058 0x16250
  27. # Init PLLs
  28. mww 0x40004044 0x006
  29. sleep 1 busy
  30. mww 0x40004044 0x106
  31. sleep 1 busy
  32. mww 0x40004044 0x006
  33. sleep 1 busy
  34. mww 0x40004048 0x2
  35. # Init SDRAM with 133 MHz timings
  36. mww 0x40028134 0x00FFFFFF
  37. mww 0x4002802C 0x00000008
  38. mww 0x31080000 1
  39. mww 0x31080008 0
  40. mww 0x40004068 0x1C000
  41. mww 0x31080028 0x11
  42. mww 0x31080400 0
  43. mww 0x31080440 0
  44. mww 0x31080460 0
  45. mww 0x31080480 0
  46. # Delays
  47. mww 0x31080030 1
  48. mww 0x31080034 6
  49. mww 0x31080038 10
  50. mww 0x31080044 1
  51. mww 0x31080048 9
  52. mww 0x3108004C 12
  53. mww 0x31080050 10
  54. mww 0x31080054 1
  55. mww 0x31080058 1
  56. mww 0x3108005C 0
  57. mww 0x31080100 0x5680
  58. mww 0x31080104 0x302
  59. # Init sequence
  60. mww 0x31080020 0x193
  61. sleep 1 busy
  62. mww 0x31080024 1
  63. mww 0x31080020 0x113
  64. sleep 1 busy
  65. mww 0x31080020 0x013
  66. sleep 1 busy
  67. mww 0x31080024 65
  68. mww 0x31080020 0x093
  69. mdw 0x80020000
  70. mww 0x31080020 0x013
  71. # SYS_CTRL remapping
  72. mww 0x40004014 1
  73. }