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  1. /***************************************************************************
  2. * Copyright (C) 2005 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * Copyright (C) 2006 by Magnus Lundin *
  6. * lundin@mlu.mine.nu *
  7. * *
  8. * Copyright (C) 2008 by Spencer Oliver *
  9. * spen@spen-soft.co.uk *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  25. ***************************************************************************/
  26. #ifndef ARMV7M_COMMON_H
  27. #define ARMV7M_COMMON_H
  28. #include "arm_adi_v5.h"
  29. #include "arm.h"
  30. /* define for enabling armv7 gdb workarounds */
  31. #if 1
  32. #define ARMV7_GDB_HACKS
  33. #endif
  34. #ifdef ARMV7_GDB_HACKS
  35. extern uint8_t armv7m_gdb_dummy_cpsr_value[];
  36. extern struct reg armv7m_gdb_dummy_cpsr_reg;
  37. #endif
  38. enum armv7m_mode {
  39. ARMV7M_MODE_THREAD = 0,
  40. ARMV7M_MODE_USER_THREAD = 1,
  41. ARMV7M_MODE_HANDLER = 2,
  42. ARMV7M_MODE_ANY = -1
  43. };
  44. extern char *armv7m_mode_strings[];
  45. extern const int armv7m_psp_reg_map[];
  46. extern const int armv7m_msp_reg_map[];
  47. enum armv7m_regtype {
  48. ARMV7M_REGISTER_CORE_GP,
  49. ARMV7M_REGISTER_CORE_SP,
  50. ARMV7M_REGISTER_MEMMAP
  51. };
  52. char *armv7m_exception_string(int number);
  53. /* offsets into armv7m core register cache */
  54. enum {
  55. /* for convenience, the first set of indices match
  56. * the Cortex-M3/-M4 DCRSR selectors
  57. */
  58. ARMV7M_R0,
  59. ARMV7M_R1,
  60. ARMV7M_R2,
  61. ARMV7M_R3,
  62. ARMV7M_R4,
  63. ARMV7M_R5,
  64. ARMV7M_R6,
  65. ARMV7M_R7,
  66. ARMV7M_R8,
  67. ARMV7M_R9,
  68. ARMV7M_R10,
  69. ARMV7M_R11,
  70. ARMV7M_R12,
  71. ARMV7M_R13,
  72. ARMV7M_R14,
  73. ARMV7M_PC = 15,
  74. ARMV7M_xPSR = 16,
  75. ARMV7M_MSP,
  76. ARMV7M_PSP,
  77. /* this next set of indices is arbitrary */
  78. ARMV7M_PRIMASK,
  79. ARMV7M_BASEPRI,
  80. ARMV7M_FAULTMASK,
  81. ARMV7M_CONTROL,
  82. /* 32bit Floating-point registers */
  83. ARMV7M_S0,
  84. ARMV7M_S1,
  85. ARMV7M_S2,
  86. ARMV7M_S3,
  87. ARMV7M_S4,
  88. ARMV7M_S5,
  89. ARMV7M_S6,
  90. ARMV7M_S7,
  91. ARMV7M_S8,
  92. ARMV7M_S9,
  93. ARMV7M_S10,
  94. ARMV7M_S11,
  95. ARMV7M_S12,
  96. ARMV7M_S13,
  97. ARMV7M_S14,
  98. ARMV7M_S15,
  99. ARMV7M_S16,
  100. ARMV7M_S17,
  101. ARMV7M_S18,
  102. ARMV7M_S19,
  103. ARMV7M_S20,
  104. ARMV7M_S21,
  105. ARMV7M_S22,
  106. ARMV7M_S23,
  107. ARMV7M_S24,
  108. ARMV7M_S25,
  109. ARMV7M_S26,
  110. ARMV7M_S27,
  111. ARMV7M_S28,
  112. ARMV7M_S29,
  113. ARMV7M_S30,
  114. ARMV7M_S31,
  115. /* 64bit Floating-point registers */
  116. ARMV7M_D0,
  117. ARMV7M_D1,
  118. ARMV7M_D2,
  119. ARMV7M_D3,
  120. ARMV7M_D4,
  121. ARMV7M_D5,
  122. ARMV7M_D6,
  123. ARMV7M_D7,
  124. ARMV7M_D8,
  125. ARMV7M_D9,
  126. ARMV7M_D10,
  127. ARMV7M_D11,
  128. ARMV7M_D12,
  129. ARMV7M_D13,
  130. ARMV7M_D14,
  131. ARMV7M_D15,
  132. /* Floating-point status registers */
  133. ARMV7M_FPSID,
  134. ARMV7M_FPSCR,
  135. ARMV7M_FPEXC,
  136. ARMV7M_LAST_REG,
  137. };
  138. enum {
  139. FP_NONE = 0,
  140. FPv4_SP,
  141. };
  142. #define ARMV7M_COMMON_MAGIC 0x2A452A45
  143. struct armv7m_common {
  144. struct arm arm;
  145. int common_magic;
  146. struct reg_cache *core_cache;
  147. enum armv7m_mode core_mode;
  148. int exception_number;
  149. struct adiv5_dap dap;
  150. int fp_feature;
  151. uint32_t demcr;
  152. /* stlink is a high level adapter, does not support all functions */
  153. bool stlink;
  154. /* Direct processor core register read and writes */
  155. int (*load_core_reg_u32)(struct target *target,
  156. enum armv7m_regtype type, uint32_t num, uint32_t *value);
  157. int (*store_core_reg_u32)(struct target *target,
  158. enum armv7m_regtype type, uint32_t num, uint32_t value);
  159. /* register cache to processor synchronization */
  160. int (*read_core_reg)(struct target *target, unsigned num);
  161. int (*write_core_reg)(struct target *target, unsigned num);
  162. int (*examine_debug_reason)(struct target *target);
  163. int (*post_debug_entry)(struct target *target);
  164. void (*pre_restore_context)(struct target *target);
  165. };
  166. static inline struct armv7m_common *
  167. target_to_armv7m(struct target *target)
  168. {
  169. return container_of(target->arch_info, struct armv7m_common, arm);
  170. }
  171. static inline bool is_armv7m(struct armv7m_common *armv7m)
  172. {
  173. return armv7m->common_magic == ARMV7M_COMMON_MAGIC;
  174. }
  175. struct armv7m_algorithm {
  176. int common_magic;
  177. enum armv7m_mode core_mode;
  178. uint32_t context[ARMV7M_LAST_REG]; /* ARMV7M_NUM_REGS */
  179. };
  180. struct armv7m_core_reg {
  181. uint32_t num;
  182. enum armv7m_regtype type;
  183. struct target *target;
  184. struct armv7m_common *armv7m_common;
  185. };
  186. struct reg_cache *armv7m_build_reg_cache(struct target *target);
  187. enum armv7m_mode armv7m_number_to_mode(int number);
  188. int armv7m_mode_to_number(enum armv7m_mode mode);
  189. int armv7m_arch_state(struct target *target);
  190. int armv7m_get_gdb_reg_list(struct target *target,
  191. struct reg **reg_list[], int *reg_list_size);
  192. int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m);
  193. int armv7m_run_algorithm(struct target *target,
  194. int num_mem_params, struct mem_param *mem_params,
  195. int num_reg_params, struct reg_param *reg_params,
  196. uint32_t entry_point, uint32_t exit_point,
  197. int timeout_ms, void *arch_info);
  198. int armv7m_start_algorithm(struct target *target,
  199. int num_mem_params, struct mem_param *mem_params,
  200. int num_reg_params, struct reg_param *reg_params,
  201. uint32_t entry_point, uint32_t exit_point,
  202. void *arch_info);
  203. int armv7m_wait_algorithm(struct target *target,
  204. int num_mem_params, struct mem_param *mem_params,
  205. int num_reg_params, struct reg_param *reg_params,
  206. uint32_t exit_point, int timeout_ms,
  207. void *arch_info);
  208. int armv7m_invalidate_core_regs(struct target *target);
  209. int armv7m_restore_context(struct target *target);
  210. int armv7m_checksum_memory(struct target *target,
  211. uint32_t address, uint32_t count, uint32_t *checksum);
  212. int armv7m_blank_check_memory(struct target *target,
  213. uint32_t address, uint32_t count, uint32_t *blank);
  214. int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found);
  215. extern const struct command_registration armv7m_command_handlers[];
  216. #endif /* ARMV7M_H */