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  1. /***************************************************************************
  2. * Copyright (C) 2007 by Dominic Rath *
  3. * Dominic.Rath@gmx.de *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. #ifdef HAVE_CONFIG_H
  21. #include "config.h"
  22. #endif
  23. #include "arm926ejs.h"
  24. #include "time_support.h"
  25. #include "target_type.h"
  26. #if 0
  27. #define _DEBUG_INSTRUCTION_EXECUTION_
  28. #endif
  29. /* cli handling */
  30. int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  31. int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  32. int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  33. int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  34. int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  35. int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  36. int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  37. int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  38. /* forward declarations */
  39. int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
  40. int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  41. int arm926ejs_quit(void);
  42. int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  43. static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
  44. static int arm926ejs_mmu(struct target_s *target, int *enabled);
  45. target_type_t arm926ejs_target =
  46. {
  47. .name = "arm926ejs",
  48. .poll = arm7_9_poll,
  49. .arch_state = arm926ejs_arch_state,
  50. .target_request_data = arm7_9_target_request_data,
  51. .halt = arm7_9_halt,
  52. .resume = arm7_9_resume,
  53. .step = arm7_9_step,
  54. .assert_reset = arm7_9_assert_reset,
  55. .deassert_reset = arm7_9_deassert_reset,
  56. .soft_reset_halt = arm926ejs_soft_reset_halt,
  57. .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  58. .read_memory = arm7_9_read_memory,
  59. .write_memory = arm926ejs_write_memory,
  60. .bulk_write_memory = arm7_9_bulk_write_memory,
  61. .checksum_memory = arm7_9_checksum_memory,
  62. .blank_check_memory = arm7_9_blank_check_memory,
  63. .run_algorithm = armv4_5_run_algorithm,
  64. .add_breakpoint = arm7_9_add_breakpoint,
  65. .remove_breakpoint = arm7_9_remove_breakpoint,
  66. .add_watchpoint = arm7_9_add_watchpoint,
  67. .remove_watchpoint = arm7_9_remove_watchpoint,
  68. .register_commands = arm926ejs_register_commands,
  69. .target_create = arm926ejs_target_create,
  70. .init_target = arm926ejs_init_target,
  71. .examine = arm9tdmi_examine,
  72. .quit = arm926ejs_quit,
  73. .virt2phys = arm926ejs_virt2phys,
  74. .mmu = arm926ejs_mmu
  75. };
  76. int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
  77. {
  78. /* FIX!!!! this code should be reenabled. For now it does not check
  79. * the queue...*/
  80. return 0;
  81. #if 0
  82. /* The ARM926EJ-S' instruction register is 4 bits wide */
  83. u8 t = *captured & 0xf;
  84. u8 t2 = *field->in_check_value & 0xf;
  85. if (t == t2)
  86. {
  87. return ERROR_OK;
  88. }
  89. else if ((t == 0x0f) || (t == 0x00))
  90. {
  91. LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
  92. return ERROR_OK;
  93. }
  94. return ERROR_JTAG_QUEUE_FAILED;;
  95. #endif
  96. }
  97. #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
  98. int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
  99. {
  100. int retval = ERROR_OK;
  101. armv4_5_common_t *armv4_5 = target->arch_info;
  102. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  103. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  104. u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
  105. scan_field_t fields[4];
  106. u8 address_buf[2];
  107. u8 nr_w_buf = 0;
  108. u8 access = 1;
  109. buf_set_u32(address_buf, 0, 14, address);
  110. jtag_add_end_state(TAP_IDLE);
  111. if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
  112. {
  113. return retval;
  114. }
  115. arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
  116. fields[0].tap = jtag_info->tap;
  117. fields[0].num_bits = 32;
  118. fields[0].out_value = NULL;
  119. fields[0].in_value = (u8 *)value;
  120. fields[1].tap = jtag_info->tap;
  121. fields[1].num_bits = 1;
  122. fields[1].out_value = &access;
  123. fields[1].in_value = &access;
  124. fields[2].tap = jtag_info->tap;
  125. fields[2].num_bits = 14;
  126. fields[2].out_value = address_buf;
  127. fields[2].in_value = NULL;
  128. fields[3].tap = jtag_info->tap;
  129. fields[3].num_bits = 1;
  130. fields[3].out_value = &nr_w_buf;
  131. fields[3].in_value = NULL;
  132. jtag_add_dr_scan(4, fields, jtag_get_end_state());
  133. /*TODO: add timeout*/
  134. do
  135. {
  136. /* rescan with NOP, to wait for the access to complete */
  137. access = 0;
  138. nr_w_buf = 0;
  139. jtag_add_dr_scan(4, fields, jtag_get_end_state());
  140. jtag_add_callback(arm_le_to_h_u32, (u8 *)value);
  141. if ((retval = jtag_execute_queue()) != ERROR_OK)
  142. {
  143. return retval;
  144. }
  145. } while (buf_get_u32(&access, 0, 1) != 1);
  146. #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  147. LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
  148. #endif
  149. arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
  150. return ERROR_OK;
  151. }
  152. int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
  153. {
  154. int retval = ERROR_OK;
  155. armv4_5_common_t *armv4_5 = target->arch_info;
  156. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  157. arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  158. u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
  159. scan_field_t fields[4];
  160. u8 value_buf[4];
  161. u8 address_buf[2];
  162. u8 nr_w_buf = 1;
  163. u8 access = 1;
  164. buf_set_u32(address_buf, 0, 14, address);
  165. buf_set_u32(value_buf, 0, 32, value);
  166. jtag_add_end_state(TAP_IDLE);
  167. if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
  168. {
  169. return retval;
  170. }
  171. arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
  172. fields[0].tap = jtag_info->tap;
  173. fields[0].num_bits = 32;
  174. fields[0].out_value = value_buf;
  175. fields[0].in_value = NULL;
  176. fields[1].tap = jtag_info->tap;
  177. fields[1].num_bits = 1;
  178. fields[1].out_value = &access;
  179. fields[1].in_value = &access;
  180. fields[2].tap = jtag_info->tap;
  181. fields[2].num_bits = 14;
  182. fields[2].out_value = address_buf;
  183. fields[2].in_value = NULL;
  184. fields[3].tap = jtag_info->tap;
  185. fields[3].num_bits = 1;
  186. fields[3].out_value = &nr_w_buf;
  187. fields[3].in_value = NULL;
  188. jtag_add_dr_scan(4, fields, jtag_get_end_state());
  189. /*TODO: add timeout*/
  190. do
  191. {
  192. /* rescan with NOP, to wait for the access to complete */
  193. access = 0;
  194. nr_w_buf = 0;
  195. jtag_add_dr_scan(4, fields, jtag_get_end_state());
  196. if ((retval = jtag_execute_queue()) != ERROR_OK)
  197. {
  198. return retval;
  199. }
  200. } while (buf_get_u32(&access, 0, 1) != 1);
  201. #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  202. LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
  203. #endif
  204. arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
  205. return ERROR_OK;
  206. }
  207. int arm926ejs_examine_debug_reason(target_t *target)
  208. {
  209. armv4_5_common_t *armv4_5 = target->arch_info;
  210. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  211. reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  212. int debug_reason;
  213. int retval;
  214. embeddedice_read_reg(dbg_stat);
  215. if ((retval = jtag_execute_queue()) != ERROR_OK)
  216. return retval;
  217. debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
  218. switch (debug_reason)
  219. {
  220. case 1:
  221. LOG_DEBUG("breakpoint from EICE unit 0");
  222. target->debug_reason = DBG_REASON_BREAKPOINT;
  223. break;
  224. case 2:
  225. LOG_DEBUG("breakpoint from EICE unit 1");
  226. target->debug_reason = DBG_REASON_BREAKPOINT;
  227. break;
  228. case 3:
  229. LOG_DEBUG("soft breakpoint (BKPT instruction)");
  230. target->debug_reason = DBG_REASON_BREAKPOINT;
  231. break;
  232. case 4:
  233. LOG_DEBUG("vector catch breakpoint");
  234. target->debug_reason = DBG_REASON_BREAKPOINT;
  235. break;
  236. case 5:
  237. LOG_DEBUG("external breakpoint");
  238. target->debug_reason = DBG_REASON_BREAKPOINT;
  239. break;
  240. case 6:
  241. LOG_DEBUG("watchpoint from EICE unit 0");
  242. target->debug_reason = DBG_REASON_WATCHPOINT;
  243. break;
  244. case 7:
  245. LOG_DEBUG("watchpoint from EICE unit 1");
  246. target->debug_reason = DBG_REASON_WATCHPOINT;
  247. break;
  248. case 8:
  249. LOG_DEBUG("external watchpoint");
  250. target->debug_reason = DBG_REASON_WATCHPOINT;
  251. break;
  252. case 9:
  253. LOG_DEBUG("internal debug request");
  254. target->debug_reason = DBG_REASON_DBGRQ;
  255. break;
  256. case 10:
  257. LOG_DEBUG("external debug request");
  258. target->debug_reason = DBG_REASON_DBGRQ;
  259. break;
  260. case 11:
  261. LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
  262. break;
  263. case 12:
  264. /* FIX!!!! here be dragons!!! We need to fail here so
  265. * the target will interpreted as halted but we won't
  266. * try to talk to it right now... a resume + halt seems
  267. * to sync things up again. Please send an email to
  268. * openocd development mailing list if you have hardware
  269. * to donate to look into this problem....
  270. */
  271. LOG_ERROR("mystery debug reason MOE=0xc. Try issuing a resume + halt.");
  272. target->debug_reason = DBG_REASON_DBGRQ;
  273. retval = ERROR_TARGET_FAILURE;
  274. break;
  275. default:
  276. LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
  277. target->debug_reason = DBG_REASON_DBGRQ;
  278. /* if we fail here, we won't talk to the target and it will
  279. * be reported to be in the halted state */
  280. retval = ERROR_TARGET_FAILURE;
  281. break;
  282. }
  283. return retval;
  284. }
  285. u32 arm926ejs_get_ttb(target_t *target)
  286. {
  287. armv4_5_common_t *armv4_5 = target->arch_info;
  288. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  289. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  290. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  291. int retval;
  292. u32 ttb = 0x0;
  293. if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
  294. return retval;
  295. return ttb;
  296. }
  297. void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
  298. {
  299. armv4_5_common_t *armv4_5 = target->arch_info;
  300. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  301. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  302. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  303. u32 cp15_control;
  304. /* read cp15 control register */
  305. arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
  306. jtag_execute_queue();
  307. if (mmu)
  308. {
  309. /* invalidate TLB */
  310. arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
  311. cp15_control &= ~0x1U;
  312. }
  313. if (d_u_cache)
  314. {
  315. u32 debug_override;
  316. /* read-modify-write CP15 debug override register
  317. * to enable "test and clean all" */
  318. arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
  319. debug_override |= 0x80000;
  320. arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
  321. /* clean and invalidate DCache */
  322. arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
  323. /* write CP15 debug override register
  324. * to disable "test and clean all" */
  325. debug_override &= ~0x80000;
  326. arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
  327. cp15_control &= ~0x4U;
  328. }
  329. if (i_cache)
  330. {
  331. /* invalidate ICache */
  332. arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
  333. cp15_control &= ~0x1000U;
  334. }
  335. arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
  336. }
  337. void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
  338. {
  339. armv4_5_common_t *armv4_5 = target->arch_info;
  340. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  341. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  342. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  343. u32 cp15_control;
  344. /* read cp15 control register */
  345. arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
  346. jtag_execute_queue();
  347. if (mmu)
  348. cp15_control |= 0x1U;
  349. if (d_u_cache)
  350. cp15_control |= 0x4U;
  351. if (i_cache)
  352. cp15_control |= 0x1000U;
  353. arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
  354. }
  355. void arm926ejs_post_debug_entry(target_t *target)
  356. {
  357. armv4_5_common_t *armv4_5 = target->arch_info;
  358. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  359. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  360. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  361. /* examine cp15 control reg */
  362. arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
  363. jtag_execute_queue();
  364. LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
  365. if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
  366. {
  367. u32 cache_type_reg;
  368. /* identify caches */
  369. arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
  370. jtag_execute_queue();
  371. armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
  372. }
  373. arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
  374. arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
  375. arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
  376. /* save i/d fault status and address register */
  377. arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
  378. arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
  379. arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
  380. LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
  381. arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
  382. u32 cache_dbg_ctrl;
  383. /* read-modify-write CP15 cache debug control register
  384. * to disable I/D-cache linefills and force WT */
  385. arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
  386. cache_dbg_ctrl |= 0x7;
  387. arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
  388. }
  389. void arm926ejs_pre_restore_context(target_t *target)
  390. {
  391. armv4_5_common_t *armv4_5 = target->arch_info;
  392. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  393. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  394. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  395. /* restore i/d fault status and address register */
  396. arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
  397. arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
  398. arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
  399. u32 cache_dbg_ctrl;
  400. /* read-modify-write CP15 cache debug control register
  401. * to reenable I/D-cache linefills and disable WT */
  402. arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
  403. cache_dbg_ctrl &= ~0x7;
  404. arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
  405. }
  406. int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
  407. {
  408. armv4_5_common_t *armv4_5 = target->arch_info;
  409. arm7_9_common_t *arm7_9;
  410. arm9tdmi_common_t *arm9tdmi;
  411. arm926ejs_common_t *arm926ejs;
  412. if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
  413. {
  414. return -1;
  415. }
  416. arm7_9 = armv4_5->arch_info;
  417. if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
  418. {
  419. return -1;
  420. }
  421. arm9tdmi = arm7_9->arch_info;
  422. if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
  423. {
  424. return -1;
  425. }
  426. arm926ejs = arm9tdmi->arch_info;
  427. if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
  428. {
  429. return -1;
  430. }
  431. *armv4_5_p = armv4_5;
  432. *arm7_9_p = arm7_9;
  433. *arm9tdmi_p = arm9tdmi;
  434. *arm926ejs_p = arm926ejs;
  435. return ERROR_OK;
  436. }
  437. int arm926ejs_arch_state(struct target_s *target)
  438. {
  439. armv4_5_common_t *armv4_5 = target->arch_info;
  440. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  441. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  442. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  443. char *state[] =
  444. {
  445. "disabled", "enabled"
  446. };
  447. if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
  448. {
  449. LOG_ERROR("BUG: called for a non-ARMv4/5 target");
  450. exit(-1);
  451. }
  452. LOG_USER(
  453. "target halted in %s state due to %s, current mode: %s\n"
  454. "cpsr: 0x%8.8x pc: 0x%8.8x\n"
  455. "MMU: %s, D-Cache: %s, I-Cache: %s",
  456. armv4_5_state_strings[armv4_5->core_state],
  457. Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
  458. armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
  459. buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
  460. buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
  461. state[arm926ejs->armv4_5_mmu.mmu_enabled],
  462. state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
  463. state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
  464. return ERROR_OK;
  465. }
  466. int arm926ejs_soft_reset_halt(struct target_s *target)
  467. {
  468. int retval = ERROR_OK;
  469. armv4_5_common_t *armv4_5 = target->arch_info;
  470. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  471. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  472. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  473. reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
  474. if ((retval = target_halt(target)) != ERROR_OK)
  475. {
  476. return retval;
  477. }
  478. long long then=timeval_ms();
  479. int timeout;
  480. while (!(timeout=((timeval_ms()-then)>1000)))
  481. {
  482. if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
  483. {
  484. embeddedice_read_reg(dbg_stat);
  485. if ((retval = jtag_execute_queue()) != ERROR_OK)
  486. {
  487. return retval;
  488. }
  489. } else
  490. {
  491. break;
  492. }
  493. if (debug_level>=1)
  494. {
  495. /* do not eat all CPU, time out after 1 se*/
  496. alive_sleep(100);
  497. } else
  498. {
  499. keep_alive();
  500. }
  501. }
  502. if (timeout)
  503. {
  504. LOG_ERROR("Failed to halt CPU after 1 sec");
  505. return ERROR_TARGET_TIMEOUT;
  506. }
  507. target->state = TARGET_HALTED;
  508. /* SVC, ARM state, IRQ and FIQ disabled */
  509. buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
  510. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
  511. armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
  512. /* start fetching from 0x0 */
  513. buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
  514. armv4_5->core_cache->reg_list[15].dirty = 1;
  515. armv4_5->core_cache->reg_list[15].valid = 1;
  516. armv4_5->core_mode = ARMV4_5_MODE_SVC;
  517. armv4_5->core_state = ARMV4_5_STATE_ARM;
  518. arm926ejs_disable_mmu_caches(target, 1, 1, 1);
  519. arm926ejs->armv4_5_mmu.mmu_enabled = 0;
  520. arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
  521. arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
  522. return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
  523. }
  524. int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
  525. {
  526. int retval;
  527. armv4_5_common_t *armv4_5 = target->arch_info;
  528. arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  529. arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  530. arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
  531. if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
  532. return retval;
  533. /* If ICache is enabled, we have to invalidate affected ICache lines
  534. * the DCache is forced to write-through, so we don't have to clean it here
  535. */
  536. if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
  537. {
  538. if (count <= 1)
  539. {
  540. /* invalidate ICache single entry with MVA */
  541. arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
  542. }
  543. else
  544. {
  545. /* invalidate ICache */
  546. arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
  547. }
  548. }
  549. return retval;
  550. }
  551. int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
  552. {
  553. arm9tdmi_init_target(cmd_ctx, target);
  554. return ERROR_OK;
  555. }
  556. int arm926ejs_quit(void)
  557. {
  558. return ERROR_OK;
  559. }
  560. int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap)
  561. {
  562. arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
  563. arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
  564. /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
  565. */
  566. arm9tdmi_init_arch_info(target, arm9tdmi, tap);
  567. arm9tdmi->arch_info = arm926ejs;
  568. arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
  569. arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
  570. arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
  571. arm926ejs->read_cp15 = arm926ejs_cp15_read;
  572. arm926ejs->write_cp15 = arm926ejs_cp15_write;
  573. arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
  574. arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
  575. arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
  576. arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
  577. arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
  578. arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
  579. arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
  580. arm926ejs->armv4_5_mmu.mmu_enabled = 0;
  581. arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
  582. /* The ARM926EJ-S implements the ARMv5TE architecture which
  583. * has the BKPT instruction, so we don't have to use a watchpoint comparator
  584. */
  585. arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
  586. arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
  587. return ERROR_OK;
  588. }
  589. int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
  590. {
  591. arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
  592. arm926ejs_init_arch_info(target, arm926ejs, target->tap);
  593. return ERROR_OK;
  594. }
  595. int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
  596. {
  597. int retval;
  598. command_t *arm926ejs_cmd;
  599. retval = arm9tdmi_register_commands(cmd_ctx);
  600. arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
  601. register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
  602. register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
  603. register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
  604. register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
  605. register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
  606. register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
  607. register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
  608. register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
  609. register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
  610. return retval;
  611. }
  612. int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  613. {
  614. int retval;
  615. target_t *target = get_current_target(cmd_ctx);
  616. armv4_5_common_t *armv4_5;
  617. arm7_9_common_t *arm7_9;
  618. arm9tdmi_common_t *arm9tdmi;
  619. arm926ejs_common_t *arm926ejs;
  620. int opcode_1;
  621. int opcode_2;
  622. int CRn;
  623. int CRm;
  624. if ((argc < 4) || (argc > 5))
  625. {
  626. command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
  627. return ERROR_OK;
  628. }
  629. opcode_1 = strtoul(args[0], NULL, 0);
  630. opcode_2 = strtoul(args[1], NULL, 0);
  631. CRn = strtoul(args[2], NULL, 0);
  632. CRm = strtoul(args[3], NULL, 0);
  633. if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
  634. {
  635. command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
  636. return ERROR_OK;
  637. }
  638. if (target->state != TARGET_HALTED)
  639. {
  640. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  641. return ERROR_OK;
  642. }
  643. if (argc == 4)
  644. {
  645. u32 value;
  646. if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
  647. {
  648. command_print(cmd_ctx, "couldn't access register");
  649. return ERROR_OK;
  650. }
  651. if ((retval = jtag_execute_queue()) != ERROR_OK)
  652. {
  653. return retval;
  654. }
  655. command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
  656. }
  657. else
  658. {
  659. u32 value = strtoul(args[4], NULL, 0);
  660. if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
  661. {
  662. command_print(cmd_ctx, "couldn't access register");
  663. return ERROR_OK;
  664. }
  665. command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
  666. }
  667. return ERROR_OK;
  668. }
  669. int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
  670. {
  671. target_t *target = get_current_target(cmd_ctx);
  672. armv4_5_common_t *armv4_5;
  673. arm7_9_common_t *arm7_9;
  674. arm9tdmi_common_t *arm9tdmi;
  675. arm926ejs_common_t *arm926ejs;
  676. if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
  677. {
  678. command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
  679. return ERROR_OK;
  680. }
  681. return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
  682. }
  683. int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
  684. {
  685. target_t *target = get_current_target(cmd_ctx);
  686. armv4_5_common_t *armv4_5;
  687. arm7_9_common_t *arm7_9;
  688. arm9tdmi_common_t *arm9tdmi;
  689. arm926ejs_common_t *arm926ejs;
  690. arm_jtag_t *jtag_info;
  691. if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
  692. {
  693. command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
  694. return ERROR_OK;
  695. }
  696. jtag_info = &arm7_9->jtag_info;
  697. if (target->state != TARGET_HALTED)
  698. {
  699. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  700. return ERROR_OK;
  701. }
  702. return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
  703. }
  704. int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
  705. {
  706. target_t *target = get_current_target(cmd_ctx);
  707. armv4_5_common_t *armv4_5;
  708. arm7_9_common_t *arm7_9;
  709. arm9tdmi_common_t *arm9tdmi;
  710. arm926ejs_common_t *arm926ejs;
  711. arm_jtag_t *jtag_info;
  712. if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
  713. {
  714. command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
  715. return ERROR_OK;
  716. }
  717. jtag_info = &arm7_9->jtag_info;
  718. if (target->state != TARGET_HALTED)
  719. {
  720. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  721. return ERROR_OK;
  722. }
  723. return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
  724. }
  725. int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
  726. {
  727. target_t *target = get_current_target(cmd_ctx);
  728. armv4_5_common_t *armv4_5;
  729. arm7_9_common_t *arm7_9;
  730. arm9tdmi_common_t *arm9tdmi;
  731. arm926ejs_common_t *arm926ejs;
  732. arm_jtag_t *jtag_info;
  733. if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
  734. {
  735. command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
  736. return ERROR_OK;
  737. }
  738. jtag_info = &arm7_9->jtag_info;
  739. if (target->state != TARGET_HALTED)
  740. {
  741. command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
  742. return ERROR_OK;
  743. }
  744. return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
  745. }
  746. static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
  747. {
  748. int retval;
  749. int type;
  750. u32 cb;
  751. int domain;
  752. u32 ap;
  753. armv4_5_common_t *armv4_5;
  754. arm7_9_common_t *arm7_9;
  755. arm9tdmi_common_t *arm9tdmi;
  756. arm926ejs_common_t *arm926ejs;
  757. retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
  758. if (retval != ERROR_OK)
  759. {
  760. return retval;
  761. }
  762. u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
  763. if (type == -1)
  764. {
  765. return ret;
  766. }
  767. *physical = ret;
  768. return ERROR_OK;
  769. }
  770. static int arm926ejs_mmu(struct target_s *target, int *enabled)
  771. {
  772. armv4_5_common_t *armv4_5 = target->arch_info;
  773. arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
  774. if (target->state != TARGET_HALTED)
  775. {
  776. LOG_ERROR("Target not halted");
  777. return ERROR_TARGET_INVALID;
  778. }
  779. *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
  780. return ERROR_OK;
  781. }