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  1. /***************************************************************************
  2. * Copyright (C) 2006 by Magnus Lundin *
  3. * lundin@mlu.mine.nu *
  4. * *
  5. * Copyright (C) 2008 by Spencer Oliver *
  6. * spen@spen-soft.co.uk *
  7. * *
  8. * Copyright (C) 2009 by Oyvind Harboe *
  9. * oyvind.harboe@zylin.com *
  10. * *
  11. * This program is free software; you can redistribute it and/or modify *
  12. * it under the terms of the GNU General Public License as published by *
  13. * the Free Software Foundation; either version 2 of the License, or *
  14. * (at your option) any later version. *
  15. * *
  16. * This program is distributed in the hope that it will be useful, *
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  19. * GNU General Public License for more details. *
  20. * *
  21. * You should have received a copy of the GNU General Public License *
  22. * along with this program; if not, write to the *
  23. * Free Software Foundation, Inc., *
  24. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  25. ***************************************************************************/
  26. /***************************************************************************
  27. * *
  28. * This file implements support for the ARM Debug Interface v5 (ADI_V5) *
  29. * *
  30. * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A *
  31. * *
  32. * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A *
  33. * Cortex-M3(tm) TRM, ARM DDI 0337C *
  34. * *
  35. ***************************************************************************/
  36. #ifdef HAVE_CONFIG_H
  37. #include "config.h"
  38. #endif
  39. #include "arm_adi_v5.h"
  40. #include "time_support.h"
  41. /*
  42. * Transaction Mode:
  43. * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  44. * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
  45. * result checking until swjdp_end_transaction()
  46. * This must be done before using or deallocating any return variables.
  47. * swjdp->trans_mode == TRANS_MODE_ATOMIC
  48. * All reads and writes to the AHB bus are checked for valid completion, and return values
  49. * are immediatley available.
  50. */
  51. /***************************************************************************
  52. * *
  53. * DPACC and APACC scanchain access through JTAG-DP *
  54. * *
  55. ***************************************************************************/
  56. /* Scan out and in from target ordered u8 buffers */
  57. int adi_jtag_dp_scan(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack)
  58. {
  59. arm_jtag_t *jtag_info = swjdp->jtag_info;
  60. scan_field_t fields[2];
  61. u8 out_addr_buf;
  62. jtag_add_end_state(TAP_IDLE);
  63. arm_jtag_set_instr(jtag_info, instr, NULL);
  64. /* Add specified number of tck clocks before accessing memory bus */
  65. if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0) )&& (swjdp->memaccess_tck != 0))
  66. jtag_add_runtest(swjdp->memaccess_tck, jtag_add_end_state(TAP_IDLE));
  67. fields[0].tap = jtag_info->tap;
  68. fields[0].num_bits = 3;
  69. buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
  70. fields[0].out_value = &out_addr_buf;
  71. fields[0].in_value = ack;
  72. fields[1].tap = jtag_info->tap;
  73. fields[1].num_bits = 32;
  74. fields[1].out_value = outvalue;
  75. fields[1].in_value = invalue;
  76. jtag_add_dr_scan(2, fields, jtag_get_end_state());
  77. return ERROR_OK;
  78. }
  79. /* Scan out and in from host ordered u32 variables */
  80. int adi_jtag_dp_scan_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack)
  81. {
  82. arm_jtag_t *jtag_info = swjdp->jtag_info;
  83. scan_field_t fields[2];
  84. u8 out_value_buf[4];
  85. u8 out_addr_buf;
  86. jtag_add_end_state(TAP_IDLE);
  87. arm_jtag_set_instr(jtag_info, instr, NULL);
  88. /* Add specified number of tck clocks before accessing memory bus */
  89. if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0) )&& (swjdp->memaccess_tck != 0))
  90. jtag_add_runtest(swjdp->memaccess_tck, jtag_add_end_state(TAP_IDLE));
  91. fields[0].tap = jtag_info->tap;
  92. fields[0].num_bits = 3;
  93. buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
  94. fields[0].out_value = &out_addr_buf;
  95. fields[0].in_value = ack;
  96. fields[1].tap = jtag_info->tap;
  97. fields[1].num_bits = 32;
  98. buf_set_u32(out_value_buf, 0, 32, outvalue);
  99. fields[1].out_value = out_value_buf;
  100. fields[1].in_value = NULL;
  101. if (invalue)
  102. {
  103. fields[1].in_value = (u8 *)invalue;
  104. jtag_add_dr_scan(2, fields, jtag_get_end_state());
  105. jtag_add_callback(arm_le_to_h_u32, (u8 *)invalue);
  106. } else
  107. {
  108. jtag_add_dr_scan(2, fields, jtag_get_end_state());
  109. }
  110. return ERROR_OK;
  111. }
  112. /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
  113. int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue)
  114. {
  115. adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
  116. if ((RnW == DPAP_READ) && (invalue != NULL))
  117. {
  118. adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
  119. }
  120. /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
  121. if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
  122. {
  123. return swjdp_transaction_endcheck(swjdp);
  124. }
  125. return ERROR_OK;
  126. }
  127. int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue)
  128. {
  129. adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
  130. if ((RnW==DPAP_READ) && (invalue != NULL))
  131. {
  132. adi_jtag_dp_scan_u32(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
  133. }
  134. /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
  135. if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
  136. {
  137. return swjdp_transaction_endcheck(swjdp);
  138. }
  139. return ERROR_OK;
  140. }
  141. int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
  142. {
  143. int retval;
  144. u32 ctrlstat;
  145. /* too expensive to call keep_alive() here */
  146. #if 0
  147. /* Danger!!!! BROKEN!!!! */
  148. scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
  149. /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
  150. R956 introduced the check on return value here and now Michael Schwingen reports
  151. that this code no longer works....
  152. https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
  153. */
  154. if ((retval=jtag_execute_queue())!=ERROR_OK)
  155. {
  156. LOG_ERROR("BUG: Why does this fail the first time????");
  157. }
  158. /* Why??? second time it works??? */
  159. #endif
  160. scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
  161. if ((retval=jtag_execute_queue())!=ERROR_OK)
  162. return retval;
  163. swjdp->ack = swjdp->ack & 0x7;
  164. if (swjdp->ack != 2)
  165. {
  166. long long then=timeval_ms();
  167. while (swjdp->ack != 2)
  168. {
  169. if (swjdp->ack == 1)
  170. {
  171. if ((timeval_ms()-then) > 1000)
  172. {
  173. LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction");
  174. return ERROR_JTAG_DEVICE_ERROR;
  175. }
  176. }
  177. else
  178. {
  179. LOG_WARNING("Invalid ACK in SWJDP transaction");
  180. return ERROR_JTAG_DEVICE_ERROR;
  181. }
  182. scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
  183. if ((retval=jtag_execute_queue())!=ERROR_OK)
  184. return retval;
  185. swjdp->ack = swjdp->ack & 0x7;
  186. }
  187. } else
  188. {
  189. /* common code path avoids fn to timeval_ms() */
  190. }
  191. /* Check for STICKYERR and STICKYORUN */
  192. if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
  193. {
  194. LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat);
  195. /* Check power to debug regions */
  196. if ((ctrlstat & 0xf0000000) != 0xf0000000)
  197. {
  198. ahbap_debugport_init(swjdp);
  199. }
  200. else
  201. {
  202. u32 mem_ap_csw, mem_ap_tar;
  203. /* Print information about last AHBAP access */
  204. LOG_ERROR("AHBAP Cached values: dp_select 0x%x, ap_csw 0x%x, ap_tar 0x%x", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
  205. if (ctrlstat & SSTICKYORUN)
  206. LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
  207. if (ctrlstat & SSTICKYERR)
  208. LOG_ERROR("SWJ-DP STICKY ERROR");
  209. /* Clear Sticky Error Bits */
  210. scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
  211. scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
  212. if ((retval=jtag_execute_queue())!=ERROR_OK)
  213. return retval;
  214. LOG_DEBUG("swjdp: status 0x%x", ctrlstat);
  215. dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
  216. dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
  217. if ((retval=jtag_execute_queue())!=ERROR_OK)
  218. return retval;
  219. LOG_ERROR("Read MEM_AP_CSW 0x%x, MEM_AP_TAR 0x%x", mem_ap_csw, mem_ap_tar);
  220. }
  221. if ((retval=jtag_execute_queue())!=ERROR_OK)
  222. return retval;
  223. return ERROR_JTAG_DEVICE_ERROR;
  224. }
  225. return ERROR_OK;
  226. }
  227. /***************************************************************************
  228. * *
  229. * DP and MEM-AP register access through APACC and DPACC *
  230. * *
  231. ***************************************************************************/
  232. int dap_dp_write_reg(swjdp_common_t *swjdp, u32 value, u8 reg_addr)
  233. {
  234. return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
  235. }
  236. int dap_dp_read_reg(swjdp_common_t *swjdp, u32 *value, u8 reg_addr)
  237. {
  238. return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
  239. }
  240. int dap_ap_select(swjdp_common_t *swjdp,u8 apsel)
  241. {
  242. u32 select;
  243. select = (apsel<<24) & 0xFF000000;
  244. if (select != swjdp->apsel)
  245. {
  246. swjdp->apsel = select;
  247. /* Switching AP invalidates cached values */
  248. swjdp->dp_select_value = -1;
  249. swjdp->ap_csw_value = -1;
  250. swjdp->ap_tar_value = -1;
  251. }
  252. return ERROR_OK;
  253. }
  254. int dap_dp_bankselect(swjdp_common_t *swjdp,u32 ap_reg)
  255. {
  256. u32 select;
  257. select = (ap_reg & 0x000000F0);
  258. if (select != swjdp->dp_select_value)
  259. {
  260. dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
  261. swjdp->dp_select_value = select;
  262. }
  263. return ERROR_OK;
  264. }
  265. int dap_ap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf)
  266. {
  267. dap_dp_bankselect(swjdp, reg_addr);
  268. scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
  269. return ERROR_OK;
  270. }
  271. int dap_ap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf)
  272. {
  273. dap_dp_bankselect(swjdp, reg_addr);
  274. scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
  275. return ERROR_OK;
  276. }
  277. int dap_ap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
  278. {
  279. u8 out_value_buf[4];
  280. buf_set_u32(out_value_buf, 0, 32, value);
  281. dap_dp_bankselect(swjdp, reg_addr);
  282. scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
  283. return ERROR_OK;
  284. }
  285. int dap_ap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value)
  286. {
  287. dap_dp_bankselect(swjdp, reg_addr);
  288. scan_inout_check_u32(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, value);
  289. return ERROR_OK;
  290. }
  291. /***************************************************************************
  292. * *
  293. * AHB-AP access to memory and system registers on AHB bus *
  294. * *
  295. ***************************************************************************/
  296. int dap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
  297. {
  298. csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
  299. if (csw != swjdp->ap_csw_value)
  300. {
  301. /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
  302. dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw );
  303. swjdp->ap_csw_value = csw;
  304. }
  305. if (tar != swjdp->ap_tar_value)
  306. {
  307. /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
  308. dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar );
  309. swjdp->ap_tar_value = tar;
  310. }
  311. if (csw & CSW_ADDRINC_MASK)
  312. {
  313. /* Do not cache TAR value when autoincrementing */
  314. swjdp->ap_tar_value = -1;
  315. }
  316. return ERROR_OK;
  317. }
  318. /*****************************************************************************
  319. * *
  320. * mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value) *
  321. * *
  322. * Read a u32 value from memory or system register *
  323. * Functionally equivalent to target_read_u32(target, address, u32 *value), *
  324. * but with less overhead *
  325. *****************************************************************************/
  326. int mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
  327. {
  328. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  329. dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
  330. dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value );
  331. return ERROR_OK;
  332. }
  333. int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
  334. {
  335. mem_ap_read_u32(swjdp, address, value);
  336. return swjdp_transaction_endcheck(swjdp);
  337. }
  338. /*****************************************************************************
  339. * *
  340. * mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value) *
  341. * *
  342. * Write a u32 value to memory or memory mapped register *
  343. * *
  344. *****************************************************************************/
  345. int mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value)
  346. {
  347. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  348. dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
  349. dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value );
  350. return ERROR_OK;
  351. }
  352. int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
  353. {
  354. mem_ap_write_u32(swjdp, address, value);
  355. return swjdp_transaction_endcheck(swjdp);
  356. }
  357. /*****************************************************************************
  358. * *
  359. * mem_ap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
  360. * *
  361. * Write a buffer in target order (little endian) *
  362. * *
  363. *****************************************************************************/
  364. int mem_ap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
  365. {
  366. int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
  367. u32 adr = address;
  368. u8* pBuffer = buffer;
  369. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  370. count >>= 2;
  371. wcount = count;
  372. /* if we have an unaligned access - reorder data */
  373. if (adr & 0x3u)
  374. {
  375. for (writecount = 0; writecount < count; writecount++)
  376. {
  377. int i;
  378. u32 outvalue;
  379. memcpy(&outvalue, pBuffer, sizeof(u32));
  380. for (i = 0; i < 4; i++ )
  381. {
  382. *((u8*)pBuffer + (adr & 0x3)) = outvalue;
  383. outvalue >>= 8;
  384. adr++;
  385. }
  386. pBuffer += sizeof(u32);
  387. }
  388. }
  389. while (wcount > 0)
  390. {
  391. /* Adjust to write blocks within 4K aligned boundaries */
  392. blocksize = (0x1000 - (0xFFF & address)) >> 2;
  393. if (wcount < blocksize)
  394. blocksize = wcount;
  395. /* handle unaligned data at 4k boundary */
  396. if (blocksize == 0)
  397. blocksize = 1;
  398. dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
  399. for (writecount = 0; writecount < blocksize; writecount++)
  400. {
  401. dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount );
  402. }
  403. if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
  404. {
  405. wcount = wcount - blocksize;
  406. address = address + 4 * blocksize;
  407. buffer = buffer + 4 * blocksize;
  408. }
  409. else
  410. {
  411. errorcount++;
  412. }
  413. if (errorcount > 1)
  414. {
  415. LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
  416. return ERROR_JTAG_DEVICE_ERROR;
  417. }
  418. }
  419. return retval;
  420. }
  421. int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
  422. {
  423. int retval = ERROR_OK;
  424. int wcount, blocksize, writecount, i;
  425. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  426. wcount = count >> 1;
  427. while (wcount > 0)
  428. {
  429. int nbytes;
  430. /* Adjust to read within 4K block boundaries */
  431. blocksize = (0x1000 - (0xFFF & address)) >> 1;
  432. if (wcount < blocksize)
  433. blocksize = wcount;
  434. /* handle unaligned data at 4k boundary */
  435. if (blocksize == 0)
  436. blocksize = 1;
  437. dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
  438. writecount = blocksize;
  439. do
  440. {
  441. nbytes = MIN((writecount << 1), 4);
  442. if (nbytes < 4 )
  443. {
  444. if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
  445. {
  446. LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
  447. return ERROR_JTAG_DEVICE_ERROR;
  448. }
  449. address += nbytes >> 1;
  450. }
  451. else
  452. {
  453. u32 outvalue;
  454. memcpy(&outvalue, buffer, sizeof(u32));
  455. for (i = 0; i < nbytes; i++ )
  456. {
  457. *((u8*)buffer + (address & 0x3)) = outvalue;
  458. outvalue >>= 8;
  459. address++;
  460. }
  461. memcpy(&outvalue, buffer, sizeof(u32));
  462. dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
  463. if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
  464. {
  465. LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
  466. return ERROR_JTAG_DEVICE_ERROR;
  467. }
  468. }
  469. buffer += nbytes >> 1;
  470. writecount -= nbytes >> 1;
  471. } while (writecount);
  472. wcount -= blocksize;
  473. }
  474. return retval;
  475. }
  476. int mem_ap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
  477. {
  478. int retval = ERROR_OK;
  479. if (count >= 4)
  480. return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
  481. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  482. while (count > 0)
  483. {
  484. dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
  485. u16 svalue;
  486. memcpy(&svalue, buffer, sizeof(u16));
  487. u32 outvalue = (u32)svalue << 8 * (address & 0x3);
  488. dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
  489. retval = swjdp_transaction_endcheck(swjdp);
  490. count -= 2;
  491. address += 2;
  492. buffer += 2;
  493. }
  494. return retval;
  495. }
  496. int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
  497. {
  498. int retval = ERROR_OK;
  499. int wcount, blocksize, writecount, i;
  500. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  501. wcount = count;
  502. while (wcount > 0)
  503. {
  504. int nbytes;
  505. /* Adjust to read within 4K block boundaries */
  506. blocksize = (0x1000 - (0xFFF & address));
  507. if (wcount < blocksize)
  508. blocksize = wcount;
  509. dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
  510. writecount = blocksize;
  511. do
  512. {
  513. nbytes = MIN(writecount, 4);
  514. if (nbytes < 4 )
  515. {
  516. if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
  517. {
  518. LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
  519. return ERROR_JTAG_DEVICE_ERROR;
  520. }
  521. address += nbytes;
  522. }
  523. else
  524. {
  525. u32 outvalue;
  526. memcpy(&outvalue, buffer, sizeof(u32));
  527. for (i = 0; i < nbytes; i++ )
  528. {
  529. *((u8*)buffer + (address & 0x3)) = outvalue;
  530. outvalue >>= 8;
  531. address++;
  532. }
  533. memcpy(&outvalue, buffer, sizeof(u32));
  534. dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
  535. if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
  536. {
  537. LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
  538. return ERROR_JTAG_DEVICE_ERROR;
  539. }
  540. }
  541. buffer += nbytes;
  542. writecount -= nbytes;
  543. } while (writecount);
  544. wcount -= blocksize;
  545. }
  546. return retval;
  547. }
  548. int mem_ap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
  549. {
  550. int retval = ERROR_OK;
  551. if (count >= 4)
  552. return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
  553. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  554. while (count > 0)
  555. {
  556. dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
  557. u32 outvalue = (u32)*buffer << 8 * (address & 0x3);
  558. dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
  559. retval = swjdp_transaction_endcheck(swjdp);
  560. count--;
  561. address++;
  562. buffer++;
  563. }
  564. return retval;
  565. }
  566. /*********************************************************************************
  567. * *
  568. * mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
  569. * *
  570. * Read block fast in target order (little endian) into a buffer *
  571. * *
  572. **********************************************************************************/
  573. int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
  574. {
  575. int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
  576. u32 adr = address;
  577. u8* pBuffer = buffer;
  578. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  579. count >>= 2;
  580. wcount = count;
  581. while (wcount > 0)
  582. {
  583. /* Adjust to read within 4K block boundaries */
  584. blocksize = (0x1000 - (0xFFF & address)) >> 2;
  585. if (wcount < blocksize)
  586. blocksize = wcount;
  587. /* handle unaligned data at 4k boundary */
  588. if (blocksize == 0)
  589. blocksize = 1;
  590. dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
  591. /* Scan out first read */
  592. adi_jtag_dp_scan(swjdp, DAP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, NULL, NULL);
  593. for (readcount = 0; readcount < blocksize - 1; readcount++)
  594. {
  595. /* Scan out read instruction and scan in previous value */
  596. adi_jtag_dp_scan(swjdp, DAP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
  597. }
  598. /* Scan in last value */
  599. adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
  600. if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
  601. {
  602. wcount = wcount - blocksize;
  603. address += 4 * blocksize;
  604. buffer += 4 * blocksize;
  605. }
  606. else
  607. {
  608. errorcount++;
  609. }
  610. if (errorcount > 1)
  611. {
  612. LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
  613. return ERROR_JTAG_DEVICE_ERROR;
  614. }
  615. }
  616. /* if we have an unaligned access - reorder data */
  617. if (adr & 0x3u)
  618. {
  619. for (readcount = 0; readcount < count; readcount++)
  620. {
  621. int i;
  622. u32 data;
  623. memcpy(&data, pBuffer, sizeof(u32));
  624. for (i = 0; i < 4; i++ )
  625. {
  626. *((u8*)pBuffer) = (data >> 8 * (adr & 0x3));
  627. pBuffer++;
  628. adr++;
  629. }
  630. }
  631. }
  632. return retval;
  633. }
  634. int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
  635. {
  636. u32 invalue;
  637. int retval = ERROR_OK;
  638. int wcount, blocksize, readcount, i;
  639. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  640. wcount = count >> 1;
  641. while (wcount > 0)
  642. {
  643. int nbytes;
  644. /* Adjust to read within 4K block boundaries */
  645. blocksize = (0x1000 - (0xFFF & address)) >> 1;
  646. if (wcount < blocksize)
  647. blocksize = wcount;
  648. dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
  649. /* handle unaligned data at 4k boundary */
  650. if (blocksize == 0)
  651. blocksize = 1;
  652. readcount = blocksize;
  653. do
  654. {
  655. dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
  656. if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
  657. {
  658. LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
  659. return ERROR_JTAG_DEVICE_ERROR;
  660. }
  661. nbytes = MIN((readcount << 1), 4);
  662. for (i = 0; i < nbytes; i++ )
  663. {
  664. *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
  665. buffer++;
  666. address++;
  667. }
  668. readcount -= (nbytes >> 1);
  669. } while (readcount);
  670. wcount -= blocksize;
  671. }
  672. return retval;
  673. }
  674. int mem_ap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
  675. {
  676. u32 invalue, i;
  677. int retval = ERROR_OK;
  678. if (count >= 4)
  679. return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
  680. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  681. while (count > 0)
  682. {
  683. dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
  684. dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
  685. retval = swjdp_transaction_endcheck(swjdp);
  686. if (address & 0x1)
  687. {
  688. for (i = 0; i < 2; i++ )
  689. {
  690. *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
  691. buffer++;
  692. address++;
  693. }
  694. }
  695. else
  696. {
  697. u16 svalue = (invalue >> 8 * (address & 0x3));
  698. memcpy(buffer, &svalue, sizeof(u16));
  699. address += 2;
  700. buffer += 2;
  701. }
  702. count -= 2;
  703. }
  704. return retval;
  705. }
  706. /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
  707. * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
  708. *
  709. * The solution is to arrange for a large out/in scan in this loop and
  710. * and convert data afterwards.
  711. */
  712. int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
  713. {
  714. u32 invalue;
  715. int retval = ERROR_OK;
  716. int wcount, blocksize, readcount, i;
  717. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  718. wcount = count;
  719. while (wcount > 0)
  720. {
  721. int nbytes;
  722. /* Adjust to read within 4K block boundaries */
  723. blocksize = (0x1000 - (0xFFF & address));
  724. if (wcount < blocksize)
  725. blocksize = wcount;
  726. dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
  727. readcount = blocksize;
  728. do
  729. {
  730. dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
  731. if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
  732. {
  733. LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
  734. return ERROR_JTAG_DEVICE_ERROR;
  735. }
  736. nbytes = MIN(readcount, 4);
  737. for (i = 0; i < nbytes; i++ )
  738. {
  739. *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
  740. buffer++;
  741. address++;
  742. }
  743. readcount -= nbytes;
  744. } while (readcount);
  745. wcount -= blocksize;
  746. }
  747. return retval;
  748. }
  749. int mem_ap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
  750. {
  751. u32 invalue;
  752. int retval = ERROR_OK;
  753. if (count >= 4)
  754. return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
  755. swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  756. while (count > 0)
  757. {
  758. dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
  759. dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
  760. retval = swjdp_transaction_endcheck(swjdp);
  761. *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
  762. count--;
  763. address++;
  764. buffer++;
  765. }
  766. return retval;
  767. }
  768. int ahbap_debugport_init(swjdp_common_t *swjdp)
  769. {
  770. u32 idreg, romaddr, dummy;
  771. u32 ctrlstat;
  772. int cnt = 0;
  773. int retval;
  774. LOG_DEBUG(" ");
  775. swjdp->apsel = 0;
  776. swjdp->ap_csw_value = -1;
  777. swjdp->ap_tar_value = -1;
  778. swjdp->trans_mode = TRANS_MODE_ATOMIC;
  779. dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
  780. dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
  781. dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
  782. swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
  783. dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
  784. dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
  785. if ((retval=jtag_execute_queue())!=ERROR_OK)
  786. return retval;
  787. /* Check that we have debug power domains activated */
  788. while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
  789. {
  790. LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
  791. dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
  792. if ((retval=jtag_execute_queue())!=ERROR_OK)
  793. return retval;
  794. alive_sleep(10);
  795. }
  796. while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
  797. {
  798. LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
  799. dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
  800. if ((retval=jtag_execute_queue())!=ERROR_OK)
  801. return retval;
  802. alive_sleep(10);
  803. }
  804. dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
  805. /* With debug power on we can activate OVERRUN checking */
  806. swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
  807. dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
  808. dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
  809. dap_ap_read_reg_u32(swjdp, 0xFC, &idreg);
  810. dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr);
  811. LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);
  812. return ERROR_OK;
  813. }
  814. char * class_description[16] ={
  815. "Reserved",
  816. "ROM table","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved",
  817. "CoreSight component","Reserved","Peripheral Test Block","Reserved","DESS","Generic IP component","Non standard layout"};
  818. int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, int apsel)
  819. {
  820. u32 dbgbase,apid;
  821. int romtable_present = 0;
  822. u8 mem_ap;
  823. u32 apselold;
  824. apselold = swjdp->apsel;
  825. dap_ap_select(swjdp, apsel);
  826. dap_ap_read_reg_u32(swjdp, 0xF8, &dbgbase);
  827. dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
  828. swjdp_transaction_endcheck(swjdp);
  829. /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
  830. mem_ap = ((apid&0x10000)&&((apid&0x0F)!=0));
  831. command_print(cmd_ctx, "ap identification register 0x%8.8x", apid);
  832. if (apid)
  833. {
  834. switch (apid&0x0F)
  835. {
  836. case 0:
  837. command_print(cmd_ctx, "\tType is jtag-ap");
  838. break;
  839. case 1:
  840. command_print(cmd_ctx, "\tType is mem-ap AHB");
  841. break;
  842. case 2:
  843. command_print(cmd_ctx, "\tType is mem-ap APB");
  844. break;
  845. default:
  846. command_print(cmd_ctx, "\tUnknown AP-type");
  847. break;
  848. }
  849. command_print(cmd_ctx, "ap debugbase 0x%8.8x", dbgbase);
  850. }
  851. else
  852. {
  853. command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
  854. }
  855. romtable_present = ((mem_ap)&&(dbgbase != 0xFFFFFFFF));
  856. if (romtable_present)
  857. {
  858. u32 cid0,cid1,cid2,cid3,memtype,romentry;
  859. u16 entry_offset;
  860. /* bit 16 of apid indicates a memory access port */
  861. if (dbgbase&0x02)
  862. {
  863. command_print(cmd_ctx, "\tValid ROM table present");
  864. }
  865. else
  866. {
  867. command_print(cmd_ctx, "\tROM table in legacy format" );
  868. }
  869. /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
  870. mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF0, &cid0);
  871. mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF4, &cid1);
  872. mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF8, &cid2);
  873. mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFFC, &cid3);
  874. mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFCC, &memtype);
  875. swjdp_transaction_endcheck(swjdp);
  876. command_print(cmd_ctx, "\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",cid3,cid2,cid1,cid0);
  877. if (memtype&0x01)
  878. {
  879. command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
  880. }
  881. else
  882. {
  883. command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus" );
  884. }
  885. /* Now we read ROM table entries from dbgbase&0xFFFFF000)|0x000 until we get 0x00000000 */
  886. entry_offset = 0;
  887. do
  888. {
  889. mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000)|entry_offset, &romentry);
  890. command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%x",entry_offset,romentry);
  891. if (romentry&0x01)
  892. {
  893. u32 c_cid0,c_cid1,c_cid2,c_cid3,c_pid0,c_pid1,c_pid2,c_pid3,c_pid4,component_start;
  894. u32 component_base = (u32)((dbgbase&0xFFFFF000)+(int)(romentry&0xFFFFF000));
  895. mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE0, &c_pid0);
  896. mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE4, &c_pid1);
  897. mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE8, &c_pid2);
  898. mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFEC, &c_pid3);
  899. mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFD0, &c_pid4);
  900. mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF0, &c_cid0);
  901. mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF4, &c_cid1);
  902. mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF8, &c_cid2);
  903. mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFFC, &c_cid3);
  904. component_start = component_base - 0x1000*(c_pid4>>4);
  905. command_print(cmd_ctx, "\t\tComponent base address 0x%x, pid4 0x%x, start address 0x%x",component_base,c_pid4,component_start);
  906. command_print(cmd_ctx, "\t\tComponent cid1 0x%x, class is %s",c_cid1,class_description[(c_cid1>>4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */
  907. command_print(cmd_ctx, "\t\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",c_cid3,c_cid2,c_cid1,c_cid0);
  908. command_print(cmd_ctx, "\t\tPID3 0x%x, PID2 0x%x, PID1 0x%x, PID0, 0x%x",c_pid3,c_pid2,c_pid1,c_pid0);
  909. /* For CoreSight components, (c_cid1>>4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */
  910. }
  911. else
  912. {
  913. if (romentry)
  914. command_print(cmd_ctx, "\t\tComponent not present");
  915. else
  916. command_print(cmd_ctx, "\t\tEnd of ROM table");
  917. }
  918. entry_offset += 4;
  919. } while (romentry>0);
  920. }
  921. else
  922. {
  923. command_print(cmd_ctx, "\tNo ROM table present");
  924. }
  925. dap_ap_select(swjdp, apselold);
  926. return ERROR_OK;
  927. }