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82 lines
3.2 KiB

  1. ################################################################################
  2. # Atmel AT91SAM9260-EK eval board
  3. #
  4. # http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
  5. #
  6. # Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
  7. # OSCSEL configured for external 32.768 kHz crystal
  8. #
  9. # 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
  10. #
  11. ################################################################################
  12. # We add to the minimal configuration.
  13. source [find target/at91sam9260.cfg]
  14. # By default S1 is open and this means that NTRST is not connected.
  15. # The reset_config in target/at91sam9260.cfg is overridden here.
  16. # (or S1 must be populated with a 0 Ohm resistor)
  17. reset_config srst_only
  18. $_TARGETNAME configure -event reset-start {
  19. # At reset CPU runs at 32.768 kHz.
  20. # JTAG Frequency must be 6 times slower if RCLK is not supported.
  21. jtag_rclk 5
  22. halt
  23. # RSTC_MR : enable user reset, MMU may be enabled... use physical address
  24. arm926ejs mww phys 0xfffffd08 0xa5000501
  25. }
  26. $_TARGETNAME configure -event reset-init {
  27. mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
  28. mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
  29. sleep 20 # wait 20 ms
  30. mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
  31. sleep 10 # wait 10 ms
  32. mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198.656 MHz
  33. sleep 20 # wait 20 ms
  34. mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler (divide by 2)
  35. sleep 10 # wait 10 ms
  36. mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
  37. sleep 10 # wait 10 ms
  38. # Increase JTAG Speed to 6 MHz if RCLK is not supported
  39. jtag_rclk 6000
  40. arm7_9 dcc_downloads enable # Enable faster DCC downloads
  41. mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
  42. mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
  43. mww 0xffffef1c 0x00010002 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
  44. mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
  45. mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
  46. mww 0x20000000 0
  47. mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
  48. mww 0x20000000 0
  49. mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
  50. mww 0x20000000 0
  51. mww 0xffffea00 0x4
  52. mww 0x20000000 0
  53. mww 0xffffea00 0x4
  54. mww 0x20000000 0
  55. mww 0xffffea00 0x4
  56. mww 0x20000000 0
  57. mww 0xffffea00 0x4
  58. mww 0x20000000 0
  59. mww 0xffffea00 0x4
  60. mww 0x20000000 0
  61. mww 0xffffea00 0x4
  62. mww 0x20000000 0
  63. mww 0xffffea00 0x4
  64. mww 0x20000000 0
  65. mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
  66. mww 0x20000000 0
  67. mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
  68. mww 0x20000000 0
  69. mww 0xffffea04 0x2b6 # SDRAMC_TR : Set refresh timer count to 7us
  70. }