Given out scaling and that n=100 on the secondary for the A6302 probe,
and a 16-bit DAC value, each LSB cancels out 300 µA of current on
the primary, for a maximum range of
  DAC 0000h ≈ -9.83 A (-300 µA * 2^15)
  DAC 8000h ≈   0.0 A
  DAC ffffh ≈  9.83 A (300 µA * 2^15)

Let's use 14 bits from the DAC.  The range covered by a single bit is
 (9.83 A * 2) / 2^14 = 1.2mA

For 5 more bits from the probe, we need to measure 1.2 mA / 2^5 = 37.5 μA.
The probe scaling is 1mA = 10mV.
So 37.5 μA is 375 μV.

The PIC can measure 12 bits over 2.5V which is 0.61mV, so we need
to scale the probe output.  Scale by (4.32) so that
  1mA at probe = 43.2mV at PIC
  37.5μA at probe = 1.62mV at PIC

(PIC input) = clamp(0, 1.25V - (probe current * 10 * 4.32), 2.5V)

Clamp by putting a 1K in series with diodes to VSS/VDD.

----------

DAC range is ± 10 A.
Probe range should be about 2^-14 as big, so ±610 μA
which is 0.000610*10*4.32 = 26.35 mV.

PIC measurements:
  (1.25V + 26.35mV) / (2.50 / 2^12) = 2091
  (1.25V - 26.35mV) / (2.50 / 2^12) = 2004

--

1 bit change at full 16-bit DAC resolution is 0.3mA.
At PIC, the voltage will change by (0.3mA * 10mV/mA * 4.32) = 12.96 mV
This means changing 1 bit at the DAC should cause the 12-bit ADC count to change by
12.96 mV / (2500mV / 2^12) = 21.234

To reset the PIC input to 2048, we therefore need to step the DAC by 
((2048 - count) / 21.234)

--

If it starts off centered, the ADC value at the PIC will max out when
it gets a step of 1250mV.  This corresponds to an input step of 
(1250mV / (10mV/mA * 4.32)) = 28.935 mA.
Sampling rate is 8000 Hz, so this limits slew rate to 28.935 mA * 8000 Hz = 231.48 A/s

A 1A sinusoid with is sin(t*2π*60), so the max slope is max(2π*60*cos(t*2π*60)) = 376.99A/s


TODO:
- Kick sampling rate up by 4, to 32 KHz on ADC and DAC commands.
- That should up our slew rate to 900 A/s.
- Send data to PC as fast as possible; 8KHz or 16KHz or all 32KHz (?)
- Smarter recentering algorithm (!)

