Set up 128 KHz 12-bit ADC sampling with DMA, and send to UART at 0.5 Mbps.
Seems to work well. Next step is to process ADC data at 128 KHz to determine DAC stepping, and send DAC + ADC to PC at 8 KHz. git-svn-id: https://bucket.mit.edu/svn/nilm/zoom@5931 ddd99763-3ecb-0310-9145-efcb8ce7c51f
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jim
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83
firmware/adc.c
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83
firmware/adc.c
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@ -0,0 +1,83 @@
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#include "config.h"
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#include "adc.h"
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#include "timer.h"
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/* Layout of buffer:
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adc_dmabuf[x] contains 16 samples of channel AN0
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*/
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uint16_t adc_dmabuf[16] __attribute__((space(dma)));
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void (*adc_adc_callback)(void) = 0;
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void (*adc_dma_callback)(void) = 0;
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/* ADC1 interrupt after each sample (if enabled) */
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void __attribute__((__interrupt__,auto_psv)) _ADC1Interrupt(void)
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{
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if (adc_adc_callback)
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(*adc_adc_callback)();
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IFS0bits.AD1IF = 0;
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}
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/* DMA0 interrupt after 16 samples */
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void __attribute__((__interrupt__,auto_psv)) _DMA0Interrupt(void)
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{
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if (adc_dma_callback)
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(*adc_dma_callback)();
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IFS0bits.DMA0IF = 0;
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}
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/* Initialize ADC1 to constantly DMA AN0. */
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void adc_init(void)
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{
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/* AD1CON1 */
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AD1CON1bits.ADDMABM = 1; /* Scatter-gather DMA */
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AD1CON1bits.AD12B = 1; /* 12-bit, 1 channel */
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AD1CON1bits.FORM = 0; /* Integer output 0000dddddddddddd */
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AD1CON1bits.SSRC = 2; /* Convert on Timer3 */
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AD1CON1bits.ASAM = 1; /* Automatically start sampling */
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AD1CON1bits.SIMSAM = 0; /* Simul sampling, N/A when AD12B=1 */
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/* AD1CON2 */
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AD1CON2bits.VCFG = 0; /* Ref: AVDD / AVSS */
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// AD1CON2bits.VCFG = 3; /* Ref: VREF+ / VREF- */
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AD1CON2bits.CSCNA = 0; /* Do not scan inputs on Mux A */
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AD1CON2bits.CHPS = 0; /* Convert CH0 only, N/A when AD12B=1 */
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AD1CON2bits.SMPI = 0; /* Increase DMA address at each sample */
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AD1CON2bits.BUFM = 0; /* Fill buffer from start */
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AD1CON2bits.ALTS = 0; /* Always use Mux A settings */
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/* AD1CON3 */
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AD1CON3bits.ADRC = 0; /* Use system clock, not internal RC */
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AD1CON3bits.SAMC = 0; /* Sample time, N/A when ADRC = 0 */
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AD1CON3bits.ADCS = 0x7; /* Tad = 8 * Tcy */
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/* AD1CON4 */
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AD1CON4bits.DMABL = 4; /* Each input gets 16 words in DMA buf */
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/* Channel 0 setup */
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AD1CHS0bits.CH0NA = 0; /* CH0-: Vrefl */
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AD1CHS0bits.CH0SA = 0; /* CH0+: AN0 */
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/* Set Timer3 to trigger conversion at 128KHz */
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timer_setup_16bit(3, 128000, 0);
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/* Turn it on */
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AD1PCFGL = 0xfffe; /* Analog = AN0 */
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AD1PCFGH = 0xffff;
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AD2PCFGL = 0xffff;
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AD1CON1bits.ADON = 1;
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/* DMA0 setup */
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DMA0CONbits.AMODE = 0; /* Register indirect, post-increment */
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DMA0CONbits.MODE = 0; /* Continuous, no ping-pong */
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DMA0PAD = (int)&ADC1BUF0; /* Get addresses from ADC1 */
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DMA0CNT = 15; /* 16 transfers before wraparound */
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DMA0STA = __builtin_dmaoffset(&adc_dmabuf);
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DMA0REQbits.IRQSEL = 13; /* Triggered by ADC1 */
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IFS0bits.DMA0IF = 0;
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IEC0bits.DMA0IE = 1; /* DMA interrupt (every 16 samples) */
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DMA0CONbits.CHEN = 1; /* enable this DMA channel */
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IFS0bits.AD1IF = 0;
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IEC0bits.AD1IE = 0; /* No ADC interrupt (every sample) */
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}
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14
firmware/adc.h
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14
firmware/adc.h
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@ -0,0 +1,14 @@
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#ifndef ADC_H
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#define ADC_H
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/* DMA region for the ADC */
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extern uint16_t adc_dmabuf[16];
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/* Initialize internal ADC */
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void adc_init(void);
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/* Callback functions */
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extern void (*adc_adc_callback)(void);
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extern void (*adc_dma_callback)(void);
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#endif
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@ -12,7 +12,7 @@
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interrupt notification if desired */
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/* Since the ADC is 5v, ADC SDO must be on a digital-only pin.
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All exposed pins on B D and E are digital, so use SPI pins:
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All exposed pins on B D and E are analog, so use SPI pins:
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ADC SDO = PIC SDI1 = RF7
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ADC SCK = PIC SCK1 = RF6
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*/
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@ -30,16 +30,22 @@
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/* Initialize ADC */
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void adcext_init(void)
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{
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int i;
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int32_t i;
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TRIS_SDO = 1;
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LAT_SCK = 0;
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TRIS_SCK = 0;
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/* Startup delay CS down to SCK high t4 = 5000ns */
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for (i = 0; i < 5000 / 25; i++)
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wait_25ns();
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/* We need to monitor BUSY, I think. With the 2-wire
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interface, we never know if we start in the middle of
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a data output phase. For now, consider reading broken..
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just return early. XXXX */
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return;
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/* Trigger a dummy read so we're prepared for the
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next conversion */
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(void) adcext_read();
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@ -118,7 +124,7 @@ void adcext_start_conversion(void)
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LAT_SCK = 0;
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/* Wait tKQMAX for SCK down to SDO valid in case we
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call adc_is_conversion_finished right away. */
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call adcext_is_conversion_ready right away. */
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wait_200ns();
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}
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@ -1,5 +1,5 @@
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#ifndef ADC_H
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#define ADC_H
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#ifndef ADCEXT_H
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#define ADCEXT_H
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/* Initialize ADC */
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void adcext_init(void);
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@ -13,7 +13,6 @@ typedef signed long long int64_t;
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typedef unsigned long long uint64_t;
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#define FCY 40000000
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#define TMR1_RATE 8000
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void config_init(void);
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@ -12,7 +12,7 @@ void uart_init(int uart, int32_t rate)
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if (uart == 1) {
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U1MODE = 0;
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U1MODEbits.BRGH = 0;
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U1MODEbits.BRGH = 0; // errata: BRGH=1 is broken
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U1BRG = brg;
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U1STA = 0;
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U1MODEbits.UARTEN = 1;
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@ -1,39 +1,37 @@
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#include "config.h"
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#include "adc.h"
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#include "adcext.h"
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#include "dac.h"
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#include "uart.h"
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#include "timer.h"
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#include <stdio.h>
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#include <math.h>
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int32_t tmr1_ms = 0;
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void TISR_HANDLER(1)
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int new_data = 0;
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uint16_t data;
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void callback(void)
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{
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/* Send most recent sample to PC */
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data = adc_dmabuf[15];
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new_data = 1;
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}
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int main(void)
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{
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config_init();
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uart1_init(1000000);
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uart1_init(500000);
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adcext_init();
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dac_init();
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timer_setup_16bit(1, 1000, 1);
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TRISDbits.TRISD0 = 0;
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TRISDbits.TRISD1 = 1;
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TRISDbits.TRISD2 = 1;
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adc_init();
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adc_dma_callback = callback;
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while(1) {
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/* these are ints, so it should be atomic */
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/*
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tmp = output_count;
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tmp2 = dacval;
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uart1_put_hex((tmp & 0x7F) | (LATDbits.LATD0 ? 0x80 : 0x00));
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uart1_put_hex((tmp2 & 0xFF00) >> 8);
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uart1_put_hex((tmp2 & 0x00FF));
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uart1_put('\r');
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*/
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if (new_data) {
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uart1_put_hex16(data);
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uart1_crlf();
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new_data = 0;
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}
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}
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for(;;) continue;
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@ -31,6 +31,8 @@ file_010=no
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file_011=no
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file_012=no
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file_013=no
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file_014=no
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file_015=no
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[FILE_INFO]
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file_000=zoom.c
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file_001=config.c
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@ -39,13 +41,15 @@ file_003=util.c
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file_004=dac.c
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file_005=timer.c
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file_006=adcext.c
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file_007=config.h
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file_008=uart.h
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file_009=util.h
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file_010=dac.h
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file_011=timer.h
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file_012=adcext.h
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file_013=p33fj256gp710.gld
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file_007=adc.c
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file_008=config.h
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file_009=uart.h
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file_010=util.h
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file_011=dac.h
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file_012=timer.h
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file_013=adcext.h
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file_014=adc.h
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file_015=p33fj256gp710.gld
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[SUITE_INFO]
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suite_guid={479DDE59-4D56-455E-855E-FFF59A3DB57E}
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suite_state=
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