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@@ -0,0 +1,56 @@ |
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# Freescale i.MX6 series single/dual/quad core processor |
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if { [info exists CHIPNAME] } { |
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set _CHIPNAME $CHIPNAME |
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} else { |
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set _CHIPNAME imx6 |
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} |
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# CoreSight Debug Access Port |
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if { [info exists DAP_TAPID] } { |
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set _DAP_TAPID $DAP_TAPID |
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} else { |
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set _DAP_TAPID 0x4ba00477 |
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} |
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jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \ |
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-expected-id $_DAP_TAPID |
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# SDMA / no IDCODE |
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jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f |
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# System JTAG Controller |
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if { [info exists SJC_TAPID] } { |
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set _SJC_TAPID SJC_TAPID |
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} else { |
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set _SJC_TAPID 0x0191c01d |
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} |
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set _SJC_TAPID2 0x2191c01d |
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jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \ |
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-expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 |
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# GDB target: Cortex-A9, using DAP, configuring only one core |
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# Base addresses of cores: |
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# core 0 - 0x82150000 |
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# core 1 - 0x82152000 |
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# core 2 - 0x82154000 |
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# core 3 - 0x82156000 |
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set _TARGETNAME $_CHIPNAME.cpu.0 |
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target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \ |
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-coreid 0 -dbgbase 0x82150000 |
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# some TCK cycles are required to activate the DEBUG power domain |
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jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100" |
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proc imx6_dbginit {target} { |
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# General Cortex A8/A9 debug initialisation |
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cortex_a8 dbginit |
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} |
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# Slow speed to be sure it will work |
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jtag_rclk 1000 |
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$_TARGETNAME configure -event reset-start { jtag_rclk 1000 } |
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$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME" |
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$_TARGETNAME configure -event gdb-attach { halt } |