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@@ -54,8 +54,6 @@ int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 co |
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int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); |
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int arm926ejs_soft_reset_halt(struct target_s *target); |
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#define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0)) |
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target_type_t arm926ejs_target = |
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{ |
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.name = "arm926ejs", |
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@@ -112,11 +110,14 @@ int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field) |
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return ERROR_JTAG_QUEUE_FAILED;; |
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} |
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int arm926ejs_read_cp15(target_t *target, u32 address, u32 *value) |
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#define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0)) |
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int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value) |
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{ |
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armv4_5_common_t *armv4_5 = target->arch_info; |
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arm7_9_common_t *arm7_9 = armv4_5->arch_info; |
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arm_jtag_t *jtag_info = &arm7_9->jtag_info; |
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u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); |
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scan_field_t fields[4]; |
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u8 address_buf[2]; |
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u8 nr_w_buf = 0; |
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@@ -191,11 +192,12 @@ int arm926ejs_read_cp15(target_t *target, u32 address, u32 *value) |
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return ERROR_OK; |
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} |
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int arm926ejs_write_cp15(target_t *target, u32 address, u32 value) |
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int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value) |
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{ |
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armv4_5_common_t *armv4_5 = target->arch_info; |
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arm7_9_common_t *arm7_9 = armv4_5->arch_info; |
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arm_jtag_t *jtag_info = &arm7_9->jtag_info; |
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u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); |
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scan_field_t fields[4]; |
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u8 value_buf[4]; |
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u8 address_buf[2]; |
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@@ -338,10 +340,14 @@ int arm926ejs_examine_debug_reason(target_t *target) |
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u32 arm926ejs_get_ttb(target_t *target) |
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{ |
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armv4_5_common_t *armv4_5 = target->arch_info; |
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arm7_9_common_t *arm7_9 = armv4_5->arch_info; |
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arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; |
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arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; |
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int retval; |
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u32 ttb = 0x0; |
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if ((retval = arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 2, 0), &ttb)) != ERROR_OK) |
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if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK) |
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return retval; |
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return ttb; |
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@@ -349,16 +355,20 @@ u32 arm926ejs_get_ttb(target_t *target) |
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void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) |
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{ |
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armv4_5_common_t *armv4_5 = target->arch_info; |
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arm7_9_common_t *arm7_9 = armv4_5->arch_info; |
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arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; |
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arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; |
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u32 cp15_control; |
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/* read cp15 control register */ |
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arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &cp15_control); |
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arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control); |
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jtag_execute_queue(); |
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if (mmu) |
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{ |
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/* invalidate TLB */ |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 8, 7), 0x0); |
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arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0); |
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cp15_control &= ~0x1U; |
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} |
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@@ -368,17 +378,17 @@ void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int |
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u32 debug_override; |
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/* read-modify-write CP15 debug override register |
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* to enable "test and clean all" */ |
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arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), &debug_override); |
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arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override); |
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debug_override |= 0x80000; |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), debug_override); |
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arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override); |
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/* clean and invalidate DCache */ |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), 0x0); |
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arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0); |
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/* write CP15 debug override register |
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* to disable "test and clean all" */ |
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debug_override &= ~0x80000; |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), debug_override); |
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arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override); |
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cp15_control &= ~0x4U; |
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} |
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@@ -386,20 +396,24 @@ void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int |
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if (i_cache) |
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{ |
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/* invalidate ICache */ |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), 0x0); |
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arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0); |
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cp15_control &= ~0x1000U; |
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} |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), cp15_control); |
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arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control); |
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} |
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void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) |
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{ |
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armv4_5_common_t *armv4_5 = target->arch_info; |
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arm7_9_common_t *arm7_9 = armv4_5->arch_info; |
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arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; |
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arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; |
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u32 cp15_control; |
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/* read cp15 control register */ |
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arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &cp15_control); |
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arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control); |
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jtag_execute_queue(); |
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if (mmu) |
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@@ -411,7 +425,7 @@ void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i |
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if (i_cache) |
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cp15_control |= 0x1000U; |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), cp15_control); |
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arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control); |
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} |
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void arm926ejs_post_debug_entry(target_t *target) |
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@@ -422,7 +436,7 @@ void arm926ejs_post_debug_entry(target_t *target) |
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arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; |
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/* examine cp15 control reg */ |
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arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &arm926ejs->cp15_control_reg); |
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arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg); |
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jtag_execute_queue(); |
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DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg); |
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@@ -430,7 +444,7 @@ void arm926ejs_post_debug_entry(target_t *target) |
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{ |
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u32 cache_type_reg; |
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/* identify caches */ |
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arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 0, 0), &cache_type_reg); |
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arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg); |
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jtag_execute_queue(); |
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armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache); |
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} |
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@@ -440,9 +454,9 @@ void arm926ejs_post_debug_entry(target_t *target) |
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arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0; |
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/* save i/d fault status and address register */ |
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arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 5, 0), &arm926ejs->d_fsr); |
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arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 5, 0), &arm926ejs->i_fsr); |
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arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 6, 0), &arm926ejs->d_far); |
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arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr); |
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arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr); |
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arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far); |
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DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x", |
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arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr); |
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@@ -452,9 +466,9 @@ void arm926ejs_post_debug_entry(target_t *target) |
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/* read-modify-write CP15 cache debug control register |
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* to disable I/D-cache linefills and force WT */ |
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arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl); |
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arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl); |
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cache_dbg_ctrl |= 0x7; |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl); |
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arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl); |
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} |
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void arm926ejs_pre_restore_context(target_t *target) |
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@@ -465,17 +479,17 @@ void arm926ejs_pre_restore_context(target_t *target) |
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arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; |
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/* restore i/d fault status and address register */ |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 5, 0), arm926ejs->d_fsr); |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 5, 0), arm926ejs->i_fsr); |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 6, 0), arm926ejs->d_far); |
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arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr); |
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arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr); |
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arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far); |
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u32 cache_dbg_ctrl; |
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/* read-modify-write CP15 cache debug control register |
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* to reenable I/D-cache linefills and disable WT */ |
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arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl); |
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arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl); |
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cache_dbg_ctrl &= ~0x7; |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl); |
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arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl); |
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} |
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int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p) |
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@@ -613,12 +627,12 @@ int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 c |
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if (count <= 1) |
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{ |
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/* invalidate ICache single entry with MVA */ |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 7, 5), address); |
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arm926ejs->write_cp15(target, 0, 1, 7, 5, address); |
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} |
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else |
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{ |
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/* invalidate ICache */ |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), address); |
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arm926ejs->write_cp15(target, 0, 0, 7, 5, address); |
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} |
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} |
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@@ -654,6 +668,8 @@ int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, in |
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arm7_9->post_debug_entry = arm926ejs_post_debug_entry; |
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arm7_9->pre_restore_context = arm926ejs_pre_restore_context; |
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arm926ejs->read_cp15 = arm926ejs_cp15_read; |
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arm926ejs->write_cp15 = arm926ejs_cp15_write; |
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arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1; |
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arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb; |
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arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory; |
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@@ -766,7 +782,7 @@ int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, |
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if (argc == 4) |
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{ |
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u32 value; |
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if ((retval = arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm), &value)) != ERROR_OK) |
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if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK) |
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{ |
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command_print(cmd_ctx, "couldn't access register"); |
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return ERROR_OK; |
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@@ -778,7 +794,7 @@ int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, |
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else |
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{ |
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u32 value = strtoul(args[4], NULL, 0); |
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if ((retval = arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm), value)) != ERROR_OK) |
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if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK) |
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{ |
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command_print(cmd_ctx, "couldn't access register"); |
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return ERROR_OK; |
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