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@@ -165,8 +165,11 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode) |
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retval = mem_ap_read_atomic_u32(swjdp, |
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armv7a->debug_base + CPUDBG_DSCR, &dscr); |
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if (retval != ERROR_OK) |
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{ |
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LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode); |
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return retval; |
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} |
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} |
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while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */ |
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mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode); |
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@@ -176,8 +179,11 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode) |
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retval = mem_ap_read_atomic_u32(swjdp, |
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armv7a->debug_base + CPUDBG_DSCR, &dscr); |
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if (retval != ERROR_OK) |
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{ |
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LOG_ERROR("Could not read DSCR register"); |
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return retval; |
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} |
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} |
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while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */ |
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return retval; |
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