@@ -34,8 +34,6 @@ | |||
int arm720t_register_commands(struct command_context_s *cmd_ctx); | |||
int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); | |||
int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); | |||
int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); | |||
/* forward declarations */ | |||
int arm720t_target_create(struct target_s *target,Jim_Interp *interp); | |||
@@ -514,14 +512,6 @@ int arm720t_register_commands(struct command_context_s *cmd_ctx) | |||
register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]"); | |||
register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]"); | |||
register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]"); | |||
register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]"); | |||
register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>"); | |||
register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>"); | |||
register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>"); | |||
return ERROR_OK; | |||
} | |||
@@ -584,55 +574,3 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch | |||
return ERROR_OK; | |||
} | |||
int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) | |||
{ | |||
target_t *target = get_current_target(cmd_ctx); | |||
armv4_5_common_t *armv4_5; | |||
arm7_9_common_t *arm7_9; | |||
arm7tdmi_common_t *arm7tdmi; | |||
arm720t_common_t *arm720t; | |||
arm_jtag_t *jtag_info; | |||
if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK) | |||
{ | |||
command_print(cmd_ctx, "current target isn't an ARM720t target"); | |||
return ERROR_OK; | |||
} | |||
jtag_info = &arm7_9->jtag_info; | |||
if (target->state != TARGET_HALTED) | |||
{ | |||
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); | |||
return ERROR_OK; | |||
} | |||
return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); | |||
} | |||
int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) | |||
{ | |||
target_t *target = get_current_target(cmd_ctx); | |||
armv4_5_common_t *armv4_5; | |||
arm7_9_common_t *arm7_9; | |||
arm7tdmi_common_t *arm7tdmi; | |||
arm720t_common_t *arm720t; | |||
arm_jtag_t *jtag_info; | |||
if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK) | |||
{ | |||
command_print(cmd_ctx, "current target isn't an ARM720t target"); | |||
return ERROR_OK; | |||
} | |||
jtag_info = &arm7_9->jtag_info; | |||
if (target->state != TARGET_HALTED) | |||
{ | |||
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); | |||
return ERROR_OK; | |||
} | |||
return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); | |||
} |
@@ -34,8 +34,6 @@ | |||
int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); | |||
int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); | |||
int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); | |||
int arm920t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); | |||
int arm920t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); | |||
int arm920t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); | |||
int arm920t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); | |||
@@ -726,14 +724,6 @@ int arm920t_register_commands(struct command_context_s *cmd_ctx) | |||
register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]"); | |||
register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches"); | |||
register_command(cmd_ctx, arm920t_cmd, "mdw_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]"); | |||
register_command(cmd_ctx, arm920t_cmd, "mdh_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]"); | |||
register_command(cmd_ctx, arm920t_cmd, "mdb_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]"); | |||
register_command(cmd_ctx, arm920t_cmd, "mww_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>"); | |||
register_command(cmd_ctx, arm920t_cmd, "mwh_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>"); | |||
register_command(cmd_ctx, arm920t_cmd, "mwb_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>"); | |||
register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content"); | |||
register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content"); | |||
@@ -1425,55 +1415,3 @@ int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *c | |||
return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache); | |||
} | |||
int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) | |||
{ | |||
target_t *target = get_current_target(cmd_ctx); | |||
armv4_5_common_t *armv4_5; | |||
arm7_9_common_t *arm7_9; | |||
arm9tdmi_common_t *arm9tdmi; | |||
arm920t_common_t *arm920t; | |||
arm_jtag_t *jtag_info; | |||
if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK) | |||
{ | |||
command_print(cmd_ctx, "current target isn't an ARM920t target"); | |||
return ERROR_OK; | |||
} | |||
jtag_info = &arm7_9->jtag_info; | |||
if (target->state != TARGET_HALTED) | |||
{ | |||
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); | |||
return ERROR_OK; | |||
} | |||
return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu); | |||
} | |||
int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) | |||
{ | |||
target_t *target = get_current_target(cmd_ctx); | |||
armv4_5_common_t *armv4_5; | |||
arm7_9_common_t *arm7_9; | |||
arm9tdmi_common_t *arm9tdmi; | |||
arm920t_common_t *arm920t; | |||
arm_jtag_t *jtag_info; | |||
if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK) | |||
{ | |||
command_print(cmd_ctx, "current target isn't an ARM920t target"); | |||
return ERROR_OK; | |||
} | |||
jtag_info = &arm7_9->jtag_info; | |||
if (target->state != TARGET_HALTED) | |||
{ | |||
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); | |||
return ERROR_OK; | |||
} | |||
return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu); | |||
} |
@@ -37,8 +37,6 @@ | |||
int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); | |||
int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); | |||
int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); | |||
int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); | |||
int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); | |||
int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); | |||
int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); | |||
@@ -835,14 +833,6 @@ int arm926ejs_register_commands(struct command_context_s *cmd_ctx) | |||
register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches"); | |||
register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]"); | |||
register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]"); | |||
register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]"); | |||
register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>"); | |||
register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>"); | |||
register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>"); | |||
return retval; | |||
} | |||
@@ -928,58 +918,6 @@ int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char | |||
return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache); | |||
} | |||
int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) | |||
{ | |||
target_t *target = get_current_target(cmd_ctx); | |||
armv4_5_common_t *armv4_5; | |||
arm7_9_common_t *arm7_9; | |||
arm9tdmi_common_t *arm9tdmi; | |||
arm926ejs_common_t *arm926ejs; | |||
arm_jtag_t *jtag_info; | |||
if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK) | |||
{ | |||
command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); | |||
return ERROR_OK; | |||
} | |||
jtag_info = &arm7_9->jtag_info; | |||
if (target->state != TARGET_HALTED) | |||
{ | |||
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); | |||
return ERROR_OK; | |||
} | |||
return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu); | |||
} | |||
int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) | |||
{ | |||
target_t *target = get_current_target(cmd_ctx); | |||
armv4_5_common_t *armv4_5; | |||
arm7_9_common_t *arm7_9; | |||
arm9tdmi_common_t *arm9tdmi; | |||
arm926ejs_common_t *arm926ejs; | |||
arm_jtag_t *jtag_info; | |||
if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK) | |||
{ | |||
command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); | |||
return ERROR_OK; | |||
} | |||
jtag_info = &arm7_9->jtag_info; | |||
if (target->state != TARGET_HALTED) | |||
{ | |||
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); | |||
return ERROR_OK; | |||
} | |||
return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu); | |||
} | |||
static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical) | |||
{ | |||
int retval; | |||
@@ -169,154 +169,3 @@ int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_m | |||
return retval; | |||
} | |||
int armv4_5_mmu_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu) | |||
{ | |||
int count = 1; | |||
int size = 4; | |||
uint32_t address = 0; | |||
int i; | |||
char output[128]; | |||
int output_len; | |||
int retval; | |||
uint8_t *buffer; | |||
if (target->state != TARGET_HALTED) | |||
{ | |||
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); | |||
return ERROR_OK; | |||
} | |||
if (argc < 1) | |||
return ERROR_OK; | |||
if (argc == 2) | |||
count = strtoul(args[1], NULL, 0); | |||
address = strtoul(args[0], NULL, 0); | |||
switch (cmd[2]) | |||
{ | |||
case 'w': | |||
size = 4; | |||
break; | |||
case 'h': | |||
size = 2; | |||
break; | |||
case 'b': | |||
size = 1; | |||
break; | |||
default: | |||
return ERROR_OK; | |||
} | |||
buffer = calloc(count, size); | |||
if ((retval = armv4_5_mmu_read_physical(target, armv4_5_mmu, address, size, count, buffer)) != ERROR_OK) | |||
{ | |||
switch (retval) | |||
{ | |||
case ERROR_TARGET_UNALIGNED_ACCESS: | |||
command_print(cmd_ctx, "error: address not aligned"); | |||
break; | |||
case ERROR_TARGET_NOT_HALTED: | |||
command_print(cmd_ctx, "error: target must be halted for memory accesses"); | |||
break; | |||
case ERROR_TARGET_DATA_ABORT: | |||
command_print(cmd_ctx, "error: access caused data abort, system possibly corrupted"); | |||
break; | |||
default: | |||
command_print(cmd_ctx, "error: unknown error"); | |||
} | |||
} | |||
output_len = 0; | |||
for (i = 0; i < count; i++) | |||
{ | |||
if (i%8 == 0) | |||
output_len += snprintf(output + output_len, 128 - output_len, "0x%8.8" PRIx32 ": ", address + (i*size)); | |||
switch (size) | |||
{ | |||
case 4: | |||
output_len += snprintf(output + output_len, 128 - output_len, "%8.8" PRIx32 " ", target_buffer_get_u32(target, &buffer[i*4])); | |||
break; | |||
case 2: | |||
output_len += snprintf(output + output_len, 128 - output_len, "%4.4x ", target_buffer_get_u16(target, &buffer[i*2])); | |||
break; | |||
case 1: | |||
output_len += snprintf(output + output_len, 128 - output_len, "%2.2x ", buffer[i*1]); | |||
break; | |||
} | |||
if ((i % 8 == 7) || (i == count - 1)) | |||
{ | |||
command_print(cmd_ctx, "%s", output); | |||
output_len = 0; | |||
} | |||
} | |||
free(buffer); | |||
return ERROR_OK; | |||
} | |||
int armv4_5_mmu_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu) | |||
{ | |||
uint32_t address = 0; | |||
uint32_t value = 0; | |||
int retval; | |||
uint8_t value_buf[4]; | |||
if (target->state != TARGET_HALTED) | |||
{ | |||
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); | |||
return ERROR_OK; | |||
} | |||
if (argc < 2) | |||
return ERROR_OK; | |||
address = strtoul(args[0], NULL, 0); | |||
value = strtoul(args[1], NULL, 0); | |||
switch (cmd[2]) | |||
{ | |||
case 'w': | |||
target_buffer_set_u32(target, value_buf, value); | |||
retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 4, 1, value_buf); | |||
break; | |||
case 'h': | |||
target_buffer_set_u16(target, value_buf, value); | |||
retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 2, 1, value_buf); | |||
break; | |||
case 'b': | |||
value_buf[0] = value; | |||
retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 1, 1, value_buf); | |||
break; | |||
default: | |||
return ERROR_OK; | |||
} | |||
switch (retval) | |||
{ | |||
case ERROR_TARGET_UNALIGNED_ACCESS: | |||
command_print(cmd_ctx, "error: address not aligned"); | |||
break; | |||
case ERROR_TARGET_DATA_ABORT: | |||
command_print(cmd_ctx, "error: access caused data abort, system possibly corrupted"); | |||
break; | |||
case ERROR_TARGET_NOT_HALTED: | |||
command_print(cmd_ctx, "error: target must be halted for memory accesses"); | |||
break; | |||
case ERROR_OK: | |||
break; | |||
default: | |||
command_print(cmd_ctx, "error: unknown error"); | |||
} | |||
return ERROR_OK; | |||
} |
@@ -46,10 +46,6 @@ extern uint32_t armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t | |||
extern int armv4_5_mmu_read_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); | |||
extern int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); | |||
extern int armv4_5_mmu_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu); | |||
extern int armv4_5_mmu_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu); | |||
extern int armv4_5_mmu_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu); | |||
enum | |||
{ | |||
ARMV4_5_MMU_ENABLED = 0x1, | |||