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@@ -608,6 +608,13 @@ int arm11_leave_debug_state(arm11_common_t * arm11) |
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if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL)) |
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{ |
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/* |
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The wDTR/rDTR two registers that are used to send/receive data to/from |
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the core in tandem with corresponding instruction codes that are |
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written into the core. The RDTR FULL/WDTR FULL flag indicates that the |
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registers hold data that was written by one side (CPU or JTAG) and not |
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read out by the other side. |
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*/ |
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LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR); |
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return ERROR_FAIL; |
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} |
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@@ -702,9 +709,6 @@ int arm11_poll(struct target_s *target) |
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arm11_common_t * arm11 = target->arch_info; |
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if (arm11->trst_active) |
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return ERROR_OK; |
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uint32_t dscr; |
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CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr)); |
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@@ -784,12 +788,6 @@ int arm11_halt(struct target_s *target) |
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return ERROR_OK; |
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} |
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if (arm11->trst_active) |
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{ |
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arm11->halt_requested = true; |
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return ERROR_OK; |
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} |
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arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE); |
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CHECK_RETVAL(jtag_execute_queue()); |
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@@ -1199,22 +1197,16 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl |
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return ERROR_OK; |
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} |
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/* target reset control */ |
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int arm11_assert_reset(struct target_s *target) |
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int arm11_assert_reset(target_t *target) |
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{ |
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FNC_INFO; |
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#if 0 |
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/* assert reset lines */ |
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/* resets only the DBGTAP, not the ARM */ |
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jtag_add_reset(1, 0); |
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jtag_add_sleep(5000); |
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arm11_common_t * arm11 = target->arch_info; |
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arm11->trst_active = true; |
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#endif |
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/* FIX! we really should assert srst here, but |
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* how do we reset the target into the halted state? |
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* |
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* Also arm11 behaves "funny" when srst is asserted |
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* (as of writing the rules are not understood). |
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*/ |
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if (target->reset_halt) |
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{ |
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CHECK_RETVAL(target_halt(target)); |
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@@ -1223,25 +1215,8 @@ int arm11_assert_reset(struct target_s *target) |
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return ERROR_OK; |
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} |
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int arm11_deassert_reset(struct target_s *target) |
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int arm11_deassert_reset(target_t *target) |
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{ |
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FNC_INFO; |
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#if 0 |
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LOG_DEBUG("target->state: %s", |
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target_state_name(target)); |
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/* deassert reset lines */ |
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jtag_add_reset(0, 0); |
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arm11_common_t * arm11 = target->arch_info; |
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arm11->trst_active = false; |
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if (arm11->halt_requested) |
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return arm11_halt(target); |
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#endif |
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return ERROR_OK; |
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} |
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@@ -1807,6 +1782,8 @@ int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target |
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/* talk to the target and set things up */ |
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int arm11_examine(struct target_s *target) |
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{ |
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int retval; |
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FNC_INFO; |
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arm11_common_t * arm11 = target->arch_info; |
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@@ -1874,7 +1851,9 @@ int arm11_examine(struct target_s *target) |
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* as suggested by the spec. |
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*/ |
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arm11_check_init(arm11, NULL); |
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retval = arm11_check_init(arm11, NULL); |
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if (retval != ERROR_OK) |
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return retval; |
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target_set_examined(target); |
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