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Delete commented out code. Add a bit of error checking.

tags/v0.3.0-rc0
Øyvind Harboe 12 years ago
parent
commit
1f917bdc0c
3 changed files with 21 additions and 48 deletions
  1. +1
    -3
      TODO
  2. +20
    -41
      src/target/arm11.c
  3. +0
    -4
      src/target/arm11.h

+ 1
- 3
TODO View File

@@ -138,11 +138,9 @@ https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
- ARM923EJS:
- reset run/halt/step is not robust; needs testing to map out problems.
- ARM11 improvements (MB?)
- add support for asserting srst to reset the core.
- Single stepping works, but should automatically
use hardware stepping if available.
- hunt down and add timeouts to all infinite loops, e.g. arm11_run_instr_no_data would
lock up in infinite loop if e.g. an "mdh" command tries to read memory from invalid memory location.
Try mdh 0x40000000 on i.MX31 PDK
- mdb can return garbage data if read byte operation fails for
a memory region(16 & 32 byte access modes may be supported). Is this
a bug in the .MX31 PDK init script? Try on i.MX31 PDK:


+ 20
- 41
src/target/arm11.c View File

@@ -608,6 +608,13 @@ int arm11_leave_debug_state(arm11_common_t * arm11)

if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
{
/*
The wDTR/rDTR two registers that are used to send/receive data to/from
the core in tandem with corresponding instruction codes that are
written into the core. The RDTR FULL/WDTR FULL flag indicates that the
registers hold data that was written by one side (CPU or JTAG) and not
read out by the other side.
*/
LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
return ERROR_FAIL;
}
@@ -702,9 +709,6 @@ int arm11_poll(struct target_s *target)

arm11_common_t * arm11 = target->arch_info;

if (arm11->trst_active)
return ERROR_OK;

uint32_t dscr;

CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
@@ -784,12 +788,6 @@ int arm11_halt(struct target_s *target)
return ERROR_OK;
}

if (arm11->trst_active)
{
arm11->halt_requested = true;
return ERROR_OK;
}

arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);

CHECK_RETVAL(jtag_execute_queue());
@@ -1199,22 +1197,16 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl
return ERROR_OK;
}

/* target reset control */
int arm11_assert_reset(struct target_s *target)
int arm11_assert_reset(target_t *target)
{
FNC_INFO;

#if 0
/* assert reset lines */
/* resets only the DBGTAP, not the ARM */

jtag_add_reset(1, 0);
jtag_add_sleep(5000);

arm11_common_t * arm11 = target->arch_info;
arm11->trst_active = true;
#endif

/* FIX! we really should assert srst here, but
* how do we reset the target into the halted state?
*
* Also arm11 behaves "funny" when srst is asserted
* (as of writing the rules are not understood).
*/
if (target->reset_halt)
{
CHECK_RETVAL(target_halt(target));
@@ -1223,25 +1215,8 @@ int arm11_assert_reset(struct target_s *target)
return ERROR_OK;
}

int arm11_deassert_reset(struct target_s *target)
int arm11_deassert_reset(target_t *target)
{
FNC_INFO;

#if 0
LOG_DEBUG("target->state: %s",
target_state_name(target));


/* deassert reset lines */
jtag_add_reset(0, 0);

arm11_common_t * arm11 = target->arch_info;
arm11->trst_active = false;

if (arm11->halt_requested)
return arm11_halt(target);
#endif

return ERROR_OK;
}

@@ -1807,6 +1782,8 @@ int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target
/* talk to the target and set things up */
int arm11_examine(struct target_s *target)
{
int retval;

FNC_INFO;

arm11_common_t * arm11 = target->arch_info;
@@ -1874,7 +1851,9 @@ int arm11_examine(struct target_s *target)
* as suggested by the spec.
*/

arm11_check_init(arm11, NULL);
retval = arm11_check_init(arm11, NULL);
if (retval != ERROR_OK)
return retval;

target_set_examined(target);



+ 0
- 4
src/target/arm11.h View File

@@ -98,10 +98,6 @@ typedef struct arm11_common_s
uint32_t last_dscr; /**< Last retrieved DSCR value;
Use only for debug message generation */

bool trst_active;
bool halt_requested; /**< Keep track if arm11_halt() calls occured
during reset. Otherwise do it ASAP. */

bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */

/** \name Shadow registers to save processor state */


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