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@@ -12,9 +12,9 @@ jtag_ntrst_delay 250 |
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# CS0, CS1 -- two banks of CFI flash, 32 MBytes each |
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# each bank is 32-bits wide, two 16-bit chips in parallel |
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set _FLASHNAME $_CHIPNAME.flash |
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set _FLASHNAME $_CHIPNAME.flash0 |
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flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME |
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set _FLASHNAME $_CHIPNAME.flash |
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set _FLASHNAME $_CHIPNAME.flash1 |
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flash bank $_FLASHNAME cfi 0x04000000 0x02000000 2 4 $_TARGETNAME |
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# CS2 low -- FPGA registers |
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