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/*************************************************************************** |
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* Copyright (C) 2013 by Andrey Yurovsky * |
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* Andrey Yurovsky <yurovsky@gmail.com> * |
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* * |
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* This program is free software; you can redistribute it and/or modify * |
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* it under the terms of the GNU General Public License as published by * |
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* the Free Software Foundation; either version 2 of the License, or * |
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* (at your option) any later version. * |
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* * |
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* This program is distributed in the hope that it will be useful, * |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of * |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
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* GNU General Public License for more details. * |
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* * |
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* You should have received a copy of the GNU General Public License * |
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* along with this program; if not, write to the * |
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* Free Software Foundation, Inc., * |
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * |
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***************************************************************************/ |
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#ifdef HAVE_CONFIG_H |
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#include "config.h" |
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#endif |
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#include "imp.h" |
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#define SAMD_NUM_SECTORS 16 |
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#define SAMD_FLASH 0x00000000 /* physical Flash memory */ |
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#define SAMD_DSU 0x41002000 /* Device Service Unit */ |
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#define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */ |
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#define SAMD_DSU_DID 0x18 /* Device ID register */ |
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#define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */ |
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#define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */ |
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#define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */ |
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#define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interupt Flag Status & Clear */ |
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#define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */ |
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#define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */ |
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#define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */ |
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#define SAMD_CMDEX_KEY 0xA5UL |
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#define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F)) |
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/* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */ |
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#define SAMD_NVM_CMD_ER 0x02 /* Erase Row */ |
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#define SAMD_NVM_CMD_WP 0x04 /* Write Page */ |
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#define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxilary Row */ |
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#define SAMD_NVM_CMD_WAP 0x06 /* Write Auxilary Page */ |
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#define SAMD_NVM_CMD_LR 0x40 /* Lock Region */ |
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#define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */ |
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#define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */ |
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#define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */ |
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#define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */ |
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#define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */ |
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#define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */ |
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/* Known identifiers */ |
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#define SAMD_PROCESSOR_M0 0x01 |
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#define SAMD_FAMILY_D 0x00 |
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#define SAMD_SERIES_20 0x00 |
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struct samd_part { |
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uint8_t id; |
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const char *name; |
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uint32_t flash_kb; |
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uint32_t ram_kb; |
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}; |
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/* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */ |
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static struct samd_part samd20_parts[] = { |
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{ 0x0, "SAMD20J18A", 256, 32 }, |
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{ 0x1, "SAMD20J17A", 128, 16 }, |
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{ 0x2, "SAMD20J16A", 64, 8 }, |
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{ 0x3, "SAMD20J15A", 32, 4 }, |
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{ 0x4, "SAMD20J14A", 16, 2 }, |
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{ 0x5, "SAMD20G18A", 256, 32 }, |
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{ 0x6, "SAMD20G17A", 128, 16 }, |
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{ 0x7, "SAMD20G16A", 64, 8 }, |
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{ 0x8, "SAMD20G15A", 32, 4 }, |
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{ 0x9, "SAMD20G14A", 16, 2 }, |
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{ 0xB, "SAMD20E17A", 128, 16 }, |
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{ 0xC, "SAMD20E16A", 64, 8 }, |
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{ 0xD, "SAMD20E15A", 32, 4 }, |
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{ 0xE, "SAMD20E14A", 16, 2 }, |
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}; |
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/* Each family of parts contains a parts table in the DEVSEL field of DID. The |
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* processor ID, family ID, and series ID are used to determine which exact |
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* family this is and then we can use the corresponding table. */ |
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struct samd_family { |
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uint8_t processor; |
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uint8_t family; |
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uint8_t series; |
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struct samd_part *parts; |
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size_t num_parts; |
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}; |
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/* Known SAMD families */ |
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static struct samd_family samd_families[] = { |
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{ SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20, |
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samd20_parts, ARRAY_SIZE(samd20_parts) }, |
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}; |
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struct samd_info { |
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uint32_t page_size; |
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int num_pages; |
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int sector_size; |
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bool probed; |
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struct target *target; |
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struct samd_info *next; |
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}; |
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static struct samd_info *samd_chips; |
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static struct samd_part *samd_find_part(uint32_t id) |
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{ |
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uint8_t processor = (id >> 28); |
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uint8_t family = (id >> 24) & 0x0F; |
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uint8_t series = (id >> 16) & 0xFF; |
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uint8_t devsel = id & 0xFF; |
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for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) { |
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if (samd_families[i].processor == processor && |
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samd_families[i].series == series && |
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samd_families[i].family == family) { |
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for (unsigned j = 0; j < samd_families[i].num_parts; j++) { |
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if (samd_families[i].parts[j].id == devsel) |
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return &samd_families[i].parts[j]; |
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} |
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} |
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} |
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return NULL; |
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} |
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static int samd_protect_check(struct flash_bank *bank) |
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{ |
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int res; |
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uint16_t lock; |
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res = target_read_u16(bank->target, |
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SAMD_NVMCTRL + SAMD_NVMCTRL_LOCK, &lock); |
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if (res != ERROR_OK) |
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return res; |
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/* Lock bits are active-low */ |
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for (int i = 0; i < bank->num_sectors; i++) |
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bank->sectors[i].is_protected = !(lock & (1<<i)); |
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return ERROR_OK; |
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} |
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static int samd_probe(struct flash_bank *bank) |
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{ |
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uint32_t id, param; |
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int res; |
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struct samd_info *chip = (struct samd_info *)bank->driver_priv; |
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struct samd_part *part; |
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if (chip->probed) |
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return ERROR_OK; |
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res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id); |
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if (res != ERROR_OK) { |
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LOG_ERROR("Couldn't read Device ID register"); |
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return res; |
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} |
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part = samd_find_part(id); |
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if (part == NULL) { |
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LOG_ERROR("Couldn't find part correspoding to DID %08" PRIx32, id); |
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return ERROR_FAIL; |
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} |
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res = target_read_u32(bank->target, |
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SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, ¶m); |
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if (res != ERROR_OK) { |
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LOG_ERROR("Couldn't read NVM Parameters register"); |
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return res; |
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} |
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bank->size = part->flash_kb * 1024; |
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chip->sector_size = bank->size / SAMD_NUM_SECTORS; |
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/* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n) so |
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* 0 is 8KB and 7 is 1024KB. */ |
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chip->page_size = (8 << ((param >> 16) & 0x7)); |
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/* The NVMP field (bits 15:0) indicates the total number of pages */ |
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chip->num_pages = param & 0xFFFF; |
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/* Sanity check: the total flash size in the DSU should match the page size |
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* multiplied by the number of pages. */ |
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if (bank->size != chip->num_pages * chip->page_size) { |
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LOG_WARNING("SAMD: bank size doesn't match NVM parameters. " |
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"Identified %uKB Flash but NVMCTRL reports %u %uB pages", |
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part->flash_kb, chip->num_pages, chip->page_size); |
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} |
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/* Allocate the sector table */ |
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bank->num_sectors = SAMD_NUM_SECTORS; |
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bank->sectors = calloc(bank->num_sectors, sizeof((bank->sectors)[0])); |
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if (!bank->sectors) |
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return ERROR_FAIL; |
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/* Fill out the sector information: all SAMD sectors are the same size and |
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* there is always a fixed number of them. */ |
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for (int i = 0; i < bank->num_sectors; i++) { |
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bank->sectors[i].size = chip->sector_size; |
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bank->sectors[i].offset = i * chip->sector_size; |
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/* mark as unknown */ |
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bank->sectors[i].is_erased = -1; |
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bank->sectors[i].is_protected = -1; |
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} |
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samd_protect_check(bank); |
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/* Done */ |
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chip->probed = true; |
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LOG_INFO("SAMD MCU: %s (%uKB Flash, %uKB RAM)", part->name, |
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part->flash_kb, part->ram_kb); |
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return ERROR_OK; |
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} |
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static int samd_protect(struct flash_bank *bank, int set, int first, int last) |
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{ |
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int res; |
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struct samd_info *chip = (struct samd_info *)bank->driver_priv; |
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for (int s = first; s <= last; s++) { |
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/* Load an address that is within this sector (we use offset 0) */ |
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res = target_write_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, |
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s * chip->sector_size); |
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if (res != ERROR_OK) |
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return res; |
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/* Tell the controller to lock that sector */ |
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res = target_write_u16(bank->target, |
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SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, |
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SAMD_NVM_CMD(SAMD_NVM_CMD_LR)); |
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if (res != ERROR_OK) |
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return res; |
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} |
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samd_protect_check(bank); |
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return ERROR_OK; |
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} |
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static bool samd_check_error(struct flash_bank *bank) |
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{ |
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int ret; |
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bool error; |
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uint16_t status; |
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ret = target_read_u16(bank->target, |
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SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status); |
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if (ret != ERROR_OK) { |
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LOG_ERROR("Can't read NVM status"); |
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return true; |
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} |
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if (status & 0x001C) { |
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if (status & (1 << 4)) /* NVME */ |
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LOG_ERROR("SAMD: NVM Error"); |
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if (status & (1 << 3)) /* LOCKE */ |
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LOG_ERROR("SAMD: NVM lock error"); |
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if (status & (1 << 2)) /* PROGE */ |
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LOG_ERROR("SAMD: NVM programming error"); |
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error = true; |
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} else { |
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error = false; |
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} |
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/* Clear the error conditions by writing a one to them */ |
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ret = target_write_u16(bank->target, |
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SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, status); |
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if (ret != ERROR_OK) |
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LOG_ERROR("Can't clear NVM error conditions"); |
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return error; |
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} |
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static int samd_erase_row(struct flash_bank *bank, uint32_t address) |
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{ |
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int res; |
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bool error = false; |
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/* Set an address contained in the row to be erased */ |
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res = target_write_u32(bank->target, |
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SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, address >> 1); |
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if (res == ERROR_OK) { |
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/* Issue the Erase Row command to erase that row */ |
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res = target_write_u16(bank->target, |
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SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, |
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SAMD_NVM_CMD(SAMD_NVM_CMD_ER)); |
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/* Check (and clear) error conditions */ |
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error = samd_check_error(bank); |
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} |
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if (res != ERROR_OK || error) { |
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LOG_ERROR("Failed to erase row containing %08X" PRIx32, address); |
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return ERROR_FAIL; |
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} |
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return ERROR_OK; |
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} |
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static int samd_erase(struct flash_bank *bank, int first, int last) |
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{ |
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int res; |
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int rows_in_sector; |
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struct samd_info *chip = (struct samd_info *)bank->driver_priv; |
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if (bank->target->state != TARGET_HALTED) { |
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LOG_ERROR("Target not halted"); |
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return ERROR_TARGET_NOT_HALTED; |
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} |
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if (!chip->probed) { |
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if (samd_probe(bank) != ERROR_OK) |
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return ERROR_FLASH_BANK_NOT_PROBED; |
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} |
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/* Make sure the sectors make sense. */ |
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if (first >= bank->num_sectors || last >= bank->num_sectors) { |
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LOG_ERROR("Erase range %d - %d not valid (%d sectors total)", |
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first, last, bank->num_sectors); |
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return ERROR_FAIL; |
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} |
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/* The SAMD NVM has row erase granularity. There are four pages in a row |
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* and the number of rows in a sector depends on the sector size, which in |
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* turn depends on the Flash capacity as there is a fixed number of |
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* sectors. */ |
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rows_in_sector = chip->sector_size / (chip->page_size * 4); |
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/* For each sector to be erased */ |
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for (int s = first; s <= last; s++) { |
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/* For each row in that sector */ |
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for (int r = s * rows_in_sector; r < (s + 1) * rows_in_sector; r++) { |
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res = samd_erase_row(bank, r * chip->page_size * 4); |
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if (res != ERROR_OK) { |
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LOG_ERROR("SAMD: failed to erase sector %d", s); |
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return res; |
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} |
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} |
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bank->sectors[s].is_erased = 1; |
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} |
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return ERROR_OK; |
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} |
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/* Write an entire row (four pages) from host buffer 'buf' to row-aligned |
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* 'address' in the Flash. */ |
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static int samd_write_row(struct flash_bank *bank, uint32_t address, |
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uint8_t *buf) |
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{ |
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int res; |
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struct samd_info *chip = (struct samd_info *)bank->driver_priv; |
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/* Erase the row that we'll be writing to */ |
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res = samd_erase_row(bank, address); |
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if (res != ERROR_OK) |
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return res; |
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/* Now write the pages in this row. */ |
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for (unsigned int i = 0; i < 4; i++) { |
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bool error; |
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/* Write the page contents to the target's page buffer. A page write |
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* is issued automatically once the last location is written in the |
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* page buffer (ie: a complete page has been written out). */ |
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res = target_write_memory(bank->target, address, 4, |
|
|
|
chip->page_size / 4, buf); |
|
|
|
if (res != ERROR_OK) { |
|
|
|
LOG_ERROR("%s: %d", __func__, __LINE__); |
|
|
|
return res; |
|
|
|
} |
|
|
|
|
|
|
|
error = samd_check_error(bank); |
|
|
|
if (error) |
|
|
|
return ERROR_FAIL; |
|
|
|
|
|
|
|
/* Next page */ |
|
|
|
address += chip->page_size; |
|
|
|
buf += chip->page_size; |
|
|
|
} |
|
|
|
|
|
|
|
return res; |
|
|
|
} |
|
|
|
|
|
|
|
/* Write partial contents into row-aligned 'address' on the Flash from host |
|
|
|
* buffer 'buf' by writing 'nb' of 'buf' at 'row_offset' into the Flash row. */ |
|
|
|
static int samd_write_row_partial(struct flash_bank *bank, uint32_t address, |
|
|
|
uint8_t *buf, uint32_t row_offset, uint32_t nb) |
|
|
|
{ |
|
|
|
int res; |
|
|
|
struct samd_info *chip = (struct samd_info *)bank->driver_priv; |
|
|
|
uint32_t row_size = chip->page_size * 4; |
|
|
|
uint8_t *rb = malloc(row_size); |
|
|
|
if (!rb) |
|
|
|
return ERROR_FAIL; |
|
|
|
|
|
|
|
assert(row_offset + nb < row_size); |
|
|
|
assert((address % row_size) == 0); |
|
|
|
|
|
|
|
/* Retrieve the full row contents from Flash */ |
|
|
|
res = target_read_memory(bank->target, address, 4, row_size / 4, rb); |
|
|
|
if (res != ERROR_OK) { |
|
|
|
free(rb); |
|
|
|
return res; |
|
|
|
} |
|
|
|
|
|
|
|
/* Insert our partial row over the data from Flash */ |
|
|
|
memcpy(rb + (row_offset % row_size), buf, nb); |
|
|
|
|
|
|
|
/* Write the row back out */ |
|
|
|
res = samd_write_row(bank, address, rb); |
|
|
|
free(rb); |
|
|
|
|
|
|
|
return res; |
|
|
|
} |
|
|
|
|
|
|
|
static int samd_write(struct flash_bank *bank, uint8_t *buffer, |
|
|
|
uint32_t offset, uint32_t count) |
|
|
|
{ |
|
|
|
int res; |
|
|
|
uint32_t address; |
|
|
|
uint32_t nb = 0; |
|
|
|
struct samd_info *chip = (struct samd_info *)bank->driver_priv; |
|
|
|
uint32_t row_size = chip->page_size * 4; |
|
|
|
|
|
|
|
if (bank->target->state != TARGET_HALTED) { |
|
|
|
LOG_ERROR("Target not halted"); |
|
|
|
|
|
|
|
return ERROR_TARGET_NOT_HALTED; |
|
|
|
} |
|
|
|
|
|
|
|
if (!chip->probed) { |
|
|
|
if (samd_probe(bank) != ERROR_OK) |
|
|
|
return ERROR_FLASH_BANK_NOT_PROBED; |
|
|
|
} |
|
|
|
|
|
|
|
if (offset % row_size) { |
|
|
|
/* We're starting at an unaligned offset so we'll write a partial row |
|
|
|
* comprising that offset and up to the end of that row. */ |
|
|
|
nb = row_size - (offset % row_size); |
|
|
|
if (nb > count) |
|
|
|
nb = count; |
|
|
|
} else if (count < row_size) { |
|
|
|
/* We're writing an aligned but partial row. */ |
|
|
|
nb = count; |
|
|
|
} |
|
|
|
|
|
|
|
address = (offset / row_size) * row_size + bank->base; |
|
|
|
|
|
|
|
if (nb > 0) { |
|
|
|
res = samd_write_row_partial(bank, address, buffer, |
|
|
|
offset % row_size, nb); |
|
|
|
if (res != ERROR_OK) |
|
|
|
return res; |
|
|
|
|
|
|
|
/* We're done with the row contents */ |
|
|
|
count -= nb; |
|
|
|
offset += nb; |
|
|
|
buffer += row_size; |
|
|
|
} |
|
|
|
|
|
|
|
/* There's at least one aligned row to write out. */ |
|
|
|
if (count >= row_size) { |
|
|
|
int nr = count / row_size + ((count % row_size) ? 1 : 0); |
|
|
|
unsigned int r = 0; |
|
|
|
|
|
|
|
for (unsigned int i = address / row_size; |
|
|
|
(i < (address / row_size) + nr) && count > 0; i++) { |
|
|
|
address = (i * row_size) + bank->base; |
|
|
|
|
|
|
|
if (count >= row_size) { |
|
|
|
res = samd_write_row(bank, address, buffer + (r * row_size)); |
|
|
|
/* Advance one row */ |
|
|
|
offset += row_size; |
|
|
|
count -= row_size; |
|
|
|
} else { |
|
|
|
res = samd_write_row_partial(bank, address, |
|
|
|
buffer + (r * row_size), 0, count); |
|
|
|
/* We're done after this. */ |
|
|
|
offset += count; |
|
|
|
count = 0; |
|
|
|
} |
|
|
|
|
|
|
|
r++; |
|
|
|
|
|
|
|
if (res != ERROR_OK) |
|
|
|
return res; |
|
|
|
} |
|
|
|
} |
|
|
|
|
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command) |
|
|
|
{ |
|
|
|
struct samd_info *chip = samd_chips; |
|
|
|
|
|
|
|
while (chip) { |
|
|
|
if (chip->target == bank->target) |
|
|
|
break; |
|
|
|
chip = chip->next; |
|
|
|
} |
|
|
|
|
|
|
|
if (!chip) { |
|
|
|
/* Create a new chip */ |
|
|
|
chip = calloc(1, sizeof(*chip)); |
|
|
|
if (!chip) |
|
|
|
return ERROR_FAIL; |
|
|
|
|
|
|
|
chip->target = bank->target; |
|
|
|
chip->probed = false; |
|
|
|
|
|
|
|
bank->driver_priv = chip; |
|
|
|
|
|
|
|
/* Insert it into the chips list (at head) */ |
|
|
|
chip->next = samd_chips; |
|
|
|
samd_chips = chip; |
|
|
|
} |
|
|
|
|
|
|
|
if (bank->base != SAMD_FLASH) { |
|
|
|
LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32 |
|
|
|
"[at91samd series] )", |
|
|
|
bank->base, SAMD_FLASH); |
|
|
|
return ERROR_FAIL; |
|
|
|
} |
|
|
|
|
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
COMMAND_HANDLER(samd_handle_info_command) |
|
|
|
{ |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
static const struct command_registration at91samd_exec_command_handlers[] = { |
|
|
|
{ |
|
|
|
.name = "info", |
|
|
|
.handler = samd_handle_info_command, |
|
|
|
.mode = COMMAND_EXEC, |
|
|
|
.help = "Print information about the current at91samd chip" |
|
|
|
"and its flash configuration.", |
|
|
|
}, |
|
|
|
COMMAND_REGISTRATION_DONE |
|
|
|
}; |
|
|
|
|
|
|
|
static const struct command_registration at91samd_command_handlers[] = { |
|
|
|
{ |
|
|
|
.name = "at91samd", |
|
|
|
.mode = COMMAND_ANY, |
|
|
|
.help = "at91samd flash command group", |
|
|
|
.usage = "", |
|
|
|
.chain = at91samd_exec_command_handlers, |
|
|
|
}, |
|
|
|
COMMAND_REGISTRATION_DONE |
|
|
|
}; |
|
|
|
|
|
|
|
struct flash_driver at91samd_flash = { |
|
|
|
.name = "at91samd", |
|
|
|
.commands = at91samd_command_handlers, |
|
|
|
.flash_bank_command = samd_flash_bank_command, |
|
|
|
.erase = samd_erase, |
|
|
|
.protect = samd_protect, |
|
|
|
.write = samd_write, |
|
|
|
.read = default_flash_read, |
|
|
|
.probe = samd_probe, |
|
|
|
.auto_probe = samd_probe, |
|
|
|
.erase_check = default_flash_blank_check, |
|
|
|
.protect_check = samd_protect_check, |
|
|
|
}; |