- reformat spaces from non_cfi.[ch] git-svn-id: svn://svn.berlios.de/openocd/trunk@843 b42882b7-edfa-0310-969c-e2dbd0fdcd60tags/v0.1.0
@@ -179,29 +179,29 @@ non_cfi_t non_cfi_flashes[] = { | |||
.num_erase_regions = 4, | |||
.erase_region_info = | |||
{ | |||
0x00400000, /* 1x 16KB */ | |||
0x00200001, /* 2x 8KB */ | |||
0x00800000, /* 1x 32KB */ | |||
0x0100000e, /* 15x 64KB */ | |||
0x00400000, /* 1x 16KB */ | |||
0x00200001, /* 2x 8KB */ | |||
0x00800000, /* 1x 32KB */ | |||
0x0100000e, /* 15x 64KB */ | |||
0x00000000 | |||
} | |||
}, | |||
{ | |||
.mfr = CFI_MFR_AMIC, | |||
.id = 0xb31a, /* A29L800A */ | |||
.id = 0xb31a, /* A29L800A */ | |||
.pri_id = 0x02, | |||
.dev_size = 0x14, | |||
.interface_desc = 0x2, | |||
.max_buf_write_size = 0x0, | |||
.num_erase_regions = 4, | |||
.erase_region_info = | |||
.dev_size = 0x14, | |||
.interface_desc = 0x2, | |||
.max_buf_write_size = 0x0, | |||
.num_erase_regions = 4, | |||
.erase_region_info = | |||
{ | |||
0x00400000, /* 1x 16KB */ | |||
0x00200001, /* 2x 8KB */ | |||
0x00800000, /* 1x 32KB */ | |||
0x0100000e, /* 15x 64KB */ | |||
0x00400000, /* 1x 16KB */ | |||
0x00200001, /* 2x 8KB */ | |||
0x00800000, /* 1x 32KB */ | |||
0x0100000e, /* 15x 64KB */ | |||
0x00000000 | |||
} | |||
} | |||
}, | |||
{ | |||
.mfr = 0, | |||
@@ -288,5 +288,3 @@ void cfi_fixup_non_cfi(flash_bank_t *bank, void *param) | |||
exit(-1); | |||
} | |||
} | |||
@@ -38,4 +38,3 @@ extern non_cfi_t non_cfi_flashes[]; | |||
extern void cfi_fixup_non_cfi(flash_bank_t *bank, void *param); | |||
#endif /* NON_CFI_H */ | |||
@@ -1,7 +1,7 @@ | |||
source [find tcl/bitsbytes.tcl] | |||
source [find tcl/cpu/arm/cortex_m3.tcl] | |||
source [find tcl/memory.tcl] | |||
source [find tcl/mmr_helpers.tcl] | |||
source [find tcl/chip/st/stm32/stm32_regs.tcl] | |||
source [find tcl/chip/st/stm32/stm32_rcc.tcl] | |||
source [find tcl/bitsbytes.tcl] | |||
source [find tcl/cpu/arm/cortex_m3.tcl] | |||
source [find tcl/memory.tcl] | |||
source [find tcl/mmr_helpers.tcl] | |||
source [find tcl/chip/st/stm32/stm32_regs.tcl] | |||
source [find tcl/chip/st/stm32/stm32_rcc.tcl] |
@@ -1,290 +1,290 @@ | |||
set RCC_CR [expr $RCC_BASE + 0x00] | |||
set RCC_CFGR [expr $RCC_BASE + 0x04] | |||
set RCC_CIR [expr $RCC_BASE + 0x08] | |||
set RCC_APB2RSTR [expr $RCC_BASE + 0x0c] | |||
set RCC_APB1RSTR [expr $RCC_BASE + 0x10] | |||
set RCC_AHBENR [expr $RCC_BASE + 0x14] | |||
set RCC_APB2ENR [expr $RCC_BASE + 0x18] | |||
set RCC_APB1ENR [expr $RCC_BASE + 0x1c] | |||
set RCC_BDCR [expr $RCC_BASE + 0x20] | |||
set RCC_CSR [expr $RCC_BASE + 0x24] | |||
proc show_RCC_CR { } { | |||
if [ catch { set val [show_mmr32_reg RCC_CR] } msg ] { | |||
error $msg | |||
} | |||
show_mmr_bitfield 0 0 $val HSI { OFF ON } | |||
show_mmr_bitfield 1 1 $val HSIRDY { NOTRDY RDY } | |||
show_mmr_bitfield 7 3 $val HSITRIM { _NUMBER_ } | |||
show_mmr_bitfield 15 8 $val HSICAL { _NUMBER_ } | |||
show_mmr_bitfield 16 16 $val HSEON { OFF ON } | |||
show_mmr_bitfield 17 17 $val HSERDY { NOTRDY RDY } | |||
show_mmr_bitfield 18 18 $val HSEBYP { NOTBYPASSED BYPASSED } | |||
show_mmr_bitfield 19 19 $val CSSON { OFF ON } | |||
show_mmr_bitfield 24 24 $val PLLON { OFF ON } | |||
show_mmr_bitfield 25 25 $val PLLRDY { NOTRDY RDY } | |||
} | |||
proc show_RCC_CFGR { } { | |||
if [ catch { set val [show_mmr32_reg RCC_CFGR] } msg ] { | |||
error $msg | |||
} | |||
show_mmr_bitfield 1 0 $val SW { HSI HSE PLL ILLEGAL } | |||
show_mmr_bitfield 3 2 $val SWS { HSI HSE PLL ILLEGAL } | |||
show_mmr_bitfield 7 4 $val HPRE { sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_2 sysclk_div_4 sysclk_div_8 sysclk_div_16 sysclk_div_64 sysclk_div_128 sysclk_div_256 sysclk_div_512 } | |||
show_mmr_bitfield 10 8 $val PPRE1 { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 } | |||
show_mmr_bitfield 13 11 $val PPRE2 { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 } | |||
show_mmr_bitfield 15 14 $val ADCPRE { pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div2 pclk2_div4 pclk2_div8 pclk2_div16 } | |||
show_mmr_bitfield 16 16 $val PLLSRC { HSI_div_2 HSE } | |||
show_mmr_bitfield 17 17 $val PLLXTPRE { hse_div1 hse_div2 } | |||
show_mmr_bitfield 21 18 $val PLLMUL { x2 x3 x4 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x16 } | |||
show_mmr_bitfield 22 22 $val USBPRE { div1 div1_5 } | |||
show_mmr_bitfield 26 24 $val MCO { none none none none SysClk HSI HSE PLL_div2 } | |||
} | |||
proc show_RCC_CIR { } { | |||
if [ catch { set val [show_mmr32_reg RCC_CIR] } msg ] { | |||
error $msg | |||
} | |||
} | |||
proc show_RCC_APB2RSTR { } { | |||
if [ catch { set val [ show_mmr32_reg RCC_APB2RSTR] } msg ] { | |||
error $msg | |||
} | |||
for { set x 0 } { $x < 32 } { incr x } { | |||
set bits($x) xxx | |||
} | |||
set bits(15) adc3 | |||
set bits(14) usart1 | |||
set bits(13) tim8 | |||
set bits(12) spi1 | |||
set bits(11) tim1 | |||
set bits(10) adc2 | |||
set bits(9) adc1 | |||
set bits(8) iopg | |||
set bits(7) iopf | |||
set bits(6) iope | |||
set bits(5) iopd | |||
set bits(4) iopc | |||
set bits(3) iopb | |||
set bits(2) iopa | |||
set bits(1) xxx | |||
set bits(0) afio | |||
show_mmr32_bits bits $val | |||
} | |||
proc show_RCC_APB1RSTR { } { | |||
if [ catch { set val [ show_mmr32_reg RCC_APB1RSTR] } msg ] { | |||
error $msg | |||
} | |||
set bits(31) xxx | |||
set bits(30) xxx | |||
set bits(29) dac | |||
set bits(28) pwr | |||
set bits(27) bkp | |||
set bits(26) xxx | |||
set bits(25) can | |||
set bits(24) xxx | |||
set bits(23) usb | |||
set bits(22) i2c2 | |||
set bits(21) i2c1 | |||
set bits(20) uart5 | |||
set bits(19) uart4 | |||
set bits(18) uart3 | |||
set bits(17) uart2 | |||
set bits(16) xxx | |||
set bits(15) spi3 | |||
set bits(14) spi2 | |||
set bits(13) xxx | |||
set bits(12) xxx | |||
set bits(11) wwdg | |||
set bits(10) xxx | |||
set bits(9) xxx | |||
set bits(8) xxx | |||
set bits(7) xxx | |||
set bits(6) xxx | |||
set bits(5) tim7 | |||
set bits(4) tim6 | |||
set bits(3) tim5 | |||
set bits(2) tim4 | |||
set bits(1) tim3 | |||
set bits(0) tim2 | |||
show_mmr32_bits bits $val | |||
} | |||
proc show_RCC_AHBENR { } { | |||
if [ catch { set val [ show_mmr32_reg RCC_AHBENR ] } msg ] { | |||
error $msg | |||
} | |||
set bits(31) xxx | |||
set bits(30) xxx | |||
set bits(29) xxx | |||
set bits(28) xxx | |||
set bits(27) xxx | |||
set bits(26) xxx | |||
set bits(25) xxx | |||
set bits(24) xxx | |||
set bits(23) xxx | |||
set bits(22) xxx | |||
set bits(21) xxx | |||
set bits(20) xxx | |||
set bits(19) xxx | |||
set bits(18) xxx | |||
set bits(17) xxx | |||
set bits(16) xxx | |||
set bits(15) xxx | |||
set bits(14) xxx | |||
set bits(13) xxx | |||
set bits(12) xxx | |||
set bits(11) xxx | |||
set bits(10) sdio | |||
set bits(9) xxx | |||
set bits(8) fsmc | |||
set bits(7) xxx | |||
set bits(6) crce | |||
set bits(5) xxx | |||
set bits(4) flitf | |||
set bits(3) xxx | |||
set bits(2) sram | |||
set bits(1) dma2 | |||
set bits(0) dma1 | |||
show_mmr32_bits bits $val | |||
} | |||
proc show_RCC_APB2ENR { } { | |||
if [ catch { set val [ show_mmr32_reg RCC_APB2ENR ] } msg ] { | |||
error $msg | |||
} | |||
set bits(31) xxx | |||
set bits(30) xxx | |||
set bits(29) xxx | |||
set bits(28) xxx | |||
set bits(27) xxx | |||
set bits(26) xxx | |||
set bits(25) xxx | |||
set bits(24) xxx | |||
set bits(23) xxx | |||
set bits(22) xxx | |||
set bits(21) xxx | |||
set bits(20) xxx | |||
set bits(19) xxx | |||
set bits(18) xxx | |||
set bits(17) xxx | |||
set bits(16) xxx | |||
set bits(15) adc3 | |||
set bits(14) usart1 | |||
set bits(13) tim8 | |||
set bits(12) spi1 | |||
set bits(11) tim1 | |||
set bits(10) adc2 | |||
set bits(9) adc1 | |||
set bits(8) iopg | |||
set bits(7) iopf | |||
set bits(6) iope | |||
set bits(5) iopd | |||
set bits(4) iopc | |||
set bits(3) iopb | |||
set bits(2) iopa | |||
set bits(1) xxx | |||
set bits(0) afio | |||
show_mmr32_bits bits $val | |||
} | |||
proc show_RCC_APB1ENR { } { | |||
if [ catch { set val [ show_mmr32_reg RCC_APB1ENR ] } msg ] { | |||
error $msg | |||
} | |||
set bits(31) xxx | |||
set bits(30) xxx | |||
set bits(29) dac | |||
set bits(28) pwr | |||
set bits(27) bkp | |||
set bits(26) xxx | |||
set bits(25) can | |||
set bits(24) xxx | |||
set bits(23) usb | |||
set bits(22) i2c2 | |||
set bits(21) i2c1 | |||
set bits(20) usart5 | |||
set bits(19) usart4 | |||
set bits(18) usart3 | |||
set bits(17) usart2 | |||
set bits(16) xxx | |||
set bits(15) spi3 | |||
set bits(14) spi2 | |||
set bits(13) xxx | |||
set bits(12) xxx | |||
set bits(11) wwdg | |||
set bits(10) xxx | |||
set bits(9) xxx | |||
set bits(8) xxx | |||
set bits(7) xxx | |||
set bits(6) xxx | |||
set bits(5) tim7 | |||
set bits(4) tim6 | |||
set bits(3) tim5 | |||
set bits(2) tim4 | |||
set bits(1) tim3 | |||
set bits(0) tim2 | |||
show_mmr32_bits bits $val | |||
} | |||
proc show_RCC_BDCR { } { | |||
if [ catch { set val [ show_mmr32_reg RCC_BDCR ] } msg ] { | |||
error $msg | |||
} | |||
for { set x 0 } { $x < 32 } { incr x } { | |||
set bits($x) xxx | |||
} | |||
set bits(0) lseon | |||
set bits(1) lserdy | |||
set bits(2) lsebyp | |||
set bits(8) rtcsel0 | |||
set bits(9) rtcsel1 | |||
set bits(15) rtcen | |||
set bits(16) bdrst | |||
show_mmr32_bits bits $val | |||
} | |||
proc show_RCC_CSR { } { | |||
if [ catch { set val [ show_mmr32_reg RCC_CSR ] } msg ] { | |||
error $msg | |||
} | |||
for { set x 0 } { $x < 32 } { incr x } { | |||
set bits($x) xxx | |||
} | |||
set bits(0) lsion | |||
set bits(1) lsirdy | |||
set bits(24) rmvf | |||
set bits(26) pin | |||
set bits(27) por | |||
set bits(28) sft | |||
set bits(29) iwdg | |||
set bits(30) wwdg | |||
set bits(31) lpwr | |||
show_mmr32_bits bits $val | |||
} | |||
proc show_RCC { } { | |||
show_RCC_CR | |||
show_RCC_CFGR | |||
show_RCC_CIR | |||
show_RCC_APB2RSTR | |||
show_RCC_APB1RSTR | |||
show_RCC_AHBENR | |||
show_RCC_APB2ENR | |||
show_RCC_APB1ENR | |||
show_RCC_BDCR | |||
show_RCC_CSR | |||
} | |||
set RCC_CR [expr $RCC_BASE + 0x00] | |||
set RCC_CFGR [expr $RCC_BASE + 0x04] | |||
set RCC_CIR [expr $RCC_BASE + 0x08] | |||
set RCC_APB2RSTR [expr $RCC_BASE + 0x0c] | |||
set RCC_APB1RSTR [expr $RCC_BASE + 0x10] | |||
set RCC_AHBENR [expr $RCC_BASE + 0x14] | |||
set RCC_APB2ENR [expr $RCC_BASE + 0x18] | |||
set RCC_APB1ENR [expr $RCC_BASE + 0x1c] | |||
set RCC_BDCR [expr $RCC_BASE + 0x20] | |||
set RCC_CSR [expr $RCC_BASE + 0x24] | |||
proc show_RCC_CR { } { | |||
if [ catch { set val [show_mmr32_reg RCC_CR] } msg ] { | |||
error $msg | |||
} | |||
show_mmr_bitfield 0 0 $val HSI { OFF ON } | |||
show_mmr_bitfield 1 1 $val HSIRDY { NOTRDY RDY } | |||
show_mmr_bitfield 7 3 $val HSITRIM { _NUMBER_ } | |||
show_mmr_bitfield 15 8 $val HSICAL { _NUMBER_ } | |||
show_mmr_bitfield 16 16 $val HSEON { OFF ON } | |||
show_mmr_bitfield 17 17 $val HSERDY { NOTRDY RDY } | |||
show_mmr_bitfield 18 18 $val HSEBYP { NOTBYPASSED BYPASSED } | |||
show_mmr_bitfield 19 19 $val CSSON { OFF ON } | |||
show_mmr_bitfield 24 24 $val PLLON { OFF ON } | |||
show_mmr_bitfield 25 25 $val PLLRDY { NOTRDY RDY } | |||
} | |||
proc show_RCC_CFGR { } { | |||
if [ catch { set val [show_mmr32_reg RCC_CFGR] } msg ] { | |||
error $msg | |||
} | |||
show_mmr_bitfield 1 0 $val SW { HSI HSE PLL ILLEGAL } | |||
show_mmr_bitfield 3 2 $val SWS { HSI HSE PLL ILLEGAL } | |||
show_mmr_bitfield 7 4 $val HPRE { sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_2 sysclk_div_4 sysclk_div_8 sysclk_div_16 sysclk_div_64 sysclk_div_128 sysclk_div_256 sysclk_div_512 } | |||
show_mmr_bitfield 10 8 $val PPRE1 { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 } | |||
show_mmr_bitfield 13 11 $val PPRE2 { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 } | |||
show_mmr_bitfield 15 14 $val ADCPRE { pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div2 pclk2_div4 pclk2_div8 pclk2_div16 } | |||
show_mmr_bitfield 16 16 $val PLLSRC { HSI_div_2 HSE } | |||
show_mmr_bitfield 17 17 $val PLLXTPRE { hse_div1 hse_div2 } | |||
show_mmr_bitfield 21 18 $val PLLMUL { x2 x3 x4 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x16 } | |||
show_mmr_bitfield 22 22 $val USBPRE { div1 div1_5 } | |||
show_mmr_bitfield 26 24 $val MCO { none none none none SysClk HSI HSE PLL_div2 } | |||
} | |||
proc show_RCC_CIR { } { | |||
if [ catch { set val [show_mmr32_reg RCC_CIR] } msg ] { | |||
error $msg | |||
} | |||
} | |||
proc show_RCC_APB2RSTR { } { | |||
if [ catch { set val [ show_mmr32_reg RCC_APB2RSTR] } msg ] { | |||
error $msg | |||
} | |||
for { set x 0 } { $x < 32 } { incr x } { | |||
set bits($x) xxx | |||
} | |||
set bits(15) adc3 | |||
set bits(14) usart1 | |||
set bits(13) tim8 | |||
set bits(12) spi1 | |||
set bits(11) tim1 | |||
set bits(10) adc2 | |||
set bits(9) adc1 | |||
set bits(8) iopg | |||
set bits(7) iopf | |||
set bits(6) iope | |||
set bits(5) iopd | |||
set bits(4) iopc | |||
set bits(3) iopb | |||
set bits(2) iopa | |||
set bits(1) xxx | |||
set bits(0) afio | |||
show_mmr32_bits bits $val | |||
} | |||
proc show_RCC_APB1RSTR { } { | |||
if [ catch { set val [ show_mmr32_reg RCC_APB1RSTR] } msg ] { | |||
error $msg | |||
} | |||
set bits(31) xxx | |||
set bits(30) xxx | |||
set bits(29) dac | |||
set bits(28) pwr | |||
set bits(27) bkp | |||
set bits(26) xxx | |||
set bits(25) can | |||
set bits(24) xxx | |||
set bits(23) usb | |||
set bits(22) i2c2 | |||
set bits(21) i2c1 | |||
set bits(20) uart5 | |||
set bits(19) uart4 | |||
set bits(18) uart3 | |||
set bits(17) uart2 | |||
set bits(16) xxx | |||
set bits(15) spi3 | |||
set bits(14) spi2 | |||
set bits(13) xxx | |||
set bits(12) xxx | |||
set bits(11) wwdg | |||
set bits(10) xxx | |||
set bits(9) xxx | |||
set bits(8) xxx | |||
set bits(7) xxx | |||
set bits(6) xxx | |||
set bits(5) tim7 | |||
set bits(4) tim6 | |||
set bits(3) tim5 | |||
set bits(2) tim4 | |||
set bits(1) tim3 | |||
set bits(0) tim2 | |||
show_mmr32_bits bits $val | |||
} | |||
proc show_RCC_AHBENR { } { | |||
if [ catch { set val [ show_mmr32_reg RCC_AHBENR ] } msg ] { | |||
error $msg | |||
} | |||
set bits(31) xxx | |||
set bits(30) xxx | |||
set bits(29) xxx | |||
set bits(28) xxx | |||
set bits(27) xxx | |||
set bits(26) xxx | |||
set bits(25) xxx | |||
set bits(24) xxx | |||
set bits(23) xxx | |||
set bits(22) xxx | |||
set bits(21) xxx | |||
set bits(20) xxx | |||
set bits(19) xxx | |||
set bits(18) xxx | |||
set bits(17) xxx | |||
set bits(16) xxx | |||
set bits(15) xxx | |||
set bits(14) xxx | |||
set bits(13) xxx | |||
set bits(12) xxx | |||
set bits(11) xxx | |||
set bits(10) sdio | |||
set bits(9) xxx | |||
set bits(8) fsmc | |||
set bits(7) xxx | |||
set bits(6) crce | |||
set bits(5) xxx | |||
set bits(4) flitf | |||
set bits(3) xxx | |||
set bits(2) sram | |||
set bits(1) dma2 | |||
set bits(0) dma1 | |||
show_mmr32_bits bits $val | |||
} | |||
proc show_RCC_APB2ENR { } { | |||
if [ catch { set val [ show_mmr32_reg RCC_APB2ENR ] } msg ] { | |||
error $msg | |||
} | |||
set bits(31) xxx | |||
set bits(30) xxx | |||
set bits(29) xxx | |||
set bits(28) xxx | |||
set bits(27) xxx | |||
set bits(26) xxx | |||
set bits(25) xxx | |||
set bits(24) xxx | |||
set bits(23) xxx | |||
set bits(22) xxx | |||
set bits(21) xxx | |||
set bits(20) xxx | |||
set bits(19) xxx | |||
set bits(18) xxx | |||
set bits(17) xxx | |||
set bits(16) xxx | |||
set bits(15) adc3 | |||
set bits(14) usart1 | |||
set bits(13) tim8 | |||
set bits(12) spi1 | |||
set bits(11) tim1 | |||
set bits(10) adc2 | |||
set bits(9) adc1 | |||
set bits(8) iopg | |||
set bits(7) iopf | |||
set bits(6) iope | |||
set bits(5) iopd | |||
set bits(4) iopc | |||
set bits(3) iopb | |||
set bits(2) iopa | |||
set bits(1) xxx | |||
set bits(0) afio | |||
show_mmr32_bits bits $val | |||
} | |||
proc show_RCC_APB1ENR { } { | |||
if [ catch { set val [ show_mmr32_reg RCC_APB1ENR ] } msg ] { | |||
error $msg | |||
} | |||
set bits(31) xxx | |||
set bits(30) xxx | |||
set bits(29) dac | |||
set bits(28) pwr | |||
set bits(27) bkp | |||
set bits(26) xxx | |||
set bits(25) can | |||
set bits(24) xxx | |||
set bits(23) usb | |||
set bits(22) i2c2 | |||
set bits(21) i2c1 | |||
set bits(20) usart5 | |||
set bits(19) usart4 | |||
set bits(18) usart3 | |||
set bits(17) usart2 | |||
set bits(16) xxx | |||
set bits(15) spi3 | |||
set bits(14) spi2 | |||
set bits(13) xxx | |||
set bits(12) xxx | |||
set bits(11) wwdg | |||
set bits(10) xxx | |||
set bits(9) xxx | |||
set bits(8) xxx | |||
set bits(7) xxx | |||
set bits(6) xxx | |||
set bits(5) tim7 | |||
set bits(4) tim6 | |||
set bits(3) tim5 | |||
set bits(2) tim4 | |||
set bits(1) tim3 | |||
set bits(0) tim2 | |||
show_mmr32_bits bits $val | |||
} | |||
proc show_RCC_BDCR { } { | |||
if [ catch { set val [ show_mmr32_reg RCC_BDCR ] } msg ] { | |||
error $msg | |||
} | |||
for { set x 0 } { $x < 32 } { incr x } { | |||
set bits($x) xxx | |||
} | |||
set bits(0) lseon | |||
set bits(1) lserdy | |||
set bits(2) lsebyp | |||
set bits(8) rtcsel0 | |||
set bits(9) rtcsel1 | |||
set bits(15) rtcen | |||
set bits(16) bdrst | |||
show_mmr32_bits bits $val | |||
} | |||
proc show_RCC_CSR { } { | |||
if [ catch { set val [ show_mmr32_reg RCC_CSR ] } msg ] { | |||
error $msg | |||
} | |||
for { set x 0 } { $x < 32 } { incr x } { | |||
set bits($x) xxx | |||
} | |||
set bits(0) lsion | |||
set bits(1) lsirdy | |||
set bits(24) rmvf | |||
set bits(26) pin | |||
set bits(27) por | |||
set bits(28) sft | |||
set bits(29) iwdg | |||
set bits(30) wwdg | |||
set bits(31) lpwr | |||
show_mmr32_bits bits $val | |||
} | |||
proc show_RCC { } { | |||
show_RCC_CR | |||
show_RCC_CFGR | |||
show_RCC_CIR | |||
show_RCC_APB2RSTR | |||
show_RCC_APB1RSTR | |||
show_RCC_AHBENR | |||
show_RCC_APB2ENR | |||
show_RCC_APB1ENR | |||
show_RCC_BDCR | |||
show_RCC_CSR | |||
} |
@@ -1,95 +1,95 @@ | |||
# /* Peripheral and SRAM base address in the alias region */ | |||
set PERIPH_BB_BASE 0x42000000 | |||
set SRAM_BB_BASE 0x22000000 | |||
# /*Peripheral and SRAM base address in the bit-band region */ | |||
set SRAM_BASE 0x20000000 | |||
set PERIPH_BASE 0x40000000 | |||
# /*FSMC registers base address */ | |||
set FSMC_R_BASE 0xA0000000 | |||
# /*Peripheral memory map */ | |||
set APB1PERIPH_BASE [set PERIPH_BASE] | |||
set APB2PERIPH_BASE [expr $PERIPH_BASE + 0x10000] | |||
set AHBPERIPH_BASE [expr $PERIPH_BASE + 0x20000] | |||
set TIM2_BASE [expr $APB1PERIPH_BASE + 0x0000] | |||
set TIM3_BASE [expr $APB1PERIPH_BASE + 0x0400] | |||
set TIM4_BASE [expr $APB1PERIPH_BASE + 0x0800] | |||
set TIM5_BASE [expr $APB1PERIPH_BASE + 0x0C00] | |||
set TIM6_BASE [expr $APB1PERIPH_BASE + 0x1000] | |||
set TIM7_BASE [expr $APB1PERIPH_BASE + 0x1400] | |||
set RTC_BASE [expr $APB1PERIPH_BASE + 0x2800] | |||
set WWDG_BASE [expr $APB1PERIPH_BASE + 0x2C00] | |||
set IWDG_BASE [expr $APB1PERIPH_BASE + 0x3000] | |||
set SPI2_BASE [expr $APB1PERIPH_BASE + 0x3800] | |||
set SPI3_BASE [expr $APB1PERIPH_BASE + 0x3C00] | |||
set USART2_BASE [expr $APB1PERIPH_BASE + 0x4400] | |||
set USART3_BASE [expr $APB1PERIPH_BASE + 0x4800] | |||
set UART4_BASE [expr $APB1PERIPH_BASE + 0x4C00] | |||
set UART5_BASE [expr $APB1PERIPH_BASE + 0x5000] | |||
set I2C1_BASE [expr $APB1PERIPH_BASE + 0x5400] | |||
set I2C2_BASE [expr $APB1PERIPH_BASE + 0x5800] | |||
set CAN_BASE [expr $APB1PERIPH_BASE + 0x6400] | |||
set BKP_BASE [expr $APB1PERIPH_BASE + 0x6C00] | |||
set PWR_BASE [expr $APB1PERIPH_BASE + 0x7000] | |||
set DAC_BASE [expr $APB1PERIPH_BASE + 0x7400] | |||
set AFIO_BASE [expr $APB2PERIPH_BASE + 0x0000] | |||
set EXTI_BASE [expr $APB2PERIPH_BASE + 0x0400] | |||
set GPIOA_BASE [expr $APB2PERIPH_BASE + 0x0800] | |||
set GPIOB_BASE [expr $APB2PERIPH_BASE + 0x0C00] | |||
set GPIOC_BASE [expr $APB2PERIPH_BASE + 0x1000] | |||
set GPIOD_BASE [expr $APB2PERIPH_BASE + 0x1400] | |||
set GPIOE_BASE [expr $APB2PERIPH_BASE + 0x1800] | |||
set GPIOF_BASE [expr $APB2PERIPH_BASE + 0x1C00] | |||
set GPIOG_BASE [expr $APB2PERIPH_BASE + 0x2000] | |||
set ADC1_BASE [expr $APB2PERIPH_BASE + 0x2400] | |||
set ADC2_BASE [expr $APB2PERIPH_BASE + 0x2800] | |||
set TIM1_BASE [expr $APB2PERIPH_BASE + 0x2C00] | |||
set SPI1_BASE [expr $APB2PERIPH_BASE + 0x3000] | |||
set TIM8_BASE [expr $APB2PERIPH_BASE + 0x3400] | |||
set USART1_BASE [expr $APB2PERIPH_BASE + 0x3800] | |||
set ADC3_BASE [expr $APB2PERIPH_BASE + 0x3C00] | |||
set SDIO_BASE [expr $PERIPH_BASE + 0x18000] | |||
set DMA1_BASE [expr $AHBPERIPH_BASE + 0x0000] | |||
set DMA1_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0008] | |||
set DMA1_Channel2_BASE [expr $AHBPERIPH_BASE + 0x001C] | |||
set DMA1_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0030] | |||
set DMA1_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0044] | |||
set DMA1_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0058] | |||
set DMA1_Channel6_BASE [expr $AHBPERIPH_BASE + 0x006C] | |||
set DMA1_Channel7_BASE [expr $AHBPERIPH_BASE + 0x0080] | |||
set DMA2_BASE [expr $AHBPERIPH_BASE + 0x0400] | |||
set DMA2_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0408] | |||
set DMA2_Channel2_BASE [expr $AHBPERIPH_BASE + 0x041C] | |||
set DMA2_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0430] | |||
set DMA2_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0444] | |||
set DMA2_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0458] | |||
set RCC_BASE [expr $AHBPERIPH_BASE + 0x1000] | |||
set CRC_BASE [expr $AHBPERIPH_BASE + 0x3000] | |||
# /*Flash registers base address */ | |||
set FLASH_R_BASE [expr $AHBPERIPH_BASE + 0x2000] | |||
# /*Flash Option Bytes base address */ | |||
set OB_BASE 0x1FFFF800 | |||
# /*FSMC Bankx registers base address */ | |||
set FSMC_Bank1_R_BASE [expr $FSMC_R_BASE + 0x0000] | |||
set FSMC_Bank1E_R_BASE [expr $FSMC_R_BASE + 0x0104] | |||
set FSMC_Bank2_R_BASE [expr $FSMC_R_BASE + 0x0060] | |||
set FSMC_Bank3_R_BASE [expr $FSMC_R_BASE + 0x0080] | |||
set FSMC_Bank4_R_BASE [expr $FSMC_R_BASE + 0x00A0] | |||
# /*Debug MCU registers base address */ | |||
set DBGMCU_BASE 0xE0042000 | |||
# /*System Control Space memory map */ | |||
set SCS_BASE 0xE000E000 | |||
set SysTick_BASE [expr $SCS_BASE + 0x0010] | |||
set NVIC_BASE [expr $SCS_BASE + 0x0100] | |||
set SCB_BASE [expr $SCS_BASE + 0x0D00] | |||
# /* Peripheral and SRAM base address in the alias region */ | |||
set PERIPH_BB_BASE 0x42000000 | |||
set SRAM_BB_BASE 0x22000000 | |||
# /*Peripheral and SRAM base address in the bit-band region */ | |||
set SRAM_BASE 0x20000000 | |||
set PERIPH_BASE 0x40000000 | |||
# /*FSMC registers base address */ | |||
set FSMC_R_BASE 0xA0000000 | |||
# /*Peripheral memory map */ | |||
set APB1PERIPH_BASE [set PERIPH_BASE] | |||
set APB2PERIPH_BASE [expr $PERIPH_BASE + 0x10000] | |||
set AHBPERIPH_BASE [expr $PERIPH_BASE + 0x20000] | |||
set TIM2_BASE [expr $APB1PERIPH_BASE + 0x0000] | |||
set TIM3_BASE [expr $APB1PERIPH_BASE + 0x0400] | |||
set TIM4_BASE [expr $APB1PERIPH_BASE + 0x0800] | |||
set TIM5_BASE [expr $APB1PERIPH_BASE + 0x0C00] | |||
set TIM6_BASE [expr $APB1PERIPH_BASE + 0x1000] | |||
set TIM7_BASE [expr $APB1PERIPH_BASE + 0x1400] | |||
set RTC_BASE [expr $APB1PERIPH_BASE + 0x2800] | |||
set WWDG_BASE [expr $APB1PERIPH_BASE + 0x2C00] | |||
set IWDG_BASE [expr $APB1PERIPH_BASE + 0x3000] | |||
set SPI2_BASE [expr $APB1PERIPH_BASE + 0x3800] | |||
set SPI3_BASE [expr $APB1PERIPH_BASE + 0x3C00] | |||
set USART2_BASE [expr $APB1PERIPH_BASE + 0x4400] | |||
set USART3_BASE [expr $APB1PERIPH_BASE + 0x4800] | |||
set UART4_BASE [expr $APB1PERIPH_BASE + 0x4C00] | |||
set UART5_BASE [expr $APB1PERIPH_BASE + 0x5000] | |||
set I2C1_BASE [expr $APB1PERIPH_BASE + 0x5400] | |||
set I2C2_BASE [expr $APB1PERIPH_BASE + 0x5800] | |||
set CAN_BASE [expr $APB1PERIPH_BASE + 0x6400] | |||
set BKP_BASE [expr $APB1PERIPH_BASE + 0x6C00] | |||
set PWR_BASE [expr $APB1PERIPH_BASE + 0x7000] | |||
set DAC_BASE [expr $APB1PERIPH_BASE + 0x7400] | |||
set AFIO_BASE [expr $APB2PERIPH_BASE + 0x0000] | |||
set EXTI_BASE [expr $APB2PERIPH_BASE + 0x0400] | |||
set GPIOA_BASE [expr $APB2PERIPH_BASE + 0x0800] | |||
set GPIOB_BASE [expr $APB2PERIPH_BASE + 0x0C00] | |||
set GPIOC_BASE [expr $APB2PERIPH_BASE + 0x1000] | |||
set GPIOD_BASE [expr $APB2PERIPH_BASE + 0x1400] | |||
set GPIOE_BASE [expr $APB2PERIPH_BASE + 0x1800] | |||
set GPIOF_BASE [expr $APB2PERIPH_BASE + 0x1C00] | |||
set GPIOG_BASE [expr $APB2PERIPH_BASE + 0x2000] | |||
set ADC1_BASE [expr $APB2PERIPH_BASE + 0x2400] | |||
set ADC2_BASE [expr $APB2PERIPH_BASE + 0x2800] | |||
set TIM1_BASE [expr $APB2PERIPH_BASE + 0x2C00] | |||
set SPI1_BASE [expr $APB2PERIPH_BASE + 0x3000] | |||
set TIM8_BASE [expr $APB2PERIPH_BASE + 0x3400] | |||
set USART1_BASE [expr $APB2PERIPH_BASE + 0x3800] | |||
set ADC3_BASE [expr $APB2PERIPH_BASE + 0x3C00] | |||
set SDIO_BASE [expr $PERIPH_BASE + 0x18000] | |||
set DMA1_BASE [expr $AHBPERIPH_BASE + 0x0000] | |||
set DMA1_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0008] | |||
set DMA1_Channel2_BASE [expr $AHBPERIPH_BASE + 0x001C] | |||
set DMA1_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0030] | |||
set DMA1_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0044] | |||
set DMA1_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0058] | |||
set DMA1_Channel6_BASE [expr $AHBPERIPH_BASE + 0x006C] | |||
set DMA1_Channel7_BASE [expr $AHBPERIPH_BASE + 0x0080] | |||
set DMA2_BASE [expr $AHBPERIPH_BASE + 0x0400] | |||
set DMA2_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0408] | |||
set DMA2_Channel2_BASE [expr $AHBPERIPH_BASE + 0x041C] | |||
set DMA2_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0430] | |||
set DMA2_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0444] | |||
set DMA2_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0458] | |||
set RCC_BASE [expr $AHBPERIPH_BASE + 0x1000] | |||
set CRC_BASE [expr $AHBPERIPH_BASE + 0x3000] | |||
# /*Flash registers base address */ | |||
set FLASH_R_BASE [expr $AHBPERIPH_BASE + 0x2000] | |||
# /*Flash Option Bytes base address */ | |||
set OB_BASE 0x1FFFF800 | |||
# /*FSMC Bankx registers base address */ | |||
set FSMC_Bank1_R_BASE [expr $FSMC_R_BASE + 0x0000] | |||
set FSMC_Bank1E_R_BASE [expr $FSMC_R_BASE + 0x0104] | |||
set FSMC_Bank2_R_BASE [expr $FSMC_R_BASE + 0x0060] | |||
set FSMC_Bank3_R_BASE [expr $FSMC_R_BASE + 0x0080] | |||
set FSMC_Bank4_R_BASE [expr $FSMC_R_BASE + 0x00A0] | |||
# /*Debug MCU registers base address */ | |||
set DBGMCU_BASE 0xE0042000 | |||
# /*System Control Space memory map */ | |||
set SCS_BASE 0xE000E000 | |||
set SysTick_BASE [expr $SCS_BASE + 0x0010] | |||
set NVIC_BASE [expr $SCS_BASE + 0x0100] | |||
set SCB_BASE [expr $SCS_BASE + 0x0D00] |