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tcl: fix some minor typo

Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.
While there, fix one indentation.

Change-Id: I72369ed26f363bacd760b40b8c83dd95e89d28a4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6214
Tested-by: jenkins
jim
Antonio Borneo 1 year ago
parent
commit
2a1f3b2574
13 changed files with 18 additions and 18 deletions
  1. +1
    -1
      tcl/bitsbytes.tcl
  2. +1
    -1
      tcl/board/arm_evaluator7t.cfg
  3. +1
    -1
      tcl/board/at91sam9g20-ek.cfg
  4. +1
    -1
      tcl/board/digilent_atlys.cfg
  5. +1
    -1
      tcl/board/hitex_lpc2929.cfg
  6. +1
    -1
      tcl/board/mini2440.cfg
  7. +1
    -1
      tcl/board/uptech_2410.cfg
  8. +1
    -1
      tcl/interface/ftdi/swd-resistor-hack.cfg
  9. +3
    -3
      tcl/target/c100config.tcl
  10. +4
    -4
      tcl/target/c100helper.tcl
  11. +1
    -1
      tcl/target/davinci.cfg
  12. +1
    -1
      tcl/target/lpc8nxx.cfg
  13. +1
    -1
      tcl/target/psoc4.cfg

+ 1
- 1
tcl/bitsbytes.tcl View File

@@ -2,7 +2,7 @@
# Purpose - Create some $BIT variables
# Create $K and $M variables
# and some bit field extraction variables.
# Creat helper variables ...
# Create helper variables ...
# BIT0.. BIT31

for { set x 0 } { $x < 32 } { set x [expr {$x + 1}]} {


+ 1
- 1
tcl/board/arm_evaluator7t.cfg View File

@@ -5,5 +5,5 @@ source [find target/samsung_s3c4510.cfg]
#
# FIXME:
# Add (A) sdram configuration
# Add (B) flash cfi programing configuration
# Add (B) flash cfi programming configuration
#

+ 1
- 1
tcl/board/at91sam9g20-ek.cfg View File

@@ -153,7 +153,7 @@ proc at91sam9g20_reset_init { } {

nand probe nandflash_cs3

# The AT91SAM9G20-EK evaluation board has build-in serial data flash also.
# The AT91SAM9G20-EK evaluation board has built-in serial data flash also.

# Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations
# are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference


+ 1
- 1
tcl/board/digilent_atlys.cfg View File

@@ -5,7 +5,7 @@
# ID 1443:0007 Digilent Development board JTAG
#
# However, the ixo-usb-jtag project provides an alternative open firmware for
# the on board programmer. When using thie firmware the board will then
# the on board programmer. When using this firmware the board will then
# enumerate as:
# ID 16c0:06ad Van Ooijen Technische Informatica
# (With SerialNumber == hw_nexys)


+ 1
- 1
tcl/board/hitex_lpc2929.cfg View File

@@ -34,7 +34,7 @@ flash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe

$_TARGETNAME configure -event reset-init {
# Flash
mww 0x20200010 0x00000007 ;# FBWST: 7 wait states, not chached
mww 0x20200010 0x00000007 ;# FBWST: 7 wait states, not cached

# Use PLL
mww 0xFFFF8020 0x00000001 ;# XTAL_OSC_CONTROL: enable, 1-20 MHz


+ 1
- 1
tcl/board/mini2440.cfg View File

@@ -38,7 +38,7 @@
# it's apt-get install libusb-dev. When I made my config I only included
# --enable-jlink and --enable-usbdevs
#
# I HAVE NOT Tested this throughly, so there could still be problems.
# I HAVE NOT Tested this thoroughly, so there could still be problems.
# But it should get you way ahead of the game from where I started.
# If you find problems (and fixes) please post them to
# openocd-development@lists.berlios.de and join the developers and


+ 1
- 1
tcl/board/uptech_2410.cfg View File

@@ -1,5 +1,5 @@
# Target Configuration for the Uptech 2410 board.
# This configuration hould also work on smdk2410, but I havn't tested it yet.
# This configuration should also work on smdk2410, but I haven't tested it yet.
# Author: xionglingfeng@Gmail.com

source [find target/samsung_s3c2410.cfg]


+ 1
- 1
tcl/interface/ftdi/swd-resistor-hack.cfg View File

@@ -5,7 +5,7 @@
#
# You also need to have reliable GND connection between the target and
# adapter. Vref of the adapter should be supplied with a voltage equal
# to the target's (preferrably connect it to Vcc). You can also
# to the target's (preferably connect it to Vcc). You can also
# optionally connect nSRST. Leave everything else unconnected.
#
# FTDI Target


+ 3
- 3
tcl/target/c100config.tcl View File

@@ -43,7 +43,7 @@ proc setupTelo {} {

# setup GPIO used as control signals for C100
setupGPIO
# This will allow acces to lower 8MB or NOR
# This will allow access to lower 8MB or NOR
lowGPIO5
# setup NOR size,timing,etc.
setupNOR
@@ -79,7 +79,7 @@ proc setupNOR {} {
#mww $EX_CS0_TMG3_REG
# set EBUS clock 165/5=33MHz
mww $EX_CLOCK_DIV_REG 0x5
# everthing else is OK with default
# everything else is OK with default
}

proc bootNOR {} {
@@ -159,7 +159,7 @@ proc boardID {id} {
proc ooma_board_detect {} {
set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]

# read the current value of the BOOTSRAP pins
# read the current value of the BOOTSTRAP pins
set tmp [mrw $GPIO_BOOTSTRAP_REG]
echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
# extract the GPBP bits


+ 4
- 4
tcl/target/c100helper.tcl View File

@@ -13,16 +13,16 @@ proc helpC100 {} {
echo "10) showArmClk: will show current config registers for Arm Bus Clock"
echo "11) setupArmClk: will setup Amba Bus Clock=450MHz"
echo "12) ooma_board_detect: will show which version of Telo you have"
echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configureg"
echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configured"
echo "14) showDDR2: will show DDR2 config registers"
echo "15) showWatchdog: will show current register config for watchdog"
echo "16) reboot: will trigger watchdog and reboot Telo (hw reset)"
echo "17) bootNOR: will boot Telo from NOR"
echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be confiured"
echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be configured"
echo "19) putcUART0: will print a character on UART0"
echo "20) putsUART0: will print a string on UART0"
echo "21) trainDDR2: will run DDR2 training program"
echo "22) flashUBOOT: will prgram NOR sectors 0-3 with u-boot.bin"
echo "21) trainDDR2: will run DDR2 training program"
echo "22) flashUBOOT: will program NOR sectors 0-3 with u-boot.bin"
}

source [find mem_helper.tcl]


+ 1
- 1
tcl/target/davinci.cfg View File

@@ -267,7 +267,7 @@ proc pll_v03_setup {pll_addr mult config} {
if {$aln != 0} {
# clear pllcmd.GO
mww [expr {$pll_addr + 0x0138}] 0x00
# write alingment flags
# write alignment flags
mww [expr {$pll_addr + 0x0140}] $aln
# write pllcmd.GO; poll pllstat.GO
mww [expr {$pll_addr + 0x0138}] 0x01


+ 1
- 1
tcl/target/lpc8nxx.cfg View File

@@ -56,7 +56,7 @@ proc set_sysclk_500khz {} {
echo "Notice: sysclock set to 500kHz."
}

# Do not remap the ARM interrupt vectors to anything but the beginning ot the flash.
# Do not remap the ARM interrupt vectors to anything but the beginning of the flash.
# Table System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
# Bit Symbol Value Description
# 0 map - interrupt vector remap. 0 after boot.


+ 1
- 1
tcl/target/psoc4.cfg View File

@@ -60,7 +60,7 @@ adapter speed 1500
#
# Newer families like PSoC 4000, 4100M, 4200M, 4100L, 4200L and PSoC 4 BLE
# clear TEST_MODE flag during device reset so workaround is not possible.
# Use a KitProg adapter for theese devices or "reset halt" will not stop
# Use a KitProg adapter for these devices or "reset halt" will not stop
# before executing user code.
#
# 3) SWD cannot be connected during system initialization after reset.


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