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@@ -124,16 +124,20 @@ static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp, |
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if (retval != ERROR_OK) |
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return retval; |
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retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); |
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// XXX check retval |
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if (retval != ERROR_OK) |
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return retval; |
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/* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */ |
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retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); |
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if (retval != ERROR_OK) |
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return retval; |
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retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR); |
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// XXX check retval |
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if (retval != ERROR_OK) |
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return retval; |
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retval = dap_run(swjdp); |
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if (retval != ERROR_OK) |
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return retval; |
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/* restore DCB_DCRDR - this needs to be in a seperate |
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* transaction otherwise the emulated DCC channel breaks */ |
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