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@@ -54,7 +54,6 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11); |
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bool arm11_config_memwrite_burst = true; |
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bool arm11_config_memwrite_error_fatal = true; |
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uint32_t arm11_vcr = 0; |
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bool arm11_config_memrw_no_increment = false; |
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bool arm11_config_step_irq_enable = false; |
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bool arm11_config_hardware_step = false; |
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@@ -1284,8 +1283,13 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i |
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/* target memory access |
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* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit) |
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* count: number of items of <size> |
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* |
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* arm11_config_memrw_no_increment - in the future we may want to be able |
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* to read/write a range of data to a "port". a "port" is an action on |
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* read memory address for some peripheral. |
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*/ |
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int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) |
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int arm11_read_memory_inner(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer, |
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bool arm11_config_memrw_no_increment) |
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{ |
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/** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */ |
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int retval; |
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@@ -1371,7 +1375,18 @@ int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, |
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return arm11_run_instr_data_finish(arm11); |
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} |
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int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) |
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int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) |
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{ |
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return arm11_read_memory_inner(target, address, size, count, buffer, false); |
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} |
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/* |
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* arm11_config_memrw_no_increment - in the future we may want to be able |
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* to read/write a range of data to a "port". a "port" is an action on |
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* read memory address for some peripheral. |
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*/ |
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int arm11_write_memory_inner(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer, |
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bool arm11_config_memrw_no_increment) |
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{ |
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int retval; |
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FNC_INFO; |
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@@ -1497,6 +1512,10 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, |
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return arm11_run_instr_data_finish(arm11); |
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} |
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int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) |
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{ |
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return arm11_write_memory_inner(target, address, size, count, buffer, false); |
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} |
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/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */ |
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int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer) |
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@@ -2002,7 +2021,6 @@ int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char |
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BOOL_WRAPPER(memwrite_burst, "memory write burst mode") |
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BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes") |
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BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers") |
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BOOL_WRAPPER(step_irq_enable, "IRQs while stepping") |
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BOOL_WRAPPER(hardware_step, "hardware single step") |
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@@ -2182,10 +2200,6 @@ int arm11_register_commands(struct command_context_s *cmd_ctx) |
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register_command(cmd_ctx, top_cmd, "mrc", |
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arm11_handle_mrc, COMMAND_ANY, |
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"Read Coprocessor register. mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only."); |
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register_command(cmd_ctx, top_cmd, "no_increment", |
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arm11_handle_bool_memrw_no_increment, COMMAND_ANY, |
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"Don't increment address on multi-read/-write" |
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" (default: disabled)"); |
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register_command(cmd_ctx, top_cmd, "step_irq_enable", |
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arm11_handle_bool_step_irq_enable, COMMAND_ANY, |
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"Enable interrupts while stepping" |
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