- Replace '\([^_]\)u32' with '\1uint32_t'. - Replace '^u32' with 'uint32_t'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2279 b42882b7-edfa-0310-969c-e2dbd0fdcd60tags/v0.2.0
@@ -25,7 +25,7 @@ | |||
#include "binarybuffer.h" | |||
void init_mem_param(mem_param_t *param, u32 address, u32 size, enum param_direction direction) | |||
void init_mem_param(mem_param_t *param, uint32_t address, uint32_t size, enum param_direction direction) | |||
{ | |||
param->address = address; | |||
param->size = size; | |||
@@ -39,7 +39,7 @@ void destroy_mem_param(mem_param_t *param) | |||
param->value = NULL; | |||
} | |||
void init_reg_param(reg_param_t *param, char *reg_name, u32 size, enum param_direction direction) | |||
void init_reg_param(reg_param_t *param, char *reg_name, uint32_t size, enum param_direction direction) | |||
{ | |||
param->reg_name = reg_name; | |||
param->size = size; | |||
@@ -31,8 +31,8 @@ enum param_direction | |||
typedef struct mem_param_s | |||
{ | |||
u32 address; | |||
u32 size; | |||
uint32_t address; | |||
uint32_t size; | |||
uint8_t *value; | |||
enum param_direction direction; | |||
} mem_param_t; | |||
@@ -40,14 +40,14 @@ typedef struct mem_param_s | |||
typedef struct reg_param_s | |||
{ | |||
char *reg_name; | |||
u32 size; | |||
uint32_t size; | |||
uint8_t *value; | |||
enum param_direction direction; | |||
} reg_param_t; | |||
extern void init_mem_param(mem_param_t *param, u32 address, u32 size, enum param_direction direction); | |||
extern void init_mem_param(mem_param_t *param, uint32_t address, uint32_t size, enum param_direction direction); | |||
extern void destroy_mem_param(mem_param_t *param); | |||
extern void init_reg_param(reg_param_t *param, char *reg_name, u32 size, enum param_direction direction); | |||
extern void init_reg_param(reg_param_t *param, char *reg_name, uint32_t size, enum param_direction direction); | |||
extern void destroy_reg_param(reg_param_t *param); | |||
#endif /* ALGORITHM_H */ |
@@ -39,8 +39,8 @@ int avr_quit(void); | |||
int avr_arch_state(struct target_s *target); | |||
int avr_poll(target_t *target); | |||
int avr_halt(target_t *target); | |||
int avr_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution); | |||
int avr_step(struct target_s *target, int current, u32 address, int handle_breakpoints); | |||
int avr_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution); | |||
int avr_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints); | |||
int avr_assert_reset(target_t *target); | |||
int avr_deassert_reset(target_t *target); | |||
@@ -48,7 +48,7 @@ int avr_soft_reset_halt(struct target_s *target); | |||
/* IR and DR functions */ | |||
int avr_jtag_sendinstr(jtag_tap_t *tap, uint8_t *ir_in, uint8_t ir_out); | |||
int avr_jtag_senddat(jtag_tap_t *tap, u32 *dr_in, u32 dr_out, int len); | |||
int avr_jtag_senddat(jtag_tap_t *tap, uint32_t *dr_in, uint32_t dr_out, int len); | |||
int mcu_write_ir(jtag_tap_t *tap, uint8_t *ir_in, uint8_t *ir_out, int ir_len, int rti); | |||
int mcu_write_dr(jtag_tap_t *tap, uint8_t *dr_in, uint8_t *dr_out, int dr_len, int rti); | |||
@@ -56,8 +56,8 @@ int mcu_write_ir_u8(jtag_tap_t *tap, uint8_t *ir_in, uint8_t ir_out, int ir_len, | |||
int mcu_write_dr_u8(jtag_tap_t *tap, uint8_t *ir_in, uint8_t ir_out, int dr_len, int rti); | |||
int mcu_write_ir_u16(jtag_tap_t *tap, uint16_t *ir_in, uint16_t ir_out, int ir_len, int rti); | |||
int mcu_write_dr_u16(jtag_tap_t *tap, uint16_t *ir_in, uint16_t ir_out, int dr_len, int rti); | |||
int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rti); | |||
int mcu_write_dr_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int dr_len, int rti); | |||
int mcu_write_ir_u32(jtag_tap_t *tap, uint32_t *ir_in, uint32_t ir_out, int ir_len, int rti); | |||
int mcu_write_dr_u32(jtag_tap_t *tap, uint32_t *ir_in, uint32_t ir_out, int dr_len, int rti); | |||
int mcu_execute_queue(void); | |||
target_type_t avr_target = | |||
@@ -153,13 +153,13 @@ int avr_halt(target_t *target) | |||
return ERROR_OK; | |||
} | |||
int avr_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution) | |||
int avr_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) | |||
{ | |||
LOG_DEBUG("%s", __FUNCTION__); | |||
return ERROR_OK; | |||
} | |||
int avr_step(struct target_s *target, int current, u32 address, int handle_breakpoints) | |||
int avr_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) | |||
{ | |||
LOG_DEBUG("%s", __FUNCTION__); | |||
return ERROR_OK; | |||
@@ -187,7 +187,7 @@ int avr_soft_reset_halt(struct target_s *target) | |||
return ERROR_OK; | |||
} | |||
int avr_jtag_senddat(jtag_tap_t *tap, u32* dr_in, u32 dr_out, int len) | |||
int avr_jtag_senddat(jtag_tap_t *tap, uint32_t* dr_in, uint32_t dr_out, int len) | |||
{ | |||
return mcu_write_dr_u32(tap, dr_in, dr_out, len, 1); | |||
} | |||
@@ -297,7 +297,7 @@ int mcu_write_dr_u16(jtag_tap_t *tap, uint16_t *dr_in, uint16_t dr_out, int dr_l | |||
return ERROR_OK; | |||
} | |||
int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rti) | |||
int mcu_write_ir_u32(jtag_tap_t *tap, uint32_t *ir_in, uint32_t ir_out, int ir_len, int rti) | |||
{ | |||
if (ir_len > 32) | |||
{ | |||
@@ -310,7 +310,7 @@ int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rt | |||
return ERROR_OK; | |||
} | |||
int mcu_write_dr_u32(jtag_tap_t *tap, u32 *dr_in, u32 dr_out, int dr_len, int rti) | |||
int mcu_write_dr_u32(jtag_tap_t *tap, uint32_t *dr_in, uint32_t dr_out, int dr_len, int rti) | |||
{ | |||
if (dr_len > 32) | |||
{ | |||
@@ -39,7 +39,7 @@ static char *watchpoint_rw_strings[] = | |||
"access" | |||
}; | |||
int breakpoint_add(target_t *target, u32 address, u32 length, enum breakpoint_type type) | |||
int breakpoint_add(target_t *target, uint32_t address, uint32_t length, enum breakpoint_type type) | |||
{ | |||
breakpoint_t *breakpoint = target->breakpoints; | |||
breakpoint_t **breakpoint_p = &target->breakpoints; | |||
@@ -115,7 +115,7 @@ static void breakpoint_free(target_t *target, breakpoint_t *breakpoint_remove) | |||
free(breakpoint); | |||
} | |||
void breakpoint_remove(target_t *target, u32 address) | |||
void breakpoint_remove(target_t *target, uint32_t address) | |||
{ | |||
breakpoint_t *breakpoint = target->breakpoints; | |||
breakpoint_t **breakpoint_p = &target->breakpoints; | |||
@@ -147,7 +147,7 @@ void breakpoint_clear_target(target_t *target) | |||
} | |||
} | |||
breakpoint_t* breakpoint_find(target_t *target, u32 address) | |||
breakpoint_t* breakpoint_find(target_t *target, uint32_t address) | |||
{ | |||
breakpoint_t *breakpoint = target->breakpoints; | |||
@@ -161,7 +161,7 @@ breakpoint_t* breakpoint_find(target_t *target, u32 address) | |||
return NULL; | |||
} | |||
int watchpoint_add(target_t *target, u32 address, u32 length, enum watchpoint_rw rw, u32 value, u32 mask) | |||
int watchpoint_add(target_t *target, uint32_t address, uint32_t length, enum watchpoint_rw rw, uint32_t value, uint32_t mask) | |||
{ | |||
watchpoint_t *watchpoint = target->watchpoints; | |||
watchpoint_t **watchpoint_p = &target->watchpoints; | |||
@@ -234,7 +234,7 @@ static void watchpoint_free(target_t *target, watchpoint_t *watchpoint_remove) | |||
free(watchpoint); | |||
} | |||
void watchpoint_remove(target_t *target, u32 address) | |||
void watchpoint_remove(target_t *target, uint32_t address) | |||
{ | |||
watchpoint_t *watchpoint = target->watchpoints; | |||
watchpoint_t **watchpoint_p = &target->watchpoints; | |||
@@ -37,7 +37,7 @@ enum watchpoint_rw | |||
typedef struct breakpoint_s | |||
{ | |||
u32 address; | |||
uint32_t address; | |||
int length; | |||
enum breakpoint_type type; | |||
int set; | |||
@@ -47,21 +47,21 @@ typedef struct breakpoint_s | |||
typedef struct watchpoint_s | |||
{ | |||
u32 address; | |||
uint32_t address; | |||
int length; | |||
u32 mask; | |||
u32 value; | |||
uint32_t mask; | |||
uint32_t value; | |||
enum watchpoint_rw rw; | |||
int set; | |||
struct watchpoint_s *next; | |||
} watchpoint_t; | |||
extern void breakpoint_clear_target(struct target_s *target); | |||
extern int breakpoint_add(struct target_s *target, u32 address, u32 length, enum breakpoint_type type); | |||
extern void breakpoint_remove(struct target_s *target, u32 address); | |||
extern breakpoint_t* breakpoint_find(struct target_s *target, u32 address); | |||
extern int watchpoint_add(struct target_s *target, u32 address, u32 length, enum watchpoint_rw rw, u32 value, u32 mask); | |||
extern void watchpoint_remove(struct target_s *target, u32 address); | |||
extern int breakpoint_add(struct target_s *target, uint32_t address, uint32_t length, enum breakpoint_type type); | |||
extern void breakpoint_remove(struct target_s *target, uint32_t address); | |||
extern breakpoint_t* breakpoint_find(struct target_s *target, uint32_t address); | |||
extern int watchpoint_add(struct target_s *target, uint32_t address, uint32_t length, enum watchpoint_rw rw, uint32_t value, uint32_t mask); | |||
extern void watchpoint_remove(struct target_s *target, uint32_t address); | |||
extern void watchpoint_clear_target(struct target_s *target); | |||
#endif /* BREAKPOINTS_H */ |
@@ -104,7 +104,7 @@ int cortex_a8_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl) | |||
return ERROR_OK; | |||
} | |||
int cortex_a8_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer) | |||
int cortex_a8_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) | |||
{ | |||
/* get pointers to arch-specific information */ | |||
armv7m_common_t *armv7m = target->arch_info; | |||
@@ -136,7 +136,7 @@ int cortex_a8_read_memory(struct target_s *target, u32 address, u32 size, u32 co | |||
return retval; | |||
} | |||
int cortex_a8_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer) | |||
int cortex_a8_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) | |||
{ | |||
/* get pointers to arch-specific information */ | |||
armv7m_common_t *armv7m = target->arch_info; | |||
@@ -187,7 +187,7 @@ int cortex_a8_handle_target_request(void *priv) | |||
/* check if we have data */ | |||
if (ctrl & (1 << 0)) | |||
{ | |||
u32 request; | |||
uint32_t request; | |||
/* we assume target is quick enough */ | |||
request = data; | |||
@@ -48,17 +48,17 @@ typedef struct cortex_a8_fp_comparator_s | |||
{ | |||
int used; | |||
int type; | |||
u32 fpcr_value; | |||
u32 fpcr_address; | |||
uint32_t fpcr_value; | |||
uint32_t fpcr_address; | |||
} cortex_a8_fp_comparator_t; | |||
typedef struct cortex_a8_dwt_comparator_s | |||
{ | |||
int used; | |||
u32 comp; | |||
u32 mask; | |||
u32 function; | |||
u32 dwt_comparator_address; | |||
uint32_t comp; | |||
uint32_t mask; | |||
uint32_t function; | |||
uint32_t dwt_comparator_address; | |||
} cortex_a8_dwt_comparator_t; | |||
typedef struct cortex_a8_common_s | |||
@@ -67,9 +67,9 @@ typedef struct cortex_a8_common_s | |||
arm_jtag_t jtag_info; | |||
/* Context information */ | |||
u32 dcb_dhcsr; | |||
u32 nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */ | |||
u32 nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */ | |||
uint32_t dcb_dhcsr; | |||
uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */ | |||
uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */ | |||
/* Flash Patch and Breakpoint (FPB) */ | |||
int fp_num_lit; | |||
@@ -86,14 +86,14 @@ typedef struct cortex_a8_common_s | |||
/* Interrupts */ | |||
int intlinesnum; | |||
u32 *intsetenable; | |||
uint32_t *intsetenable; | |||
armv7m_common_t armv7m; | |||
void *arch_info; | |||
} cortex_a8_common_t; | |||
extern int cortex_a8_init_arch_info(target_t *target, cortex_a8_common_t *cortex_a8, jtag_tap_t *tap); | |||
int cortex_a8_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer); | |||
int cortex_a8_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer); | |||
int cortex_a8_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); | |||
int cortex_a8_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); | |||
#endif /* CORTEX_A8_H */ |
@@ -46,9 +46,9 @@ void cortex_m3_enable_watchpoints(struct target_s *target); | |||
int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp); | |||
int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target); | |||
int cortex_m3_quit(void); | |||
int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 *value); | |||
int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 value); | |||
int cortex_m3_target_request_data(target_t *target, u32 size, uint8_t *buffer); | |||
int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, uint32_t num, uint32_t *value); | |||
int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, uint32_t num, uint32_t value); | |||
int cortex_m3_target_request_data(target_t *target, uint32_t size, uint8_t *buffer); | |||
int cortex_m3_examine(struct target_s *target); | |||
#ifdef ARMV7_GDB_HACKS | |||
@@ -95,10 +95,10 @@ target_type_t cortexm3_target = | |||
.quit = cortex_m3_quit | |||
}; | |||
int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum) | |||
int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, uint32_t *value, int regnum) | |||
{ | |||
int retval; | |||
u32 dcrdr; | |||
uint32_t dcrdr; | |||
/* because the DCB_DCRDR is used for the emulated dcc channel | |||
* we gave to save/restore the DCB_DCRDR when used */ | |||
@@ -120,10 +120,10 @@ int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int re | |||
return retval; | |||
} | |||
int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum) | |||
int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, uint32_t value, int regnum) | |||
{ | |||
int retval; | |||
u32 dcrdr; | |||
uint32_t dcrdr; | |||
/* because the DCB_DCRDR is used for the emulated dcc channel | |||
* we gave to save/restore the DCB_DCRDR when used */ | |||
@@ -146,7 +146,7 @@ int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int re | |||
} | |||
int cortex_m3_write_debug_halt_mask(target_t *target, u32 mask_on, u32 mask_off) | |||
int cortex_m3_write_debug_halt_mask(target_t *target, uint32_t mask_on, uint32_t mask_off) | |||
{ | |||
/* get pointers to arch-specific information */ | |||
armv7m_common_t *armv7m = target->arch_info; | |||
@@ -186,7 +186,7 @@ int cortex_m3_single_step_core(target_t *target) | |||
armv7m_common_t *armv7m = target->arch_info; | |||
cortex_m3_common_t *cortex_m3 = armv7m->arch_info; | |||
swjdp_common_t *swjdp = &armv7m->swjdp_info; | |||
u32 dhcsr_save; | |||
uint32_t dhcsr_save; | |||
/* backup dhcsr reg */ | |||
dhcsr_save = cortex_m3->dcb_dhcsr; | |||
@@ -204,12 +204,12 @@ int cortex_m3_single_step_core(target_t *target) | |||
return ERROR_OK; | |||
} | |||
int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_invalue, &r0_outvalue */ ) | |||
int cortex_m3_exec_opcode(target_t *target,uint32_t opcode, int len /* MODE, r0_invalue, &r0_outvalue */ ) | |||
{ | |||
/* get pointers to arch-specific information */ | |||
armv7m_common_t *armv7m = target->arch_info; | |||
swjdp_common_t *swjdp = &armv7m->swjdp_info; | |||
u32 savedram; | |||
uint32_t savedram; | |||
int retvalue; | |||
mem_ap_read_u32(swjdp, 0x20000000, &savedram); | |||
@@ -224,13 +224,13 @@ int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_inval | |||
#if 0 | |||
/* Enable interrupts */ | |||
int cortex_m3_cpsie(target_t *target, u32 IF) | |||
int cortex_m3_cpsie(target_t *target, uint32_t IF) | |||
{ | |||
return cortex_m3_exec_opcode(target, ARMV7M_T_CPSIE(IF), 2); | |||
} | |||
/* Disable interrupts */ | |||
int cortex_m3_cpsid(target_t *target, u32 IF) | |||
int cortex_m3_cpsid(target_t *target, uint32_t IF) | |||
{ | |||
return cortex_m3_exec_opcode(target, ARMV7M_T_CPSID(IF), 2); | |||
} | |||
@@ -239,7 +239,7 @@ int cortex_m3_cpsid(target_t *target, u32 IF) | |||
int cortex_m3_endreset_event(target_t *target) | |||
{ | |||
int i; | |||
u32 dcb_demcr; | |||
uint32_t dcb_demcr; | |||
/* get pointers to arch-specific information */ | |||
armv7m_common_t *armv7m = target->arch_info; | |||
@@ -323,7 +323,7 @@ int cortex_m3_examine_debug_reason(target_t *target) | |||
int cortex_m3_examine_exception_reason(target_t *target) | |||
{ | |||
u32 shcsr, except_sr, cfsr = -1, except_ar = -1; | |||
uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1; | |||
/* get pointers to arch-specific information */ | |||
armv7m_common_t *armv7m = target->arch_info; | |||
@@ -374,7 +374,7 @@ int cortex_m3_examine_exception_reason(target_t *target) | |||
int cortex_m3_debug_entry(target_t *target) | |||
{ | |||
int i; | |||
u32 xPSR; | |||
uint32_t xPSR; | |||
int retval; | |||
/* get pointers to arch-specific information */ | |||
@@ -443,7 +443,7 @@ int cortex_m3_debug_entry(target_t *target) | |||
LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s", | |||
armv7m_mode_strings[armv7m->core_mode], | |||
*(u32*)(armv7m->core_cache->reg_list[15].value), | |||
*(uint32_t*)(armv7m->core_cache->reg_list[15].value), | |||
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); | |||
if (armv7m->post_debug_entry) | |||
@@ -574,7 +574,7 @@ int cortex_m3_soft_reset_halt(struct target_s *target) | |||
armv7m_common_t *armv7m = target->arch_info; | |||
cortex_m3_common_t *cortex_m3 = armv7m->arch_info; | |||
swjdp_common_t *swjdp = &armv7m->swjdp_info; | |||
u32 dcb_dhcsr = 0; | |||
uint32_t dcb_dhcsr = 0; | |||
int retval, timeout = 0; | |||
/* Enter debug state on reset, cf. end_reset_event() */ | |||
@@ -609,12 +609,12 @@ int cortex_m3_soft_reset_halt(struct target_s *target) | |||
return ERROR_OK; | |||
} | |||
int cortex_m3_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution) | |||
int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) | |||
{ | |||
/* get pointers to arch-specific information */ | |||
armv7m_common_t *armv7m = target->arch_info; | |||
breakpoint_t *breakpoint = NULL; | |||
u32 resume_pc; | |||
uint32_t resume_pc; | |||
if (target->state != TARGET_HALTED) | |||
{ | |||
@@ -695,7 +695,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand | |||
} | |||
/* int irqstepcount=0; */ | |||
int cortex_m3_step(struct target_s *target, int current, u32 address, int handle_breakpoints) | |||
int cortex_m3_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) | |||
{ | |||
/* get pointers to arch-specific information */ | |||
armv7m_common_t *armv7m = target->arch_info; | |||
@@ -797,7 +797,7 @@ int cortex_m3_assert_reset(target_t *target) | |||
/* get revision of lm3s target, only early silicon has this issue | |||
* Fury Rev B, DustDevil Rev B, Tempest all ok */ | |||
u32 did0; | |||
uint32_t did0; | |||
if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK) | |||
{ | |||
@@ -839,7 +839,7 @@ int cortex_m3_assert_reset(target_t *target) | |||
{ | |||
/* I do not know why this is necessary, but it fixes strange effects | |||
* (step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */ | |||
u32 tmp; | |||
uint32_t tmp; | |||
mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp); | |||
} | |||
} | |||
@@ -887,7 +887,7 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) | |||
{ | |||
int retval; | |||
int fp_num=0; | |||
u32 hilo; | |||
uint32_t hilo; | |||
/* get pointers to arch-specific information */ | |||
armv7m_common_t *armv7m = target->arch_info; | |||
@@ -1076,7 +1076,7 @@ int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin | |||
int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) | |||
{ | |||
int dwt_num=0; | |||
u32 mask, temp; | |||
uint32_t mask, temp; | |||
/* get pointers to arch-specific information */ | |||
armv7m_common_t *armv7m = target->arch_info; | |||
@@ -1218,7 +1218,7 @@ void cortex_m3_enable_watchpoints(struct target_s *target) | |||
} | |||
} | |||
int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype type, u32 num, u32 * value) | |||
int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t * value) | |||
{ | |||
int retval; | |||
/* get pointers to arch-specific information */ | |||
@@ -1271,10 +1271,10 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ | |||
return ERROR_OK; | |||
} | |||
int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value) | |||
int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t value) | |||
{ | |||
int retval; | |||
u32 reg; | |||
uint32_t reg; | |||
/* get pointers to arch-specific information */ | |||
armv7m_common_t *armv7m = target->arch_info; | |||
@@ -1339,7 +1339,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty | |||
return ERROR_OK; | |||
} | |||
int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer) | |||
int cortex_m3_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) | |||
{ | |||
/* get pointers to arch-specific information */ | |||
armv7m_common_t *armv7m = target->arch_info; | |||
@@ -1371,7 +1371,7 @@ int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 co | |||
return retval; | |||
} | |||
int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer) | |||
int cortex_m3_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) | |||
{ | |||
/* get pointers to arch-specific information */ | |||
armv7m_common_t *armv7m = target->arch_info; | |||
@@ -1401,7 +1401,7 @@ int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 c | |||
return retval; | |||
} | |||
int cortex_m3_bulk_write_memory(target_t *target, u32 address, u32 count, uint8_t *buffer) | |||
int cortex_m3_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) | |||
{ | |||
return cortex_m3_write_memory(target, address, 4, count, buffer); | |||
} | |||
@@ -1420,7 +1420,7 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta | |||
int cortex_m3_examine(struct target_s *target) | |||
{ | |||
int retval; | |||
u32 cpuid, fpcr, dwtcr, ictr; | |||
uint32_t cpuid, fpcr, dwtcr, ictr; | |||
int i; | |||
/* get pointers to arch-specific information */ | |||
@@ -1508,13 +1508,13 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl) | |||
return ERROR_OK; | |||
} | |||
int cortex_m3_target_request_data(target_t *target, u32 size, uint8_t *buffer) | |||
int cortex_m3_target_request_data(target_t *target, uint32_t size, uint8_t *buffer) | |||
{ | |||
armv7m_common_t *armv7m = target->arch_info; | |||
swjdp_common_t *swjdp = &armv7m->swjdp_info; | |||
uint8_t data; | |||
uint8_t ctrl; | |||
u32 i; | |||
uint32_t i; | |||
for (i = 0; i < (size * 4); i++) | |||
{ | |||
@@ -1546,7 +1546,7 @@ int cortex_m3_handle_target_request(void *priv) | |||
/* check if we have data */ | |||
if (ctrl & (1 << 0)) | |||
{ | |||
u32 request; | |||
uint32_t request; | |||
/* we assume target is quick enough */ | |||
request = data; | |||
@@ -121,17 +121,17 @@ typedef struct cortex_m3_fp_comparator_s | |||
{ | |||
int used; | |||
int type; | |||
u32 fpcr_value; | |||
u32 fpcr_address; | |||
uint32_t fpcr_value; | |||
uint32_t fpcr_address; | |||
} cortex_m3_fp_comparator_t; | |||
typedef struct cortex_m3_dwt_comparator_s | |||
{ | |||
int used; | |||
u32 comp; | |||
u32 mask; | |||
u32 function; | |||
u32 dwt_comparator_address; | |||
uint32_t comp; | |||
uint32_t mask; | |||
uint32_t function; | |||
uint32_t dwt_comparator_address; | |||
} cortex_m3_dwt_comparator_t; | |||
typedef struct cortex_m3_common_s | |||
@@ -140,9 +140,9 @@ typedef struct cortex_m3_common_s | |||
arm_jtag_t jtag_info; | |||
/* Context information */ | |||
u32 dcb_dhcsr; | |||
u32 nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */ | |||
u32 nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */ | |||
uint32_t dcb_dhcsr; | |||
uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */ | |||
uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */ | |||
/* Flash Patch and Breakpoint (FPB) */ | |||
int fp_num_lit; | |||
@@ -159,7 +159,7 @@ typedef struct cortex_m3_common_s | |||
/* Interrupts */ | |||
int intlinesnum; | |||
u32 *intsetenable; | |||
uint32_t *intsetenable; | |||
armv7m_common_t armv7m; | |||
// swjdp_common_t swjdp_info; | |||
@@ -170,16 +170,16 @@ extern void cortex_m3_build_reg_cache(target_t *target); | |||
int cortex_m3_poll(target_t *target); | |||
int cortex_m3_halt(target_t *target); | |||
int cortex_m3_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution); | |||
int cortex_m3_step(struct target_s *target, int current, u32 address, int handle_breakpoints); | |||
int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution); | |||
int cortex_m3_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints); | |||
int cortex_m3_assert_reset(target_t *target); | |||
int cortex_m3_deassert_reset(target_t *target); | |||
int cortex_m3_soft_reset_halt(struct target_s *target); | |||
int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer); | |||
int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer); | |||
int cortex_m3_bulk_write_memory(target_t *target, u32 address, u32 count, uint8_t *buffer); | |||
int cortex_m3_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); | |||
int cortex_m3_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); | |||
int cortex_m3_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer); | |||
int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint); | |||
int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint); | |||
@@ -287,7 +287,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* chec | |||
* we pretend the target is always going to be fast enough | |||
* (relative to the JTAG clock), so we don't need to handshake | |||
*/ | |||
int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) | |||
int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size) | |||
{ | |||
scan_field_t fields[3]; | |||
uint8_t field1_out[1]; | |||
@@ -340,7 +340,7 @@ int embeddedice_read_reg(reg_t *reg) | |||
return embeddedice_read_reg_w_check(reg, NULL, NULL); | |||
} | |||
void embeddedice_set_reg(reg_t *reg, u32 value) | |||
void embeddedice_set_reg(reg_t *reg, uint32_t value) | |||
{ | |||
embeddedice_write_reg(reg, value); | |||
@@ -363,7 +363,7 @@ int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf) | |||
return ERROR_OK; | |||
} | |||
void embeddedice_write_reg(reg_t *reg, u32 value) | |||
void embeddedice_write_reg(reg_t *reg, uint32_t value) | |||
{ | |||
embeddedice_reg_t *ice_reg = reg->arch_info; | |||
@@ -388,7 +388,7 @@ void embeddedice_store_reg(reg_t *reg) | |||
* we pretend the target is always going to be fast enough | |||
* (relative to the JTAG clock), so we don't need to handshake | |||
*/ | |||
int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size) | |||
int embeddedice_send(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size) | |||
{ | |||
scan_field_t fields[3]; | |||
uint8_t field0_out[4]; | |||
@@ -432,14 +432,14 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size) | |||
/* wait for DCC control register R/W handshake bit to become active | |||
*/ | |||
int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) | |||
int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, uint32_t timeout) | |||
{ | |||
scan_field_t fields[3]; | |||
uint8_t field0_in[4]; | |||
uint8_t field1_out[1]; | |||
uint8_t field2_out[1]; | |||
int retval; | |||
u32 hsact; | |||
uint32_t hsact; | |||
struct timeval lap; | |||
struct timeval now; | |||
@@ -484,7 +484,7 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) | |||
gettimeofday(&now, NULL); | |||
} | |||
while ((u32)((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000) <= timeout); | |||
while ((uint32_t)((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000) <= timeout); | |||
return ERROR_TARGET_TIMEOUT; | |||
} | |||
@@ -96,22 +96,22 @@ typedef struct embeddedice_reg_s | |||
extern reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9); | |||
extern int embeddedice_setup(target_t *target); | |||
extern int embeddedice_read_reg(reg_t *reg); | |||
extern void embeddedice_write_reg(reg_t *reg, u32 value); | |||
extern void embeddedice_write_reg(reg_t *reg, uint32_t value); | |||
extern int embeddedice_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask); | |||
extern void embeddedice_store_reg(reg_t *reg); | |||
extern void embeddedice_set_reg(reg_t *reg, u32 value); | |||
extern void embeddedice_set_reg(reg_t *reg, uint32_t value); | |||
extern int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf); | |||
extern int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size); | |||
extern int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size); | |||
extern int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout); | |||
extern int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size); | |||
extern int embeddedice_send(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size); | |||
extern int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, uint32_t timeout); | |||
/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be this faster version of | |||
* embeddedice_write_reg | |||
*/ | |||
static __inline__ void embeddedice_write_reg_inner( jtag_tap_t *tap, int reg_addr, u32 value) | |||
static __inline__ void embeddedice_write_reg_inner( jtag_tap_t *tap, int reg_addr, uint32_t value) | |||
{ | |||
static const int embeddedice_num_bits[]={32,5,1}; | |||
u32 values[3]; | |||
uint32_t values[3]; | |||
values[0]=value; | |||
values[1]=reg_addr; | |||
@@ -44,7 +44,7 @@ static int etb_get_reg(reg_t *reg); | |||
static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); | |||
static int etb_set_instr(etb_t *etb, u32 new_instr) | |||
static int etb_set_instr(etb_t *etb, uint32_t new_instr) | |||
{ | |||
jtag_tap_t *tap; | |||
@@ -71,7 +71,7 @@ static int etb_set_instr(etb_t *etb, u32 new_instr) | |||
return ERROR_OK; | |||
} | |||
static int etb_scann(etb_t *etb, u32 new_scan_chain) | |||
static int etb_scann(etb_t *etb, uint32_t new_scan_chain) | |||
{ | |||
if (etb->cur_scan_chain != new_scan_chain) | |||
{ | |||
@@ -160,11 +160,11 @@ static int etb_get_reg(reg_t *reg) | |||
static void etb_getbuf(uint8_t *in) | |||
{ | |||
*((u32 *)in)=buf_get_u32(in, 0, 32); | |||
*((uint32_t *)in)=buf_get_u32(in, 0, 32); | |||
} | |||
static int etb_read_ram(etb_t *etb, u32 *data, int num_frames) | |||
static int etb_read_ram(etb_t *etb, uint32_t *data, int num_frames) | |||
{ | |||
scan_field_t fields[3]; | |||
int i; | |||
@@ -275,7 +275,7 @@ int etb_read_reg(reg_t *reg) | |||
return etb_read_reg_w_check(reg, NULL, NULL); | |||
} | |||
int etb_set_reg(reg_t *reg, u32 value) | |||
int etb_set_reg(reg_t *reg, uint32_t value) | |||
{ | |||
int retval; | |||
@@ -306,7 +306,7 @@ int etb_set_reg_w_exec(reg_t *reg, uint8_t *buf) | |||
return ERROR_OK; | |||
} | |||
int etb_write_reg(reg_t *reg, u32 value) | |||
int etb_write_reg(reg_t *reg, uint32_t value) | |||
{ | |||
etb_reg_t *etb_reg = reg->arch_info; | |||
uint8_t reg_addr = etb_reg->addr & 0x7f; | |||
@@ -491,7 +491,7 @@ static int etb_read_trace(etm_context_t *etm_ctx) | |||
etb_t *etb = etm_ctx->capture_driver_priv; | |||
int first_frame = 0; | |||
int num_frames = etb->ram_depth; | |||
u32 *trace_data = NULL; | |||
uint32_t *trace_data = NULL; | |||
int i, j; | |||
etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]); | |||
@@ -514,7 +514,7 @@ static int etb_read_trace(etm_context_t *etm_ctx) | |||
etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame); | |||
/* read data into temporary array for unpacking */ | |||
trace_data = malloc(sizeof(u32) * num_frames); | |||
trace_data = malloc(sizeof(uint32_t) * num_frames); | |||
etb_read_ram(etb, trace_data, num_frames); | |||
if (etm_ctx->trace_depth > 0) | |||
@@ -639,8 +639,8 @@ static int etb_read_trace(etm_context_t *etm_ctx) | |||
static int etb_start_capture(etm_context_t *etm_ctx) | |||
{ | |||
etb_t *etb = etm_ctx->capture_driver_priv; | |||
u32 etb_ctrl_value = 0x1; | |||
u32 trigger_count; | |||
uint32_t etb_ctrl_value = 0x1; | |||
uint32_t trigger_count; | |||
if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED) | |||
{ | |||
@@ -40,17 +40,17 @@ typedef struct etb_s | |||
{ | |||
etm_context_t *etm_ctx; | |||
jtag_tap_t *tap; | |||
u32 cur_scan_chain; | |||
uint32_t cur_scan_chain; | |||
reg_cache_t *reg_cache; | |||
/* ETB parameters */ | |||
u32 ram_depth; | |||
u32 ram_width; | |||
uint32_t ram_depth; | |||
uint32_t ram_width; | |||
} etb_t; | |||
typedef struct etb_reg_s | |||
{ | |||
u32 addr; | |||
uint32_t addr; | |||
etb_t *etb; | |||
} etb_reg_t; | |||
@@ -58,10 +58,10 @@ extern etm_capture_driver_t etb_capture_driver; | |||
extern reg_cache_t* etb_build_reg_cache(etb_t *etb); | |||
extern int etb_read_reg(reg_t *reg); | |||
extern int etb_write_reg(reg_t *reg, u32 value); | |||
extern int etb_write_reg(reg_t *reg, uint32_t value); | |||
extern int etb_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask); | |||
extern int etb_store_reg(reg_t *reg); | |||
extern int etb_set_reg(reg_t *reg, u32 value); | |||
extern int etb_set_reg(reg_t *reg, uint32_t value); | |||
extern int etb_set_reg_w_exec(reg_t *reg, uint8_t *buf); | |||
#endif /* ETB_H */ |
@@ -261,7 +261,7 @@ reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_co | |||
int etm_setup(target_t *target) | |||
{ | |||
int retval; | |||
u32 etm_ctrl_value; | |||
uint32_t etm_ctrl_value; | |||
armv4_5_common_t *armv4_5 = target->arch_info; | |||
arm7_9_common_t *arm7_9 = armv4_5->arch_info; | |||
etm_context_t *etm_ctx = arm7_9->etm_ctx; | |||
@@ -366,7 +366,7 @@ int etm_read_reg(reg_t *reg) | |||
return etm_read_reg_w_check(reg, NULL, NULL); | |||
} | |||
int etm_set_reg(reg_t *reg, u32 value) | |||
int etm_set_reg(reg_t *reg, uint32_t value) | |||
{ | |||
int retval; | |||
@@ -397,7 +397,7 @@ int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf) | |||
return ERROR_OK; | |||
} | |||
int etm_write_reg(reg_t *reg, u32 value) | |||
int etm_write_reg(reg_t *reg, uint32_t value) | |||
{ | |||
etm_reg_t *etm_reg = reg->arch_info; | |||
uint8_t reg_addr = etm_reg->addr & 0x7f; | |||
@@ -474,8 +474,8 @@ static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instructi | |||
{ | |||
int i; | |||
int section = -1; | |||
u32 size_read; | |||
u32 opcode; | |||
uint32_t size_read; | |||
uint32_t opcode; | |||
int retval; | |||
if (!ctx->image) | |||
@@ -609,7 +609,7 @@ static int etmv1_branch_address(etm_context_t *ctx) | |||
uint8_t packet; | |||
int shift = 0; | |||
int apo; | |||
u32 i; | |||
uint32_t i; | |||
/* quit analysis if less than two cycles are left in the trace | |||
* because we can't extract the APO */ | |||
@@ -689,7 +689,7 @@ static int etmv1_branch_address(etm_context_t *ctx) | |||
return 0; | |||
} | |||
static int etmv1_data(etm_context_t *ctx, int size, u32 *data) | |||
static int etmv1_data(etm_context_t *ctx, int size, uint32_t *data) | |||
{ | |||
int j; | |||
uint8_t buf[4]; | |||
@@ -739,12 +739,12 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd | |||
while (ctx->pipe_index < ctx->trace_depth) | |||
{ | |||
uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat; | |||
u32 next_pc = ctx->current_pc; | |||
u32 old_data_index = ctx->data_index; | |||
u32 old_data_half = ctx->data_half; | |||
u32 old_index = ctx->pipe_index; | |||
u32 last_instruction = ctx->last_instruction; | |||
u32 cycles = 0; | |||
uint32_t next_pc = ctx->current_pc; | |||
uint32_t old_data_index = ctx->data_index; | |||
uint32_t old_data_half = ctx->data_half; | |||
uint32_t old_index = ctx->pipe_index; | |||
uint32_t last_instruction = ctx->last_instruction; | |||
uint32_t cycles = 0; | |||
int current_pc_ok = ctx->pc_ok; | |||
if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE) | |||
@@ -888,8 +888,8 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd | |||
if ((pipestat == STAT_ID) || (pipestat == STAT_BD)) | |||
{ | |||
u32 new_data_index = ctx->data_index; | |||
u32 new_data_half = ctx->data_half; | |||
uint32_t new_data_index = ctx->data_index; | |||
uint32_t new_data_half = ctx->data_half; | |||
/* in case of a branch with data, the branch target address was consumed before | |||
* we temporarily go back to the saved data index */ | |||
@@ -930,7 +930,7 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd | |||
{ | |||
if (instruction.info.load_store_multiple.register_list & (1 << i)) | |||
{ | |||
u32 data; | |||
uint32_t data; | |||
if (etmv1_data(ctx, 4, &data) != 0) | |||
return ERROR_ETM_ANALYSIS_FAILED; | |||
command_print(cmd_ctx, "data: 0x%8.8x", data); | |||
@@ -939,7 +939,7 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd | |||
} | |||
else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH)) | |||
{ | |||
u32 data; | |||
uint32_t data; | |||
if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0) | |||
return ERROR_ETM_ANALYSIS_FAILED; | |||
command_print(cmd_ctx, "data: 0x%8.8x", data); | |||
@@ -1504,7 +1504,7 @@ static int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, | |||
armv4_5_common_t *armv4_5; | |||
arm7_9_common_t *arm7_9; | |||
etm_context_t *etm_ctx; | |||
u32 i; | |||
uint32_t i; | |||
if (argc != 1) | |||
{ | |||
@@ -1572,7 +1572,7 @@ static int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, | |||
armv4_5_common_t *armv4_5; | |||
arm7_9_common_t *arm7_9; | |||
etm_context_t *etm_ctx; | |||
u32 i; | |||
uint32_t i; | |||
if (argc != 1) | |||
{ | |||
@@ -1633,7 +1633,7 @@ static int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, | |||
for (i = 0; i < etm_ctx->trace_depth; i++) | |||
{ | |||
u32 pipestat, packet, flags; | |||
uint32_t pipestat, packet, flags; | |||
fileio_read_u32(&file, &pipestat); | |||
fileio_read_u32(&file, &packet); | |||
fileio_read_u32(&file, &flags); | |||
@@ -1670,7 +1670,7 @@ static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx, | |||
if (argc > 0) | |||
{ | |||
u32 new_value = strtoul(args[0], NULL, 0); | |||
uint32_t new_value = strtoul(args[0], NULL, 0); | |||
if ((new_value < 2) || (new_value > 100)) | |||
{ | |||
@@ -143,25 +143,25 @@ typedef struct etm_context_s | |||
reg_cache_t *reg_cache; /* ETM register cache */ | |||
etm_capture_driver_t *capture_driver; /* driver used to access ETM data */ | |||
void *capture_driver_priv; /* capture driver private data */ | |||
u32 trigger_percent; /* percent of trace buffer to be filled after the trigger */ | |||
uint32_t trigger_percent; /* percent of trace buffer to be filled after the trigger */ | |||
trace_status_t capture_status; /* current state of capture run */ | |||
etmv1_trace_data_t *trace_data; /* trace data */ | |||
u32 trace_depth; /* number of trace cycles to be analyzed, 0 if no trace data available */ | |||
uint32_t trace_depth; /* number of trace cycles to be analyzed, 0 if no trace data available */ | |||
etm_portmode_t portmode; /* normal, multiplexed or demultiplexed */ | |||
etmv1_tracemode_t tracemode; /* type of information the trace contains (data, addres, contextID, ...) */ | |||
armv4_5_state_t core_state; /* current core state (ARM, Thumb, Jazelle) */ | |||
struct image_s *image; /* source for target opcodes */ | |||
u32 pipe_index; /* current trace cycle */ | |||
u32 data_index; /* cycle holding next data packet */ | |||
uint32_t pipe_index; /* current trace cycle */ | |||
uint32_t data_index; /* cycle holding next data packet */ | |||
int data_half; /* port half on a 16 bit port */ | |||
u32 current_pc; /* current program counter */ | |||
u32 pc_ok; /* full PC has been acquired */ | |||
u32 last_branch; /* last branch address output */ | |||
u32 last_branch_reason; /* branch reason code for the last branch encountered */ | |||
u32 last_ptr; /* address of the last data access */ | |||
u32 ptr_ok; /* whether last_ptr is valid */ | |||
u32 context_id; /* context ID of the code being traced */ | |||
u32 last_instruction; /* index of last instruction executed (to calculate cycle timings) */ | |||
uint32_t current_pc; /* current program counter */ | |||
uint32_t pc_ok; /* full PC has been acquired */ | |||
uint32_t last_branch; /* last branch address output */ | |||
uint32_t last_branch_reason; /* branch reason code for the last branch encountered */ | |||
uint32_t last_ptr; /* address of the last data access */ | |||
uint32_t ptr_ok; /* whether last_ptr is valid */ | |||
uint32_t context_id; /* context ID of the code being traced */ | |||
uint32_t last_instruction; /* index of last instruction executed (to calculate cycle timings) */ | |||
} etm_context_t; | |||
/* PIPESTAT values */ | |||
@@ -194,10 +194,10 @@ extern char *etmv1v1_branch_reason_strings[]; | |||
extern reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx); | |||
extern int etm_read_reg(reg_t *reg); | |||
extern int etm_write_reg(reg_t *reg, u32 value); | |||
extern int etm_write_reg(reg_t *reg, uint32_t value); | |||
extern int etm_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask); | |||
extern int etm_store_reg(reg_t *reg); | |||
extern int etm_set_reg(reg_t *reg, u32 value); | |||
extern int etm_set_reg(reg_t *reg, uint32_t value); | |||
extern int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf); | |||
extern int etm_setup(target_t *target); | |||
@@ -55,7 +55,7 @@ | |||
int feroceon_examine(struct target_s *target); | |||
int feroceon_target_create(struct target_s *target, Jim_Interp *interp); | |||
int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, uint8_t *buffer); | |||
int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer); | |||
int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target); | |||
int feroceon_quit(void); | |||
@@ -112,7 +112,7 @@ target_type_t feroceon_target = | |||
}; | |||
int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr) | |||
int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, uint32_t instr) | |||
{ | |||
scan_field_t fields[3]; | |||
uint8_t out_buf[4]; | |||
@@ -166,7 +166,7 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr) | |||
return ERROR_OK; | |||
} | |||
void feroceon_change_to_arm(target_t *target, u32 *r0, u32 *pc) | |||
void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc) | |||
{ | |||
armv4_5_common_t *armv4_5 = target->arch_info; | |||
arm7_9_common_t *arm7_9 = armv4_5->arch_info; | |||
@@ -212,7 +212,7 @@ void feroceon_change_to_arm(target_t *target, u32 *r0, u32 *pc) | |||
*pc -= (12 + 4); | |||
} | |||
void feroceon_read_core_regs(target_t *target, u32 mask, u32* core_regs[16]) | |||
void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16]) | |||
{ | |||
int i; | |||
armv4_5_common_t *armv4_5 = target->arch_info; | |||
@@ -231,14 +231,14 @@ void feroceon_read_core_regs(target_t *target, u32 mask, u32* core_regs[16]) | |||
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); | |||
} | |||
void feroceon_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size) | |||
void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size) | |||
{ | |||
int i; | |||
armv4_5_common_t *armv4_5 = target->arch_info; | |||
arm7_9_common_t *arm7_9 = armv4_5->arch_info; | |||
arm_jtag_t *jtag_info = &arm7_9->jtag_info; | |||
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0; | |||
u32 *buf_u32 = buffer; | |||
uint32_t *buf_u32 = buffer; | |||
uint16_t *buf_u16 = buffer; | |||
uint8_t *buf_u8 = buffer; | |||
@@ -268,7 +268,7 @@ void feroceon_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf | |||
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); | |||
} | |||
void feroceon_read_xpsr(target_t *target, u32 *xpsr, int spsr) | |||
void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) | |||
{ | |||
armv4_5_common_t *armv4_5 = target->arch_info; | |||
arm7_9_common_t *arm7_9 = armv4_5->arch_info; | |||
@@ -291,7 +291,7 @@ void feroceon_read_xpsr(target_t *target, u32 *xpsr, int spsr) | |||
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); | |||
} | |||
void feroceon_write_xpsr(target_t *target, u32 xpsr, int spsr) | |||
void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr) | |||
{ | |||
armv4_5_common_t *armv4_5 = target->arch_info; | |||
arm7_9_common_t *arm7_9 = armv4_5->arch_info; | |||
@@ -349,7 +349,7 @@ void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int sps | |||
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); | |||
} | |||
void feroceon_write_core_regs(target_t *target, u32 mask, u32 core_regs[16]) | |||
void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16]) | |||
{ | |||
int i; | |||
armv4_5_common_t *armv4_5 = target->arch_info; | |||
@@ -391,8 +391,8 @@ void feroceon_branch_resume_thumb(target_t *target) | |||
armv4_5_common_t *armv4_5 = target->arch_info; | |||
arm7_9_common_t *arm7_9 = armv4_5->arch_info; | |||
arm_jtag_t *jtag_info = &arm7_9->jtag_info; | |||
u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); | |||
u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); | |||
uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); | |||
uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); | |||
(void)(r0); // use R0... | |||
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); | |||
@@ -420,7 +420,7 @@ void feroceon_branch_resume_thumb(target_t *target) | |||
arm7_9->need_bypass_before_restart = 1; | |||
} | |||
int feroceon_read_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value) | |||
int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) | |||
{ | |||
armv4_5_common_t *armv4_5 = target->arch_info; | |||
arm7_9_common_t *arm7_9 = armv4_5->arch_info; | |||
@@ -442,7 +442,7 @@ int feroceon_read_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 | |||
return jtag_execute_queue(); | |||
} | |||
int feroceon_write_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value) | |||
int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) | |||
{ | |||
armv4_5_common_t *armv4_5 = target->arch_info; | |||
arm7_9_common_t *arm7_9 = armv4_5->arch_info; | |||
@@ -471,7 +471,7 @@ void feroceon_set_dbgrq(target_t *target) | |||
embeddedice_store_reg(dbg_ctrl); | |||
} | |||
void feroceon_enable_single_step(target_t *target, u32 next_pc) | |||
void feroceon_enable_single_step(target_t *target, uint32_t next_pc) | |||
{ | |||
armv4_5_common_t *armv4_5 = target->arch_info; | |||
arm7_9_common_t *arm7_9 = armv4_5->arch_info; | |||
@@ -507,20 +507,20 @@ int feroceon_examine_debug_reason(target_t *target) | |||
return ERROR_OK; | |||
} | |||
int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, uint8_t *buffer) | |||
int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) | |||
{ | |||
int retval; | |||
armv4_5_common_t *armv4_5 = target->arch_info; | |||
arm7_9_common_t *arm7_9 = armv4_5->arch_info; | |||
enum armv4_5_state core_state = armv4_5->core_state; | |||
u32 x, flip, shift, save[7]; | |||
u32 i; | |||
uint32_t x, flip, shift, save[7]; | |||
uint32_t i; | |||
/* | |||
* We can't use the dcc flow control bits, so let's transfer data | |||
* with 31 bits and flip the MSB each time a new data word is sent. | |||
*/ | |||
static u32 dcc_code[] = | |||
static uint32_t dcc_code[] = | |||
{ | |||
0xee115e10, /* 3: mrc p14, 0, r5, c1, c0, 0 */ | |||
0xe3a0301e, /* 1: mov r3, #30 */ | |||
@@ -544,7 +544,7 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, uint8_t | |||
0xeafffff3, /* b 3b */ | |||
}; | |||
u32 dcc_size = sizeof(dcc_code); | |||
uint32_t dcc_size = sizeof(dcc_code); | |||
if (!arm7_9->dcc_downloads) | |||
return target_write_memory(target, address, 4, count, buffer); | |||
@@ -592,8 +592,8 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, uint8_t | |||
shift = 1; | |||
for (i = 0; i < count; i++) | |||
{ | |||
u32 y = target_buffer_get_u32(target, buffer); | |||
u32 z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000); | |||
uint32_t y = target_buffer_get_u32(target, buffer); | |||
uint32_t z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000); | |||
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z); | |||
x = y << (32 - shift); | |||
if (++shift >= 32 || i + 1 >= count) | |||
@@ -45,7 +45,7 @@ static int autodetect_image_type(image_t *image, char *url) | |||
{ | |||
int retval; | |||
fileio_t fileio; | |||
u32 read_bytes; | |||
uint32_t read_bytes; | |||
uint8_t buffer[9]; | |||
/* read the first 4 bytes of image */ | |||
@@ -148,8 +148,8 @@ static int image_ihex_buffer_complete(image_t *image) | |||
{ | |||
image_ihex_t *ihex = image->type_private; | |||
fileio_t *fileio = &ihex->fileio; | |||
u32 full_address = 0x0; | |||
u32 cooked_bytes; | |||
uint32_t full_address = 0x0; | |||
uint32_t cooked_bytes; | |||
int i; | |||
char lpszLine[1023]; | |||
@@ -167,12 +167,12 @@ static int image_ihex_buffer_complete(image_t *image) | |||
while (fileio_fgets(fileio, 1023, lpszLine) == ERROR_OK) | |||
{ | |||
u32 count; | |||
u32 address; | |||
u32 record_type; | |||
u32 checksum; | |||
uint32_t count; | |||
uint32_t address; | |||
uint32_t record_type; | |||
uint32_t checksum; | |||
uint8_t cal_checksum = 0; | |||
u32 bytes_read = 0; | |||
uint32_t bytes_read = 0; | |||
if (sscanf(&lpszLine[bytes_read], ":%2x%4x%2x", &count, &address, &record_type) != 3) | |||
{ | |||
@@ -263,7 +263,7 @@ static int image_ihex_buffer_complete(image_t *image) | |||
} | |||
else if (record_type == 3) /* Start Segment Address Record */ | |||
{ | |||
u32 dummy; | |||
uint32_t dummy; | |||
/* "Start Segment Address Record" will not be supported */ | |||
/* but we must consume it, and do not create an error. */ | |||
@@ -303,7 +303,7 @@ static int image_ihex_buffer_complete(image_t *image) | |||
} | |||
else if (record_type == 5) /* Start Linear Address Record */ | |||
{ | |||
u32 start_address; | |||
uint32_t start_address; | |||
sscanf(&lpszLine[bytes_read], "%8x", &start_address); | |||
cal_checksum += (uint8_t)(start_address >> 24); | |||
@@ -339,8 +339,8 @@ static int image_ihex_buffer_complete(image_t *image) | |||
static int image_elf_read_headers(image_t *image) | |||
{ | |||
image_elf_t *elf = image->type_private; | |||
u32 read_bytes; | |||
u32 i,j; | |||
uint32_t read_bytes; | |||
uint32_t i,j; | |||
int retval; | |||
elf->header = malloc(sizeof(Elf32_Ehdr)); | |||
@@ -437,11 +437,11 @@ static int image_elf_read_headers(image_t *image) | |||
return ERROR_OK; | |||
} | |||
static int image_elf_read_section(image_t *image, int section, u32 offset, u32 size, uint8_t *buffer, u32 *size_read) | |||
static int image_elf_read_section(image_t *image, int section, uint32_t offset, uint32_t size, uint8_t *buffer, uint32_t *size_read) | |||
{ | |||
image_elf_t *elf = image->type_private; | |||
Elf32_Phdr *segment = (Elf32_Phdr *)image->sections[section].private; | |||
u32 read_size,really_read; | |||
uint32_t read_size,really_read; | |||
int retval; | |||
*size_read = 0; | |||
@@ -482,8 +482,8 @@ static int image_mot_buffer_complete(image_t *image) | |||
{ | |||
image_mot_t *mot = image->type_private; | |||
fileio_t *fileio = &mot->fileio; | |||
u32 full_address = 0x0; | |||
u32 cooked_bytes; | |||
uint32_t full_address = 0x0; | |||
uint32_t cooked_bytes; | |||
int i; | |||
char lpszLine[1023]; | |||
@@ -501,12 +501,12 @@ static int image_mot_buffer_complete(image_t *image) | |||
while (fileio_fgets(fileio, 1023, lpszLine) == ERROR_OK) | |||
{ | |||
u32 count; | |||
u32 address; | |||
u32 record_type; | |||
u32 checksum; | |||
uint32_t count; | |||
uint32_t address; | |||
uint32_t record_type; | |||
uint32_t checksum; | |||
uint8_t cal_checksum = 0; | |||
u32 bytes_read = 0; | |||
uint32_t bytes_read = 0; | |||
/* get record type and record length */ | |||
if (sscanf(&lpszLine[bytes_read], "S%1x%2x", &record_type, &count) != 2) | |||
@@ -599,7 +599,7 @@ static int image_mot_buffer_complete(image_t *image) | |||
else if (record_type == 5) | |||
{ | |||
/* S5 is the data count record, we ignore it */ | |||
u32 dummy; | |||
uint32_t dummy; | |||
while (count-- > 0) | |||
{ | |||
@@ -776,7 +776,7 @@ int image_open(image_t *image, char *url, char *type_string) | |||
return retval; | |||
}; | |||
int image_read_section(image_t *image, int section, u32 offset, u32 size, uint8_t *buffer, u32 *size_read) | |||
int image_read_section(image_t *image, int section, uint32_t offset, uint32_t size, uint8_t *buffer, uint32_t *size_read) | |||
{ | |||
int retval; | |||
@@ -822,13 +822,13 @@ int image_read_section(image_t *image, int section, u32 offset, u32 size, uint8_ | |||
else if (image->type == IMAGE_MEMORY) | |||
{ | |||
image_memory_t *image_memory = image->type_private; | |||
u32 address = image->sections[section].base_address + offset; | |||
uint32_t address = image->sections[section].base_address + offset; | |||
*size_read = 0; | |||
while ((size - *size_read) > 0) | |||
{ | |||
u32 size_in_cache; | |||
uint32_t size_in_cache; | |||
if (!image_memory->cache | |||
|| (address < image_memory->cache_address) | |||
@@ -876,7 +876,7 @@ int image_read_section(image_t *image, int section, u32 offset, u32 size, uint8_ | |||
return ERROR_OK; | |||
} | |||
int image_add_section(image_t *image, u32 base, u32 size, int flags, uint8_t *data) | |||
int image_add_section(image_t *image, uint32_t base, uint32_t size, int flags, uint8_t *data) | |||
{ | |||
image_section_t *section; | |||
@@ -997,12 +997,12 @@ void image_close(image_t *image) | |||
} | |||
} | |||
int image_calculate_checksum(uint8_t* buffer, u32 nbytes, u32* checksum) | |||
int image_calculate_checksum(uint8_t* buffer, uint32_t nbytes, uint32_t* checksum) | |||
{ | |||
u32 crc = 0xffffffff; | |||
uint32_t crc = 0xffffffff; | |||
LOG_DEBUG("Calculating checksum"); | |||
u32 crc32_table[256]; | |||
uint32_t crc32_table[256]; | |||
/* Initialize the CRC table and the decoding table. */ | |||
int i, j; | |||
@@ -49,8 +49,8 @@ typedef enum image_type | |||
typedef struct image_section_s | |||
{ | |||
u32 base_address; | |||
u32 size; | |||
uint32_t base_address; | |||
uint32_t size; | |||
int flags; | |||
void *private; /* private data */ | |||
} image_section_t; | |||
@@ -64,7 +64,7 @@ typedef struct image_s | |||
int base_address_set; /* whether the image has a base address set (for relocation purposes) */ | |||
int base_address; /* base address, if one is set */ | |||
int start_address_set; /* whether the image has a start address (entry point) associated */ | |||
u32 start_address; /* start address, if one is set */ | |||
uint32_t start_address; /* start address, if one is set */ | |||
} image_t; | |||
typedef struct image_binary_s | |||
@@ -82,7 +82,7 @@ typedef struct image_memory_s | |||
{ | |||
struct target_s *target; | |||
uint8_t *cache; | |||
u32 cache_address; | |||
uint32_t cache_address; | |||
} image_memory_t; | |||
typedef struct fileio_elf_s | |||
@@ -90,7 +90,7 @@ typedef struct fileio_elf_s | |||
fileio_t fileio; | |||
Elf32_Ehdr *header; | |||
Elf32_Phdr *segments; | |||
u32 segment_count; | |||
uint32_t segment_count; | |||
uint8_t endianness; | |||
} image_elf_t; | |||
@@ -101,11 +101,11 @@ typedef struct image_mot_s | |||
} image_mot_t; | |||
extern int image_open(image_t *image, char *url, char *type_string); | |||
extern int image_read_section(image_t *image, int section, u32 offset, u32 size, uint8_t *buffer, u32 *size_read); | |||
extern int image_read_section(image_t *image, int section, uint32_t offset, uint32_t size, uint8_t *buffer, uint32_t *size_read); | |||
extern void image_close(image_t *image); | |||
extern int image_add_section(image_t *image, u32 base, u32 size, int flags, uint8_t *data); | |||
extern int image_add_section(image_t *image, uint32_t base, uint32_t size, int flags, uint8_t *data); | |||
extern int image_calculate_checksum(uint8_t* buffer, u32 nbytes, u32* checksum); | |||
extern int image_calculate_checksum(uint8_t* buffer, uint32_t nbytes, uint32_t* checksum); | |||
#define ERROR_IMAGE_FORMAT_ERROR (-1400) | |||
#define ERROR_IMAGE_TYPE_UNKNOWN (-1401) | |||
@@ -116,7 +116,7 @@ int mips32_set_core_reg(reg_t *reg, uint8_t *buf) | |||
{ | |||
mips32_core_reg_t *mips32_reg = reg->arch_info; | |||
target_t *target = mips32_reg->target; | |||
u32 value = buf_get_u32(buf, 0, 32); | |||
uint32_t value = buf_get_u32(buf, 0, 32); | |||
if (target->state != TARGET_HALTED) | |||
{ | |||
@@ -132,7 +132,7 @@ int mips32_set_core_reg(reg_t *reg, uint8_t *buf) | |||
int mips32_read_core_reg(struct target_s *target, int num) | |||
{ | |||
u32 reg_value; | |||
uint32_t reg_value; | |||
mips32_core_reg_t *mips_core_reg; | |||
/* get pointers to arch-specific information */ | |||
@@ -152,7 +152,7 @@ int mips32_read_core_reg(struct target_s *target, int num) | |||
int mips32_write_core_reg(struct target_s *target, int num) | |||
{ | |||
u32 reg_value; | |||
uint32_t reg_value; | |||
mips32_core_reg_t *mips_core_reg; | |||
/* get pointers to arch-specific information */ | |||
@@ -336,7 +336,7 @@ int mips32_register_commands(struct command_context_s *cmd_ctx) | |||
return ERROR_OK; | |||
} | |||
int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info) | |||
int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info) | |||
{ | |||
/*TODO*/ | |||
return ERROR_OK; | |||
@@ -366,7 +366,7 @@ int mips32_configure_break_unit(struct target_s *target) | |||
/* get pointers to arch-specific information */ | |||
mips32_common_t *mips32 = target->arch_info; | |||
int retval; | |||
u32 dcr, bpinfo; | |||
uint32_t dcr, bpinfo; | |||
int i; | |||
if (mips32->bp_scanned) | |||
@@ -425,7 +425,7 @@ int mips32_enable_interrupts(struct target_s *target, int enable) | |||
{ | |||
int retval; | |||
int update = 0; | |||
u32 dcr; | |||
uint32_t dcr; | |||
/* read debug control register */ | |||
if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK) | |||
@@ -41,17 +41,17 @@ typedef struct mips32_comparator_s | |||
{ | |||
int used; | |||
//int type; | |||
u32 bp_value; | |||
u32 reg_address; | |||
uint32_t bp_value; | |||
uint32_t reg_address; | |||
} mips32_comparator_t; | |||
typedef struct mips32_common_s | |||
{ | |||
u32 common_magic; | |||
uint32_t common_magic; | |||
void *arch_info; | |||
reg_cache_t *core_cache; | |||
mips_ejtag_t ejtag_info; | |||
u32 core_regs[MIPS32NUMCOREREGS]; | |||
uint32_t core_regs[MIPS32NUMCOREREGS]; | |||
int bp_scanned; | |||
int num_inst_bpoints; | |||
@@ -68,7 +68,7 @@ typedef struct mips32_common_s | |||
typedef struct mips32_core_reg_s | |||
{ | |||
u32 num; | |||
uint32_t num; | |||
struct target_s *target; | |||
mips32_common_t *mips32_common; | |||
} mips32_core_reg_t; | |||
@@ -129,7 +129,7 @@ extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag | |||
extern int mips32_restore_context(target_t *target); | |||
extern int mips32_save_context(target_t *target); | |||
extern reg_cache_t *mips32_build_reg_cache(target_t *target); | |||
extern int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info); | |||
extern int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info); | |||
extern int mips32_configure_break_unit(struct target_s *target); | |||
extern int mips32_enable_interrupts(struct target_s *target, int enable); | |||
extern int mips32_examine(struct target_s *target); | |||
@@ -39,10 +39,10 @@ | |||
* displaying/modifying memory and memory mapped registers. | |||
*/ | |||
static int ejtag_dma_read(mips_ejtag_t *ejtag_info, u32 addr, u32 *data) | |||
static int ejtag_dma_read(mips_ejtag_t *ejtag_info, uint32_t addr, uint32_t *data) | |||
{ | |||
u32 v; | |||
u32 ejtag_ctrl; | |||
uint32_t v; | |||
uint32_t ejtag_ctrl; | |||
int retries = RETRY_ATTEMPTS; | |||
begin_ejtag_dma_read: | |||
@@ -85,10 +85,10 @@ begin_ejtag_dma_read: | |||
return ERROR_OK; | |||
} | |||
static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, uint16_t *data) | |||
static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, uint32_t addr, uint16_t *data) | |||
{ | |||
u32 v; | |||
u32 ejtag_ctrl; | |||
uint32_t v; | |||
uint32_t ejtag_ctrl; | |||
int retries = RETRY_ATTEMPTS; | |||
begin_ejtag_dma_read_h: | |||
@@ -137,10 +137,10 @@ begin_ejtag_dma_read_h: | |||
return ERROR_OK; | |||
} | |||
static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, uint8_t *data) | |||
static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, uint32_t addr, uint8_t *data) | |||
{ | |||
u32 v; | |||
u32 ejtag_ctrl; | |||
uint32_t v; | |||
uint32_t ejtag_ctrl; | |||
int retries = RETRY_ATTEMPTS; | |||
begin_ejtag_dma_read_b: | |||
@@ -199,10 +199,10 @@ begin_ejtag_dma_read_b: | |||
return ERROR_OK; | |||
} | |||
static int ejtag_dma_write(mips_ejtag_t *ejtag_info, u32 addr, u32 data) | |||
static int ejtag_dma_write(mips_ejtag_t *ejtag_info, uint32_t addr, uint32_t data) | |||
{ | |||
u32 v; | |||
u32 ejtag_ctrl; | |||
uint32_t v; | |||
uint32_t ejtag_ctrl; | |||
int retries = RETRY_ATTEMPTS; | |||
begin_ejtag_dma_write: | |||
@@ -246,10 +246,10 @@ begin_ejtag_dma_write: | |||
return ERROR_OK; | |||
} | |||
static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, u32 addr, u32 data) | |||
static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, uint32_t addr, uint32_t data) | |||
{ | |||
u32 v; | |||
u32 ejtag_ctrl; | |||
uint32_t v; | |||
uint32_t ejtag_ctrl; | |||
int retries = RETRY_ATTEMPTS; | |||
/* Handle the bigendian/littleendian */ | |||
@@ -297,10 +297,10 @@ begin_ejtag_dma_write_h: | |||
return ERROR_OK; | |||
} | |||
static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, u32 addr, u32 data) | |||
static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, uint32_t addr, uint32_t data) | |||
{ | |||
u32 v; | |||
u32 ejtag_ctrl; | |||
uint32_t v; | |||
uint32_t ejtag_ctrl; | |||
int retries = RETRY_ATTEMPTS; | |||
/* Handle the bigendian/littleendian */ | |||
@@ -349,7 +349,7 @@ begin_ejtag_dma_write_b: | |||
return ERROR_OK; | |||
} | |||
int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf) | |||
int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, uint32_t addr, int size, int count, void *buf) | |||
{ | |||
switch (size) | |||
{ | |||
@@ -358,13 +358,13 @@ int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int cou | |||
case 2: | |||
return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t*)buf); | |||
case 4: | |||
return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (u32*)buf); | |||
return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (uint32_t*)buf); | |||
} | |||
return ERROR_OK; | |||
} | |||
int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf) | |||
int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint32_t *buf) | |||
{ | |||
int i; | |||
int retval; | |||
@@ -377,7 +377,7 @@ int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 | |||
return ERROR_OK; | |||
} | |||
int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, uint16_t *buf) | |||
int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint16_t *buf) | |||
{ | |||
int i; | |||
int retval; | |||
@@ -390,7 +390,7 @@ int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, uint | |||
return ERROR_OK; | |||
} | |||
int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, uint8_t *buf) | |||
int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint8_t *buf) | |||
{ | |||
int i; | |||
int retval; | |||
@@ -403,7 +403,7 @@ int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, uint8 | |||
return ERROR_OK; | |||
} | |||
int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf) | |||
int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, uint32_t addr, int size, int count, void *buf) | |||
{ | |||
switch (size) | |||
{ | |||
@@ -412,13 +412,13 @@ int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int co | |||
case 2: | |||
return mips32_dmaacc_write_mem16(ejtag_info, addr, count,(uint16_t*)buf); | |||
case 4: | |||
return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (u32*)buf); | |||
return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (uint32_t*)buf); | |||
} | |||
return ERROR_OK; | |||
} | |||
int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf) | |||
int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint32_t *buf) | |||
{ | |||
int i; | |||
int retval; | |||
@@ -431,7 +431,7 @@ int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 | |||
return ERROR_OK; | |||
} | |||
int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, uint16_t *buf) | |||
int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint16_t *buf) | |||
{ | |||
int i; | |||
int retval; | |||
@@ -444,7 +444,7 @@ int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, uin | |||
return ERROR_OK; | |||
} | |||
int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, uint8_t *buf) | |||
int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint8_t *buf) | |||
{ | |||
int i; | |||
int retval; | |||
@@ -34,15 +34,15 @@ | |||
#define RETRY_ATTEMPTS 0 | |||
extern int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf); | |||
extern int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf); | |||
extern int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, uint32_t addr, int size, int count, void *buf); | |||
extern int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, uint32_t addr, int size, int count, void *buf); | |||
extern int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, uint8_t *buf); | |||
extern int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, uint16_t *buf); | |||
extern int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf); | |||
extern int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint8_t *buf); | |||
extern int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint16_t *buf); | |||
extern int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint32_t *buf); | |||
extern int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, uint8_t *buf); | |||
extern int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, uint16_t *buf); | |||
extern int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf); | |||
extern int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint8_t *buf); | |||
extern int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint16_t *buf); | |||
extern int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint32_t *buf); | |||
#endif |
@@ -78,20 +78,20 @@ Nico Coesel | |||
#include "mips32_pracc.h" | |||
typedef struct { | |||
u32 *local_iparam; | |||
uint32_t *local_iparam; | |||
int num_iparam; | |||
u32 *local_oparam; | |||
uint32_t *local_oparam; | |||
int num_oparam; | |||
u32 *code; | |||
uint32_t *code; | |||
int code_len; | |||
u32 stack[32]; | |||
uint32_t stack[32]; | |||
int stack_offset; | |||
mips_ejtag_t *ejtag_info; | |||
} mips32_pracc_context; | |||
static int wait_for_pracc_rw(mips_ejtag_t *ejtag_info, u32 *ctrl) | |||
static int wait_for_pracc_rw(mips_ejtag_t *ejtag_info, uint32_t *ctrl) | |||
{ | |||
u32 ejtag_ctrl; | |||
uint32_t ejtag_ctrl; | |||
while (1) | |||
{ | |||
@@ -108,11 +108,11 @@ static int wait_for_pracc_rw(mips_ejtag_t *ejtag_info, u32 *ctrl) | |||
return ERROR_OK; | |||
} | |||
static int mips32_pracc_exec_read(mips32_pracc_context *ctx, u32 address) | |||
static int mips32_pracc_exec_read(mips32_pracc_context *ctx, uint32_t address) | |||
{ | |||
mips_ejtag_t *ejtag_info = ctx->ejtag_info; | |||
int offset; | |||
u32 ejtag_ctrl, data; | |||
uint32_t ejtag_ctrl, data; | |||
if ((address >= MIPS32_PRACC_PARAM_IN) | |||
&& (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4)) | |||
@@ -164,9 +164,9 @@ static int mips32_pracc_exec_read(mips32_pracc_context *ctx, u32 address) | |||
return ERROR_OK; | |||
} | |||
static int mips32_pracc_exec_write(mips32_pracc_context *ctx, u32 address) | |||
static int mips32_pracc_exec_write(mips32_pracc_context *ctx, uint32_t address) | |||
{ | |||
u32 ejtag_ctrl,data; | |||
uint32_t ejtag_ctrl,data; | |||
int offset; | |||
mips_ejtag_t *ejtag_info = ctx->ejtag_info; | |||
@@ -207,10 +207,10 @@ static int mips32_pracc_exec_write(mips32_pracc_context *ctx, u32 address) | |||
return ERROR_OK; | |||
} | |||
int |