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@@ -533,7 +533,7 @@ static const struct reg_arch_type arm_reg_type = { |
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.set = armv4_5_set_core_reg, |
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}; |
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struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common) |
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struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm) |
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{ |
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int num_regs = ARRAY_SIZE(arm_core_regs); |
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struct reg_cache *cache = malloc(sizeof(struct reg_cache)); |
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@@ -557,7 +557,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm |
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{ |
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/* Skip registers this core doesn't expose */ |
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if (arm_core_regs[i].mode == ARM_MODE_MON |
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&& armv4_5_common->core_type != ARM_MODE_MON) |
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&& arm->core_type != ARM_MODE_MON) |
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continue; |
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/* REVISIT handle Cortex-M, which only shadows R13/SP */ |
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@@ -565,7 +565,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm |
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arch_info[i].num = arm_core_regs[i].cookie; |
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arch_info[i].mode = arm_core_regs[i].mode; |
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arch_info[i].target = target; |
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arch_info[i].armv4_5_common = armv4_5_common; |
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arch_info[i].armv4_5_common = arm; |
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reg_list[i].name = (char *) arm_core_regs[i].name; |
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reg_list[i].size = 32; |
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@@ -576,8 +576,8 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm |
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cache->num_regs++; |
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} |
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armv4_5_common->cpsr = reg_list + ARMV4_5_CPSR; |
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armv4_5_common->core_cache = cache; |
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arm->cpsr = reg_list + ARMV4_5_CPSR; |
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arm->core_cache = cache; |
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return cache; |
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} |
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