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# OMAP4430 |
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if { [info exists CHIPNAME] } { |
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set _CHIPNAME $CHIPNAME |
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} else { |
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set _CHIPNAME omap4430 |
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} |
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# Although the OMAP4430 supposedly has an ICEpick-D, only the |
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# ICEpick-C router commands seem to work. |
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# See http://processors.wiki.ti.com/index.php/ICEPICK |
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source [find target/icepick.cfg] |
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# |
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# A9 DAP |
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# |
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if { [info exists DAP_TAPID ] } { |
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set _DAP_TAPID $DAP_TAPID |
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} else { |
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set _DAP_TAPID 0x3BA00477 |
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} |
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jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \ |
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-expected-id $_DAP_TAPID -disable |
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jtag configure $_CHIPNAME.dap -event tap-enable \ |
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"icepick_c_tapenable $_CHIPNAME.jrc 9" |
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# |
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# M3 DAPs, one per core |
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# |
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if { [info exists M3_DAP_TAPID ] } { |
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set _M3_DAP_TAPID $M3_DAP_TAPID |
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} else { |
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set _M3_DAP_TAPID 0x4BA00477 |
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} |
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jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \ |
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-expected-id $_M3_DAP_TAPID -disable |
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jtag configure $_CHIPNAME.m31_dap -event tap-enable \ |
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"icepick_c_tapenable $_CHIPNAME.jrc 5" |
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jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \ |
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-expected-id $_M3_DAP_TAPID -disable |
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jtag configure $_CHIPNAME.m30_dap -event tap-enable \ |
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"icepick_c_tapenable $_CHIPNAME.jrc 4" |
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# |
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# ICEpick-D JRC (JTAG route controller) |
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# |
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if { [info exists JRC_TAPID ] } { |
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set _JRC_TAPID $JRC_TAPID |
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} else { |
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set _JRC_TAPID 0x3b95c02f |
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} |
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ |
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-expected-id $_JRC_TAPID |
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# Required by ICEpick to power-up the debug domain |
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jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200" |
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# |
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# GDB target: Cortex-A9, using DAP |
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# |
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# The debugger can connect to either core of the A9, but currently |
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# not both simultaneously. Change -coreid to 1 to connect to the |
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# second core. |
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# |
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set _TARGETNAME $_CHIPNAME.cpu |
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target create $_TARGETNAME cortex_a9 -chain-position $_CHIPNAME.dap -coreid 0 |
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# SRAM: 56KiB at 0x4030.0000 |
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$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000 |
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# |
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# M3 targets, separate TAP/DAP for each core |
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# |
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target create $_CHIPNAME.m30 cortex_m3 -chain-position $_CHIPNAME.m30_dap |
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target create $_CHIPNAME.m31 cortex_m3 -chain-position $_CHIPNAME.m31_dap |
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# Once the JRC is up, enable our TAPs |
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jtag configure $_CHIPNAME.jrc -event setup " |
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jtag tapenable $_CHIPNAME.dap |
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jtag tapenable $_CHIPNAME.m30_dap |
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jtag tapenable $_CHIPNAME.m31_dap |
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" |
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proc omap4_dbginit {target} { |
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# General Cortex A9 debug initialisation |
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cortex_a9 dbginit |
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} |
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$_TARGETNAME configure -event reset-assert-post "omap4_dbginit $_TARGETNAME" |
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# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset |
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# ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset. |
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set PRM_RSTCTRL 0x4A307B00 |
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$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 0x1" |
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