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@@ -34,28 +34,38 @@ if { [info exists JRC_TAPID ] } { |
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ |
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-expected-id $_JRC_TAPID |
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jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100" |
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# GDB target: Cortex-A8, using DAP |
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target create omap3.cpu cortex_a8 -chain-position $_CHIPNAME.dap |
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set _TARGETNAME $_CHIPNAME.cpu |
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target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap |
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################### |
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# FIXME much of this should be in reset event handlers |
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proc omap3_dbginit { } { |
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poll off |
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sleep 100 |
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# the reset sequence is event-driven |
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# and kind of finicky... |
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# some TCK tycles are required to activate the DEBUG power domain |
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jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100" |
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jtag tapenable omap3530.dap |
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targets |
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# have the DAP "always" be active |
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jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" |
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proc omap3_dbginit {target} { |
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# General Cortex A8 debug initialisation |
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cortex_a8 dbginit |
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# Enable DBGU signal for OMAP353x |
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omap3.cpu mww 0x5401d030 0x00002000 |
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poll on |
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$target mww 0x5401d030 0x00002000 |
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} |
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set PRM_RSTCTRL 0x48307250 |
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omap3.cpu configure -event reset-start "omap3.cpu mww $PRM_RSTCTRL 2" |
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omap3.cpu configure -event reset-assert-pre "omap3_dbginit" |
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# be absolutely certain the JTAG clock will work with the worst-case |
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# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in. |
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# OK to speed up *after* PLL and clock tree setup. |
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jtag_rclk 1000 |
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$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 } |
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# REVISIT This assumes that SRST is unavailable, so we must assert reset |
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# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick |
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# would issue. RST_DPLL3 (4) is a cold reset. |
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set PRM_RSTCTRL 0x48307250 |
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$_TARGETNAME configure -event reset-assert-pre "$_TARGETNAME mww $PRM_RSTCTRL 2" |
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$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME" |