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omap3530: target reset/init improvements

Now I can issue "reset halt" and have everything act smoothly;
the vector_catch hardware is obviously not kicking in, but the
rest of the reset sequence acts sanely.

 - TAP "setup" event enables the DAP, not omap3_dbginit
   (resolving a chicken/egg bug I noted a while back)
 - Remove stuff from omap3_dbginit which should never be
   used in event handlers
 - Cope better with slow clocking during reset

Also, stop hard-wiring the target name: use the input params in
the standard way, and set up $_TARGETNAME as an output param.

Signed-off-by: David Brownell <>
David Brownell 14 years ago
1 changed files with 25 additions and 15 deletions
  1. +25

+ 25
- 15
tcl/target/omap3530.cfg View File

@@ -34,28 +34,38 @@ if { [info exists JRC_TAPID ] } {
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-expected-id $_JRC_TAPID

jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"

# GDB target: Cortex-A8, using DAP
target create omap3.cpu cortex_a8 -chain-position $_CHIPNAME.dap
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap


# FIXME much of this should be in reset event handlers
proc omap3_dbginit { } {
poll off
sleep 100
# the reset sequence is event-driven
# and kind of finicky...

# some TCK tycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"

jtag tapenable omap3530.dap
# have the DAP "always" be active
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"

proc omap3_dbginit {target} {
# General Cortex A8 debug initialisation
cortex_a8 dbginit
# Enable DBGU signal for OMAP353x
omap3.cpu mww 0x5401d030 0x00002000
poll on
$target mww 0x5401d030 0x00002000

set PRM_RSTCTRL 0x48307250

omap3.cpu configure -event reset-start "omap3.cpu mww $PRM_RSTCTRL 2"
omap3.cpu configure -event reset-assert-pre "omap3_dbginit"
# be absolutely certain the JTAG clock will work with the worst-case
# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
# OK to speed up *after* PLL and clock tree setup.
jtag_rclk 1000
$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }

# REVISIT This assumes that SRST is unavailable, so we must assert reset
# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
# would issue. RST_DPLL3 (4) is a cold reset.
set PRM_RSTCTRL 0x48307250
$_TARGETNAME configure -event reset-assert-pre "$_TARGETNAME mww $PRM_RSTCTRL 2"

$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"