@@ -33,94 +33,8 @@
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
/* cli handling */
int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
/* forward declarations */
int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm926ejs_quit(void);
int arm926ejs_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int arm926ejs_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical);
static int arm926ejs_mmu(struct target_s *target, int *enabled);
int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
static int arm926ejs_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
if (cpnum!=15)
{
LOG_ERROR("Only cp15 is supported");
return ERROR_FAIL;
}
return arm926ejs_cp15_read(target, op1, op2, CRn, CRm, value);
}
static int arm926ejs_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
if (cpnum!=15)
{
LOG_ERROR("Only cp15 is supported");
return ERROR_FAIL;
}
return arm926ejs_cp15_write(target, op1, op2, CRn, CRm, value);
}
target_type_t arm926ejs_target =
{
.name = "arm926ejs",
.poll = arm7_9_poll,
.arch_state = arm926ejs_arch_state,
.target_request_data = arm7_9_target_request_data,
.halt = arm7_9_halt,
.resume = arm7_9_resume,
.step = arm7_9_step,
.assert_reset = arm7_9_assert_reset,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm926ejs_soft_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.read_memory = arm7_9_read_memory,
.write_memory = arm926ejs_write_memory,
.bulk_write_memory = arm7_9_bulk_write_memory,
.checksum_memory = arm7_9_checksum_memory,
.blank_check_memory = arm7_9_blank_check_memory,
.run_algorithm = armv4_5_run_algorithm,
.add_breakpoint = arm7_9_add_breakpoint,
.remove_breakpoint = arm7_9_remove_breakpoint,
.add_watchpoint = arm7_9_add_watchpoint,
.remove_watchpoint = arm7_9_remove_watchpoint,
.register_commands = arm926ejs_register_commands,
.target_create = arm926ejs_target_create,
.init_target = arm926ejs_init_target,
.examine = arm9tdmi_examine,
.quit = arm926ejs_quit,
.virt2phys = arm926ejs_virt2phys,
.mmu = arm926ejs_mmu,
.read_phys_memory = arm926ejs_read_phys_memory,
.write_phys_memory = arm926ejs_write_phys_memory,
.mrc = arm926ejs_mrc,
.mcr = arm926ejs_mcr,
};
int arm926ejs_catch_broken_irscan(uint8_t *captured, void *priv, scan_field_t *field)
static int arm926ejs_catch_broken_irscan(uint8_t *captured, void *priv,
scan_field_t *field)
{
/* FIX!!!! this code should be reenabled. For now it does not check
* the queue...*/
@@ -144,7 +58,8 @@ int arm926ejs_catch_broken_irscan(uint8_t *captured, void *priv, scan_field_t *f
#define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
static int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t *value)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -226,7 +141,18 @@ int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t C
return ERROR_OK;
}
int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
static int arm926ejs_mrc(target_t *target, int cpnum, uint32_t op1,
uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
if (cpnum != 15) {
LOG_ERROR("Only cp15 is supported");
return ERROR_FAIL;
}
return arm926ejs_cp15_read(target, op1, op2, CRn, CRm, value);
}
static int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t value)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -306,6 +232,16 @@ int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t
return ERROR_OK;
}
static int arm926ejs_mcr(target_t *target, int cpnum, uint32_t op1,
uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
if (cpnum != 15) {
LOG_ERROR("Only cp15 is supported");
return ERROR_FAIL;
}
return arm926ejs_cp15_write(target, op1, op2, CRn, CRm, value);
}
static int arm926ejs_examine_debug_reason(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -410,7 +346,7 @@ static int arm926ejs_examine_debug_reason(target_t *target)
return ERROR_OK;
}
uint32_t arm926ejs_get_ttb(target_t *target)
static uint32_t arm926ejs_get_ttb(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -425,7 +361,8 @@ uint32_t arm926ejs_get_ttb(target_t *target)
return ttb;
}
void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
static void arm926ejs_disable_mmu_caches(target_t *target, int mmu,
int d_u_cache, int i_cache)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -476,7 +413,8 @@ void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int
arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
}
void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
static void arm926ejs_enable_mmu_caches(target_t *target, int mmu,
int d_u_cache, int i_cache)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -500,7 +438,7 @@ void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i
arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
}
void arm926ejs_post_debug_entry(target_t *target)
static void arm926ejs_post_debug_entry(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -542,7 +480,7 @@ void arm926ejs_post_debug_entry(target_t *target)
arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
}
void arm926ejs_pre_restore_context(target_t *target)
static void arm926ejs_pre_restore_context(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -563,7 +501,11 @@ void arm926ejs_pre_restore_context(target_t *target)
arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
}
int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
static int arm926ejs_get_arch_pointers(target_t *target,
armv4_5_common_t **armv4_5_p,
arm7_9_common_t **arm7_9_p,
arm9tdmi_common_t **arm9tdmi_p,
arm926ejs_common_t **arm926ejs_p)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9;
@@ -702,7 +644,8 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
}
int arm926ejs_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
int arm926ejs_write_memory(struct target_s *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -765,7 +708,9 @@ int arm926ejs_write_memory(struct target_s *target, uint32_t address, uint32_t s
return retval;
}
int arm926ejs_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
static int arm926ejs_write_phys_memory(struct target_s *target,
uint32_t address, uint32_t size,
uint32_t count, uint8_t *buffer)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -775,7 +720,9 @@ int arm926ejs_write_phys_memory(struct target_s *target, uint32_t address, uint3
return armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, address, size, count, buffer);
}
int arm926ejs_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
static int arm926ejs_read_phys_memory(struct target_s *target,
uint32_t address, uint32_t size,
uint32_t count, uint8_t *buffer)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -785,19 +732,21 @@ int arm926ejs_read_phys_memory(struct target_s *target, uint32_t address, uint32
return armv4_5_mmu_read_physical(target, &arm926ejs->armv4_5_mmu, address, size, count, buffer);
}
int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
static int arm926ejs_init_target(struct command_context_s *cmd_ctx,
struct target_s *target)
{
arm9tdmi_init_target(cmd_ctx, target);
return ERROR_OK;
}
int arm926ejs_quit(void)
static int arm926ejs_quit(void)
{
return ERROR_OK;
}
int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap)
int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs,
jtag_tap_t *tap)
{
arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
@@ -834,7 +783,7 @@ int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jt
return ERROR_OK;
}
int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
static int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
{
arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
@@ -843,24 +792,8 @@ int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
return ERROR_OK;
}
int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
{
int retval;
command_t *arm926ejs_cmd;
retval = arm9tdmi_register_commands(cmd_ctx);
arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
return retval;
}
int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
static int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx,
char *cmd, char **args, int argc)
{
int retval;
target_t *target = get_current_target(cmd_ctx);
@@ -925,7 +858,9 @@ int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd,
return ERROR_OK;
}
int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
static int
arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx,
char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
@@ -981,3 +916,73 @@ static int arm926ejs_mmu(struct target_s *target, int *enabled)
*enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
return ERROR_OK;
}
int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
{
int retval;
command_t *arm926ejs_cmd;
retval = arm9tdmi_register_commands(cmd_ctx);
arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs",
NULL, COMMAND_ANY,
"arm926ejs specific commands");
register_command(cmd_ctx, arm926ejs_cmd, "cp15",
arm926ejs_handle_cp15_command, COMMAND_EXEC,
"display/modify cp15 register "
"<opcode_1> <opcode_2> <CRn> <CRm> [value]");
register_command(cmd_ctx, arm926ejs_cmd, "cache_info",
arm926ejs_handle_cache_info_command, COMMAND_EXEC,
"display information about target caches");
return retval;
}
target_type_t arm926ejs_target =
{
.name = "arm926ejs",
.poll = arm7_9_poll,
.arch_state = arm926ejs_arch_state,
.target_request_data = arm7_9_target_request_data,
.halt = arm7_9_halt,
.resume = arm7_9_resume,
.step = arm7_9_step,
.assert_reset = arm7_9_assert_reset,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm926ejs_soft_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.read_memory = arm7_9_read_memory,
.write_memory = arm926ejs_write_memory,
.bulk_write_memory = arm7_9_bulk_write_memory,
.checksum_memory = arm7_9_checksum_memory,
.blank_check_memory = arm7_9_blank_check_memory,
.run_algorithm = armv4_5_run_algorithm,
.add_breakpoint = arm7_9_add_breakpoint,
.remove_breakpoint = arm7_9_remove_breakpoint,
.add_watchpoint = arm7_9_add_watchpoint,
.remove_watchpoint = arm7_9_remove_watchpoint,
.register_commands = arm926ejs_register_commands,
.target_create = arm926ejs_target_create,
.init_target = arm926ejs_init_target,
.examine = arm9tdmi_examine,
.quit = arm926ejs_quit,
.virt2phys = arm926ejs_virt2phys,
.mmu = arm926ejs_mmu,
.read_phys_memory = arm926ejs_read_phys_memory,
.write_phys_memory = arm926ejs_write_phys_memory,
.mrc = arm926ejs_mrc,
.mcr = arm926ejs_mcr,
};