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@@ -1712,50 +1712,41 @@ static int xscale_full_context(struct target *target) |
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mode, j).valid) |
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valid = false; |
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} |
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if (valid) |
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continue; |
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if (!valid) |
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{ |
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uint32_t tmp_cpsr; |
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/* request banked registers */ |
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xscale_send_u32(target, 0x0); |
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/* request banked registers */ |
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xscale_send_u32(target, 0x0); |
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tmp_cpsr = 0x0; |
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tmp_cpsr |= mode; |
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tmp_cpsr |= 0xc0; /* I/F bits */ |
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/* send CPSR for desired mode */ |
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xscale_send_u32(target, tmp_cpsr); |
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/* send CPSR for desired bank mode */ |
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xscale_send_u32(target, mode | 0xc0 /* I/F bits */); |
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/* get banked registers: r8 to r14; and SPSR |
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* if not in USR/SYS mode |
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*/ |
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if (mode != ARMV4_5_MODE_SYS) { |
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/* SPSR */ |
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r = &ARMV4_5_CORE_REG_MODE( |
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armv4_5->core_cache, |
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mode, 16); |
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xscale_receive(target, buffer, 8); |
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buf_set_u32(r->value, 0, 32, buffer[7]); |
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r->dirty = false; |
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r->valid = true; |
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} else { |
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xscale_receive(target, buffer, 7); |
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} |
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/* get banked registers: r8 to r14; and SPSR |
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* except in USR/SYS mode |
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*/ |
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if (mode != ARMV4_5_MODE_SYS) { |
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/* SPSR */ |
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r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, |
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mode, 16); |
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xscale_receive(target, buffer, 8); |
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buf_set_u32(r->value, 0, 32, buffer[7]); |
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r->dirty = false; |
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r->valid = true; |
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} else { |
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xscale_receive(target, buffer, 7); |
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} |
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/* move data from buffer to register cache */ |
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for (j = 8; j <= 14; j++) |
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{ |
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r = &ARMV4_5_CORE_REG_MODE( |
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armv4_5->core_cache, |
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mode, j); |
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/* move data from buffer to register cache */ |
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for (j = 8; j <= 14; j++) |
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{ |
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r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, |
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mode, j); |
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buf_set_u32(r->value, 0, 32, buffer[j - 8]); |
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r->dirty = false; |
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r->valid = true; |
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} |
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buf_set_u32(r->value, 0, 32, buffer[j - 8]); |
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r->dirty = false; |
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r->valid = true; |
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} |
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} |
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