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@@ -238,7 +238,7 @@ static int cortex_a_init_debug_access(struct target *target) |
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the registers in the Core Power Domain */ |
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retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, |
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armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg); |
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LOG_DEBUG("target->coreid %d DBGPRSR 0x%x ", target->coreid, dbg_osreg); |
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LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg); |
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if (retval != ERROR_OK) |
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return retval; |
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@@ -2954,7 +2954,7 @@ static int cortex_a_examine_first(struct target *target) |
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if (retval != ERROR_OK) |
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return retval; |
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LOG_DEBUG("target->coreid %d DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg); |
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LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg); |
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armv7a->arm.core_type = ARM_MODE_MON; |
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retval = cortex_a_dpm_setup(cortex_a, didr); |
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