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@@ -34,6 +34,61 @@ |
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* implementation differences between cores like ARM1136 and Cortex-A8. |
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*/ |
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/* |
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* Coprocessor support |
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*/ |
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/* Read coprocessor */ |
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static int dpm_mrc(struct target *target, int cpnum, |
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uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, |
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uint32_t *value) |
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{ |
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struct arm *arm = target_to_arm(target); |
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struct arm_dpm *dpm = arm->dpm; |
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int retval; |
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retval = dpm->prepare(dpm); |
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if (retval != ERROR_OK) |
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return retval; |
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LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum, op1, CRn, CRm, op2); |
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/* read coprocessor register into R0; return via DCC */ |
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retval = dpm->instr_read_data_r0(dpm, |
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ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2), |
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value); |
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/* (void) */ dpm->finish(dpm); |
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return retval; |
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} |
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static int dpm_mcr(struct target *target, int cpnum, |
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uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, |
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uint32_t value) |
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{ |
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struct arm *arm = target_to_arm(target); |
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struct arm_dpm *dpm = arm->dpm; |
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int retval; |
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retval = dpm->prepare(dpm); |
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if (retval != ERROR_OK) |
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return retval; |
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LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum, op1, CRn, CRm, op2); |
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/* read DCC into r0; then write coprocessor register from R0 */ |
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retval = dpm->instr_write_data_r0(dpm, |
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ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2), |
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value); |
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/* (void) */ dpm->finish(dpm); |
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return retval; |
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} |
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/* |
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* Register access utilities |
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*/ |
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/* Toggles between recorded core mode (USR, SVC, etc) and a temporary one. |
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* Routines *must* restore the original mode before returning!! |
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*/ |
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@@ -510,6 +565,10 @@ int arm_dpm_setup(struct arm_dpm *dpm) |
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return ERROR_FAIL; |
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*register_get_last_cache_p(&target->reg_cache) = cache; |
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arm->mrc = dpm_mrc; |
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arm->mcr = dpm_mcr; |
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return ERROR_OK; |
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} |
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