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# |
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# Copyright (C) 2010 by Karl Kurbjun |
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# Copyright (C) 2009, 2010 by Øyvind Harboe |
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# Copyright (C) 2009 by David Brownell |
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# Copyright (C) 2009 by Magnus Lundin |
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# |
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# TI AM/DM37x |
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# http://www.ti.com/litv/pdf/sprugn4b |
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# |
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# This script is based on the AM3517 initialization. It should be considered |
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# preliminary since it needs more complete testing and only the basic |
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# operations work. |
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# |
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############################################################################### |
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# User modifiable parameters |
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############################################################################### |
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# This script uses the variable CHIPTYPE to determine whether this is an AM35x |
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# or DM37x target. If CHIPTYPE is not set it will error out. |
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if { [info exists CHIPTYPE] } { |
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if { [info exists CHIPNAME] } { |
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set _CHIPNAME $CHIPNAME |
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} else { |
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set _CHIPNAME $CHIPTYPE |
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} |
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switch $CHIPTYPE { |
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dm37x { |
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# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan |
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set _JRC_TAPID 0x0b89102f |
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} |
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am35x { |
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# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan |
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set _JRC_TAPID 0x0b7ae02f |
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} |
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default { |
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error "ERROR: CHIPTYPE was set, but it was not set to a valid value. Acceptable values are \"dm37x\" or \"am35x\"." |
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} |
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} |
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} else { |
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error "ERROR: CHIPTYPE was not defined. Please set CHIPTYPE to \"am35x\" for the AM35x or \"dm37x\" for the DM37x series in the board configuration." |
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} |
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# Run the adapter at the fastest acceptable speed with the slowest possible |
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# core clock. |
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adapter_khz 10 |
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############################################################################### |
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# JTAG setup |
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# The OpenOCD commands are described in the TAP Declaration section |
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# http://openocd.berlios.de/doc/html/TAP-Declaration.html |
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############################################################################### |
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# The AM/DM37x has an ICEpick module in it like many of TI's other devices. More |
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# can be read about this module in sprugn4b under chapter 27: "Debug and |
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# Emulation". The module is used to route the JTAG chain to the various |
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# subsystems in the chip. |
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source [find target/icepick.cfg] |
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# The TAP order should be described from the TDO connection in OpenOCD to the |
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# TDI pin. The OpenOCD FAQ describes this in more detail: |
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# http://openocd.berlios.de/doc/html/FAQ.html |
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# From SPRUGN4B CH27 the available secondary TAPs are in this order from TDO: |
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# |
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# Device | TAP number |
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# ---------|------------ |
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# DAP | 3 |
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# Sequencer| 2 Note: The sequencer is an ARM968 |
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# DSP | 1 |
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# D2D | 0 |
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# |
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# Right now the only secondary tap enabled is the DAP so the rest are left |
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# undescribed. |
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###### |
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# Start of Chain Description |
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# The Secondary TAPs all have enable functions defined for use with the ICEpick |
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# Only the DAP is enabled. The AM37xx does not have the Sequencer or DSP but |
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# the TAP numbers for ICEpick do not change. |
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# |
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# TODO: A disable function should also be added. |
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###### |
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# Secondary TAP: DAP is closest to the TDO output |
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# The TAP enable event also needs to be described |
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jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -disable |
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jtag configure $_CHIPNAME.dap -event tap-enable \ |
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"icepick_c_tapenable $_CHIPNAME.jrc 3" |
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# These taps are only present in the DM37x series. |
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if { $CHIPTYPE == "dm37x" } { |
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# Secondary TAP: Sequencer (ARM968) it is not in the chain by default |
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# The ICEpick can be used to enable it in the chain. |
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jtag newtap $_CHIPNAME arm2 -irlen 4 -ircapture 0x1 -irmask 0x0f -disable |
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jtag configure $_CHIPNAME.arm2 -event tap-enable \ |
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"icepick_c_tapenable $_CHIPNAME.jrc 2" |
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# Secondary TAP: C64x+ DSP - it is not in the chain by default (-disable) |
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# The ICEpick can be used to enable it in the chain. |
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jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable |
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jtag configure $_CHIPNAME.dsp -event tap-enable \ |
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"icepick_c_tapenable $_CHIPNAME.jrc 1" |
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} |
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# Secondary TAP: D2D it is not in the chain by default (-disable) |
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# The ICEpick can be used to enable it in the chain. |
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# This IRLEN is probably incorrect - not sure where the documentation is. |
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jtag newtap $_CHIPNAME d2d -irlen 4 -ircapture 0x1 -irmask 0x0f -disable |
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jtag configure $_CHIPNAME.d2d -event tap-enable \ |
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"icepick_c_tapenable $_CHIPNAME.jrc 0" |
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# Primary TAP: ICEpick - it is closest to TDI so last in the chain |
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ |
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-expected-id $_JRC_TAPID |
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###### |
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# End of Chain Description |
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###### |
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###### |
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# Start JTAG TAP events |
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###### |
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# some TCK tycles are required to activate the DEBUG power domain |
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jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100" |
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# Enable the DAP TAP |
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jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" |
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###### |
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# End JTAG TAP events |
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###### |
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############################################################################### |
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# Target Setup: |
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# This section is described in the OpenOCD documentation under CPU Configuration |
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# http://openocd.berlios.de/doc/html/CPU-Configuration.html |
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############################################################################### |
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# Create the CPU target to be used with GDB: Cortex-A8, using DAP |
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set _TARGETNAME $_CHIPNAME.cpu |
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target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap |
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# The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first |
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# 16K to be used as a scratchpad for OpenOCD. |
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$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000 |
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###### |
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# Start Target Reset Event Setup: |
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###### |
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# Set the JTAG clock down to 10 kHz to be sure that it will work with the |
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# slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up |
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# *after* PLL and clock tree setup. |
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$_TARGETNAME configure -event "reset-start" { adapter_khz 10 } |
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# Reset needs to be performed in in software. |
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# The AM/DM37x TRM (sprugn4b) describes the software reset in detail. |
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# PRM_RSTCTRL is described in table 3-425 on page 618. We assert RST_GS |
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# (bit 1 (in 31:0) ) to do a warm reset. |
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# Create a vaiable for the register address |
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set PRM_RSTCTRL 0x48307250 |
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# Describe the reset assert process: A value of 2 must be written |
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# (assert bit 1) to the physical address of PRM_RSTCTRL. |
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$_TARGETNAME configure -event \ |
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reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 2" |
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# After the reset is asserted we need to re-initialize debugging and speed up |
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# the JTAG clock. |
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$_TARGETNAME configure -event \ |
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reset-assert-post "amdm37x_dbginit $_TARGETNAME; adapter_khz 1000" |
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###### |
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# End Target Reset Event Setup: |
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###### |
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############################################################################### |
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# Target Functions |
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# Add any functions needed for the target here |
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############################################################################### |
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# Run this to enable invasive debugging. This is run automatically in the |
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# reset sequence. |
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proc amdm37x_dbginit {target} { |
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# General Cortex A8 debug initialisation |
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cortex_a8 dbginit |
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# Enable DBGEN signal. This signal is described in the ARM v7 TRM, but |
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# access to the signal appears to be implementation specific. TI does not |
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# describe this register much except a quick line that states DBGEM (sic) is |
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# at this address and this bit. |
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$target mww phys 0x5401d030 0x00002000 |
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} |
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