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@@ -1025,6 +1025,387 @@ int dap_lookup_cs_component(struct adiv5_dap *dap, int ap, |
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return retval; |
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} |
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static int dap_rom_display(struct command_context *cmd_ctx, |
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struct adiv5_dap *dap, int ap, uint32_t dbgbase, int depth) |
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{ |
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int retval; |
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uint32_t cid0, cid1, cid2, cid3, memtype, romentry; |
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uint16_t entry_offset; |
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int i; |
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char tabs[16 + 1]; |
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if (depth > 16) { |
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command_print(cmd_ctx, "\tTables too deep"); |
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return ERROR_FAIL; |
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} |
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for (i = 0; i < depth; ++i) |
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tabs[i] = '\t'; |
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tabs[i] = '\0'; |
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/* bit 16 of apid indicates a memory access port */ |
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if (dbgbase & 0x02) |
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command_print(cmd_ctx, "\t%sValid ROM table present", tabs); |
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else |
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command_print(cmd_ctx, "\t%sROM table in legacy format", tabs); |
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/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ |
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retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0); |
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if (retval != ERROR_OK) |
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return retval; |
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retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1); |
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if (retval != ERROR_OK) |
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return retval; |
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retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2); |
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if (retval != ERROR_OK) |
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return retval; |
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retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3); |
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if (retval != ERROR_OK) |
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return retval; |
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retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype); |
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if (retval != ERROR_OK) |
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return retval; |
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retval = dap_run(dap); |
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if (retval != ERROR_OK) |
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return retval; |
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if (!is_dap_cid_ok(cid3, cid2, cid1, cid0)) |
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command_print(cmd_ctx, "\t%sCID3 0x%02x" |
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", CID2 0x%02x" |
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", CID1 0x%02x" |
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", CID0 0x%02x", |
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tabs, |
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(unsigned)cid3, (unsigned)cid2, |
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(unsigned)cid1, (unsigned)cid0); |
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if (memtype & 0x01) |
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command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs); |
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else |
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command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs); |
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/* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */ |
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for (entry_offset = 0; ; entry_offset += 4) { |
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retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry); |
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if (retval != ERROR_OK) |
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return retval; |
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command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "", |
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tabs, entry_offset, romentry); |
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if (romentry & 0x01) { |
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uint32_t c_cid0, c_cid1, c_cid2, c_cid3; |
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uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4; |
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uint32_t component_base; |
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unsigned part_num; |
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char *type, *full; |
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component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000); |
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/* IDs are in last 4K section */ |
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retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0); |
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if (retval != ERROR_OK) { |
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command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32 |
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", the corresponding core might be turned off", tabs, component_base); |
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continue; |
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} |
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c_pid0 &= 0xff; |
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retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1); |
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if (retval != ERROR_OK) |
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return retval; |
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c_pid1 &= 0xff; |
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retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2); |
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if (retval != ERROR_OK) |
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return retval; |
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c_pid2 &= 0xff; |
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retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3); |
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if (retval != ERROR_OK) |
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return retval; |
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c_pid3 &= 0xff; |
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retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4); |
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if (retval != ERROR_OK) |
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return retval; |
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c_pid4 &= 0xff; |
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retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0); |
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if (retval != ERROR_OK) |
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return retval; |
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c_cid0 &= 0xff; |
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retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1); |
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if (retval != ERROR_OK) |
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return retval; |
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c_cid1 &= 0xff; |
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retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2); |
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if (retval != ERROR_OK) |
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return retval; |
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c_cid2 &= 0xff; |
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retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3); |
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if (retval != ERROR_OK) |
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return retval; |
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c_cid3 &= 0xff; |
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command_print(cmd_ctx, "\t%s\tComponent base address 0x%" PRIx32 ", " |
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"start address 0x%" PRIx32, tabs, component_base, |
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/* component may take multiple 4K pages */ |
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(uint32_t)(component_base - 0x1000*(c_pid4 >> 4))); |
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command_print(cmd_ctx, "\t%s\tComponent class is 0x%x, %s", |
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tabs, (c_cid1 >> 4) & 0xf, |
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/* See ARM IHI 0029B Table 3-3 */ |
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class_description[(c_cid1 >> 4) & 0xf]); |
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/* CoreSight component? */ |
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if (((c_cid1 >> 4) & 0x0f) == 9) { |
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uint32_t devtype; |
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unsigned minor; |
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char *major = "Reserved", *subtype = "Reserved"; |
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retval = mem_ap_read_atomic_u32(dap, |
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(component_base & 0xfffff000) | 0xfcc, |
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&devtype); |
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if (retval != ERROR_OK) |
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return retval; |
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minor = (devtype >> 4) & 0x0f; |
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switch (devtype & 0x0f) { |
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case 0: |
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major = "Miscellaneous"; |
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switch (minor) { |
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case 0: |
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subtype = "other"; |
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break; |
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case 4: |
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subtype = "Validation component"; |
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break; |
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} |
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break; |
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case 1: |
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major = "Trace Sink"; |
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switch (minor) { |
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case 0: |
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subtype = "other"; |
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break; |
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case 1: |
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subtype = "Port"; |
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break; |
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case 2: |
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subtype = "Buffer"; |
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break; |
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} |
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break; |
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case 2: |
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major = "Trace Link"; |
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switch (minor) { |
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case 0: |
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subtype = "other"; |
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break; |
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case 1: |
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subtype = "Funnel, router"; |
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break; |
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case 2: |
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subtype = "Filter"; |
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break; |
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case 3: |
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subtype = "FIFO, buffer"; |
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break; |
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} |
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break; |
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case 3: |
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major = "Trace Source"; |
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switch (minor) { |
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case 0: |
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subtype = "other"; |
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break; |
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case 1: |
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subtype = "Processor"; |
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break; |
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case 2: |
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subtype = "DSP"; |
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break; |
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case 3: |
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subtype = "Engine/Coprocessor"; |
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break; |
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case 4: |
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subtype = "Bus"; |
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break; |
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} |
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break; |
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case 4: |
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major = "Debug Control"; |
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switch (minor) { |
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case 0: |
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subtype = "other"; |
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break; |
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case 1: |
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subtype = "Trigger Matrix"; |
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break; |
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case 2: |
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subtype = "Debug Auth"; |
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break; |
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} |
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break; |
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case 5: |
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major = "Debug Logic"; |
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switch (minor) { |
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case 0: |
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subtype = "other"; |
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break; |
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case 1: |
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subtype = "Processor"; |
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break; |
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case 2: |
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subtype = "DSP"; |
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break; |
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case 3: |
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subtype = "Engine/Coprocessor"; |
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break; |
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} |
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break; |
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} |
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command_print(cmd_ctx, "\t%s\tType is 0x%02x, %s, %s", |
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tabs, devtype & 0xff, |
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major, subtype); |
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/* REVISIT also show 0xfc8 DevId */ |
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} |
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if (!is_dap_cid_ok(cid3, cid2, cid1, cid0)) |
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command_print(cmd_ctx, |
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"\t%s\tCID3 0%02x" |
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", CID2 0%02x" |
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", CID1 0%02x" |
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", CID0 0%02x", |
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tabs, |
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(int)c_cid3, |
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(int)c_cid2, |
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(int)c_cid1, |
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(int)c_cid0); |
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command_print(cmd_ctx, |
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"\t%s\tPeripheral ID[4..0] = hex " |
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"%02x %02x %02x %02x %02x", tabs, |
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(int)c_pid4, (int)c_pid3, (int)c_pid2, |
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(int)c_pid1, (int)c_pid0); |
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/* Part number interpretations are from Cortex |
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* core specs, the CoreSight components TRM |
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* (ARM DDI 0314H), CoreSight System Design |
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* Guide (ARM DGI 0012D) and ETM specs; also |
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* from chip observation (e.g. TI SDTI). |
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*/ |
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part_num = (c_pid0 & 0xff); |
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part_num |= (c_pid1 & 0x0f) << 8; |
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switch (part_num) { |
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case 0x000: |
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type = "Cortex-M3 NVIC"; |
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full = "(Interrupt Controller)"; |
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break; |
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case 0x001: |
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type = "Cortex-M3 ITM"; |
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full = "(Instrumentation Trace Module)"; |
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break; |
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case 0x002: |
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type = "Cortex-M3 DWT"; |
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full = "(Data Watchpoint and Trace)"; |
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break; |
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case 0x003: |
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type = "Cortex-M3 FBP"; |
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full = "(Flash Patch and Breakpoint)"; |
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break; |
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case 0x00c: |
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type = "Cortex-M4 SCS"; |
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full = "(System Control Space)"; |
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break; |
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case 0x00d: |
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type = "CoreSight ETM11"; |
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full = "(Embedded Trace)"; |
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break; |
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/* case 0x113: what? */ |
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case 0x120: /* from OMAP3 memmap */ |
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type = "TI SDTI"; |
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full = "(System Debug Trace Interface)"; |
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break; |
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case 0x343: /* from OMAP3 memmap */ |
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type = "TI DAPCTL"; |
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full = ""; |
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break; |
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case 0x906: |
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type = "Coresight CTI"; |
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full = "(Cross Trigger)"; |
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break; |
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case 0x907: |
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type = "Coresight ETB"; |
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full = "(Trace Buffer)"; |
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break; |
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case 0x908: |
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type = "Coresight CSTF"; |
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full = "(Trace Funnel)"; |
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break; |
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case 0x910: |
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type = "CoreSight ETM9"; |
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full = "(Embedded Trace)"; |
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break; |
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case 0x912: |
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type = "Coresight TPIU"; |
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full = "(Trace Port Interface Unit)"; |
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break; |
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case 0x913: |
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type = "Coresight ITM"; |
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full = "(Instrumentation Trace Macrocell)"; |
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break; |
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case 0x921: |
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type = "Cortex-A8 ETM"; |
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full = "(Embedded Trace)"; |
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break; |
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case 0x922: |
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type = "Cortex-A8 CTI"; |
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full = "(Cross Trigger)"; |
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break; |
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case 0x923: |
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type = "Cortex-M3 TPIU"; |
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full = "(Trace Port Interface Unit)"; |
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break; |
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case 0x924: |
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type = "Cortex-M3 ETM"; |
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full = "(Embedded Trace)"; |
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break; |
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case 0x925: |
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type = "Cortex-M4 ETM"; |
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full = "(Embedded Trace)"; |
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break; |
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case 0x930: |
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type = "Cortex-R4 ETM"; |
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full = "(Embedded Trace)"; |
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break; |
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case 0x9a1: |
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type = "Cortex-M4 TPUI"; |
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full = "(Trace Port Interface Unit)"; |
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break; |
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case 0xc08: |
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type = "Cortex-A8 Debug"; |
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full = "(Debug Unit)"; |
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break; |
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case 0xc09: |
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type = "Cortex-A9 Debug"; |
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full = "(Debug Unit)"; |
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break; |
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default: |
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type = "-*- unrecognized -*-"; |
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full = ""; |
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break; |
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} |
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command_print(cmd_ctx, "\t%s\tPart is %s %s", |
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tabs, type, full); |
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/* ROM Table? */ |
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if (((c_cid1 >> 4) & 0x0f) == 1) { |
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retval = dap_rom_display(cmd_ctx, dap, ap, component_base, depth + 1); |
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if (retval != ERROR_OK) |
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return retval; |
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} |
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} else { |
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if (romentry) |
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command_print(cmd_ctx, "\t%s\tComponent not present", tabs); |
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else |
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break; |
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} |
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} |
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command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs); |
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return ERROR_OK; |
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} |
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static int dap_info_command(struct command_context *cmd_ctx, |
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struct adiv5_dap *dap, int ap) |
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{ |
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@@ -1070,350 +1451,7 @@ static int dap_info_command(struct command_context *cmd_ctx, |
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romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF)); |
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if (romtable_present) { |
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uint32_t cid0, cid1, cid2, cid3, memtype, romentry; |
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uint16_t entry_offset; |
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/* bit 16 of apid indicates a memory access port */ |
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if (dbgbase & 0x02) |
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command_print(cmd_ctx, "\tValid ROM table present"); |
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else |
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command_print(cmd_ctx, "\tROM table in legacy format"); |
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|
|
|
|
|
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ |
|
|
|
retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
retval = dap_run(dap); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
|
|
|
|
if (!is_dap_cid_ok(cid3, cid2, cid1, cid0)) |
|
|
|
command_print(cmd_ctx, "\tCID3 0x%2.2x" |
|
|
|
", CID2 0x%2.2x" |
|
|
|
", CID1 0x%2.2x" |
|
|
|
", CID0 0x%2.2x", |
|
|
|
(unsigned) cid3, (unsigned)cid2, |
|
|
|
(unsigned) cid1, (unsigned) cid0); |
|
|
|
if (memtype & 0x01) |
|
|
|
command_print(cmd_ctx, "\tMEMTYPE system memory present on bus"); |
|
|
|
else |
|
|
|
command_print(cmd_ctx, "\tMEMTYPE System memory not present. " |
|
|
|
"Dedicated debug bus."); |
|
|
|
|
|
|
|
/* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */ |
|
|
|
entry_offset = 0; |
|
|
|
do { |
|
|
|
retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "", entry_offset, romentry); |
|
|
|
if (romentry & 0x01) { |
|
|
|
uint32_t c_cid0, c_cid1, c_cid2, c_cid3; |
|
|
|
uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4; |
|
|
|
uint32_t component_base; |
|
|
|
unsigned part_num; |
|
|
|
char *type, *full; |
|
|
|
|
|
|
|
component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000); |
|
|
|
|
|
|
|
/* IDs are in last 4K section */ |
|
|
|
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
c_pid0 &= 0xff; |
|
|
|
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
c_pid1 &= 0xff; |
|
|
|
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
c_pid2 &= 0xff; |
|
|
|
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
c_pid3 &= 0xff; |
|
|
|
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
c_pid4 &= 0xff; |
|
|
|
|
|
|
|
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
c_cid0 &= 0xff; |
|
|
|
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
c_cid1 &= 0xff; |
|
|
|
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
c_cid2 &= 0xff; |
|
|
|
retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
c_cid3 &= 0xff; |
|
|
|
|
|
|
|
command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 "," |
|
|
|
"start address 0x%" PRIx32, component_base, |
|
|
|
/* component may take multiple 4K pages */ |
|
|
|
component_base - 0x1000*(c_pid4 >> 4)); |
|
|
|
command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s", |
|
|
|
(int) (c_cid1 >> 4) & 0xf, |
|
|
|
/* See ARM IHI 0029B Table 3-3 */ |
|
|
|
class_description[(c_cid1 >> 4) & 0xf]); |
|
|
|
|
|
|
|
/* CoreSight component? */ |
|
|
|
if (((c_cid1 >> 4) & 0x0f) == 9) { |
|
|
|
uint32_t devtype; |
|
|
|
unsigned minor; |
|
|
|
char *major = "Reserved", *subtype = "Reserved"; |
|
|
|
|
|
|
|
retval = mem_ap_read_atomic_u32(dap, |
|
|
|
(component_base & 0xfffff000) | 0xfcc, |
|
|
|
&devtype); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
return retval; |
|
|
|
minor = (devtype >> 4) & 0x0f; |
|
|
|
switch (devtype & 0x0f) { |
|
|
|
case 0: |
|
|
|
major = "Miscellaneous"; |
|
|
|
switch (minor) { |
|
|
|
case 0: |
|
|
|
subtype = "other"; |
|
|
|
break; |
|
|
|
case 4: |
|
|
|
subtype = "Validation component"; |
|
|
|
break; |
|
|
|
} |
|
|
|
break; |
|
|
|
case 1: |
|
|
|
major = "Trace Sink"; |
|
|
|
switch (minor) { |
|
|
|
case 0: |
|
|
|
subtype = "other"; |
|
|
|
break; |
|
|
|
case 1: |
|
|
|
subtype = "Port"; |
|
|
|
break; |
|
|
|
case 2: |
|
|
|
subtype = "Buffer"; |
|
|
|
break; |
|
|
|
} |
|
|
|
break; |
|
|
|
case 2: |
|
|
|
major = "Trace Link"; |
|
|
|
switch (minor) { |
|
|
|
case 0: |
|
|
|
subtype = "other"; |
|
|
|
break; |
|
|
|
case 1: |
|
|
|
subtype = "Funnel, router"; |
|
|
|
break; |
|
|
|
case 2: |
|
|
|
subtype = "Filter"; |
|
|
|
break; |
|
|
|
case 3: |
|
|
|
subtype = "FIFO, buffer"; |
|
|
|
break; |
|
|
|
} |
|
|
|
break; |
|
|
|
case 3: |
|
|
|
major = "Trace Source"; |
|
|
|
switch (minor) { |
|
|
|
case 0: |
|
|
|
subtype = "other"; |
|
|
|
break; |
|
|
|
case 1: |
|
|
|
subtype = "Processor"; |
|
|
|
break; |
|
|
|
case 2: |
|
|
|
subtype = "DSP"; |
|
|
|
break; |
|
|
|
case 3: |
|
|
|
subtype = "Engine/Coprocessor"; |
|
|
|
break; |
|
|
|
case 4: |
|
|
|
subtype = "Bus"; |
|
|
|
break; |
|
|
|
} |
|
|
|
break; |
|
|
|
case 4: |
|
|
|
major = "Debug Control"; |
|
|
|
switch (minor) { |
|
|
|
case 0: |
|
|
|
subtype = "other"; |
|
|
|
break; |
|
|
|
case 1: |
|
|
|
subtype = "Trigger Matrix"; |
|
|
|
break; |
|
|
|
case 2: |
|
|
|
subtype = "Debug Auth"; |
|
|
|
break; |
|
|
|
} |
|
|
|
break; |
|
|
|
case 5: |
|
|
|
major = "Debug Logic"; |
|
|
|
switch (minor) { |
|
|
|
case 0: |
|
|
|
subtype = "other"; |
|
|
|
break; |
|
|
|
case 1: |
|
|
|
subtype = "Processor"; |
|
|
|
break; |
|
|
|
case 2: |
|
|
|
subtype = "DSP"; |
|
|
|
break; |
|
|
|
case 3: |
|
|
|
subtype = "Engine/Coprocessor"; |
|
|
|
break; |
|
|
|
} |
|
|
|
break; |
|
|
|
} |
|
|
|
command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s", |
|
|
|
(unsigned) (devtype & 0xff), |
|
|
|
major, subtype); |
|
|
|
/* REVISIT also show 0xfc8 DevId */ |
|
|
|
} |
|
|
|
|
|
|
|
if (!is_dap_cid_ok(cid3, cid2, cid1, cid0)) |
|
|
|
command_print(cmd_ctx, |
|
|
|
"\t\tCID3 0%2.2x" |
|
|
|
", CID2 0%2.2x" |
|
|
|
", CID1 0%2.2x" |
|
|
|
", CID0 0%2.2x", |
|
|
|
(int) c_cid3, |
|
|
|
(int) c_cid2, |
|
|
|
(int)c_cid1, |
|
|
|
(int)c_cid0); |
|
|
|
command_print(cmd_ctx, |
|
|
|
"\t\tPeripheral ID[4..0] = hex " |
|
|
|
"%2.2x %2.2x %2.2x %2.2x %2.2x", |
|
|
|
(int) c_pid4, (int) c_pid3, (int) c_pid2, |
|
|
|
(int) c_pid1, (int) c_pid0); |
|
|
|
|
|
|
|
/* Part number interpretations are from Cortex |
|
|
|
* core specs, the CoreSight components TRM |
|
|
|
* (ARM DDI 0314H), CoreSight System Design |
|
|
|
* Guide (ARM DGI 0012D) and ETM specs; also |
|
|
|
* from chip observation (e.g. TI SDTI). |
|
|
|
*/ |
|
|
|
part_num = (c_pid0 & 0xff); |
|
|
|
part_num |= (c_pid1 & 0x0f) << 8; |
|
|
|
switch (part_num) { |
|
|
|
case 0x000: |
|
|
|
type = "Cortex-M3 NVIC"; |
|
|
|
full = "(Interrupt Controller)"; |
|
|
|
break; |
|
|
|
case 0x001: |
|
|
|
type = "Cortex-M3 ITM"; |
|
|
|
full = "(Instrumentation Trace Module)"; |
|
|
|
break; |
|
|
|
case 0x002: |
|
|
|
type = "Cortex-M3 DWT"; |
|
|
|
full = "(Data Watchpoint and Trace)"; |
|
|
|
break; |
|
|
|
case 0x003: |
|
|
|
type = "Cortex-M3 FBP"; |
|
|
|
full = "(Flash Patch and Breakpoint)"; |
|
|
|
break; |
|
|
|
case 0x00c: |
|
|
|
type = "Cortex-M4 SCS"; |
|
|
|
full = "(System Control Space)"; |
|
|
|
break; |
|
|
|
case 0x00d: |
|
|
|
type = "CoreSight ETM11"; |
|
|
|
full = "(Embedded Trace)"; |
|
|
|
break; |
|
|
|
/* case 0x113: what? */ |
|
|
|
case 0x120: /* from OMAP3 memmap */ |
|
|
|
type = "TI SDTI"; |
|
|
|
full = "(System Debug Trace Interface)"; |
|
|
|
break; |
|
|
|
case 0x343: /* from OMAP3 memmap */ |
|
|
|
type = "TI DAPCTL"; |
|
|
|
full = ""; |
|
|
|
break; |
|
|
|
case 0x906: |
|
|
|
type = "Coresight CTI"; |
|
|
|
full = "(Cross Trigger)"; |
|
|
|
break; |
|
|
|
case 0x907: |
|
|
|
type = "Coresight ETB"; |
|
|
|
full = "(Trace Buffer)"; |
|
|
|
break; |
|
|
|
case 0x908: |
|
|
|
type = "Coresight CSTF"; |
|
|
|
full = "(Trace Funnel)"; |
|
|
|
break; |
|
|
|
case 0x910: |
|
|
|
type = "CoreSight ETM9"; |
|
|
|
full = "(Embedded Trace)"; |
|
|
|
break; |
|
|
|
case 0x912: |
|
|
|
type = "Coresight TPIU"; |
|
|
|
full = "(Trace Port Interface Unit)"; |
|
|
|
break; |
|
|
|
case 0x921: |
|
|
|
type = "Cortex-A8 ETM"; |
|
|
|
full = "(Embedded Trace)"; |
|
|
|
break; |
|
|
|
case 0x922: |
|
|
|
type = "Cortex-A8 CTI"; |
|
|
|
full = "(Cross Trigger)"; |
|
|
|
break; |
|
|
|
case 0x923: |
|
|
|
type = "Cortex-M3 TPIU"; |
|
|
|
full = "(Trace Port Interface Unit)"; |
|
|
|
break; |
|
|
|
case 0x924: |
|
|
|
type = "Cortex-M3 ETM"; |
|
|
|
full = "(Embedded Trace)"; |
|
|
|
break; |
|
|
|
case 0x925: |
|
|
|
type = "Cortex-M4 ETM"; |
|
|
|
full = "(Embedded Trace)"; |
|
|
|
break; |
|
|
|
case 0x930: |
|
|
|
type = "Cortex-R4 ETM"; |
|
|
|
full = "(Embedded Trace)"; |
|
|
|
break; |
|
|
|
case 0x9a1: |
|
|
|
type = "Cortex-M4 TPUI"; |
|
|
|
full = "(Trace Port Interface Unit)"; |
|
|
|
break; |
|
|
|
case 0xc08: |
|
|
|
type = "Cortex-A8 Debug"; |
|
|
|
full = "(Debug Unit)"; |
|
|
|
break; |
|
|
|
default: |
|
|
|
type = "-*- unrecognized -*-"; |
|
|
|
full = ""; |
|
|
|
break; |
|
|
|
} |
|
|
|
command_print(cmd_ctx, "\t\tPart is %s %s", |
|
|
|
type, full); |
|
|
|
} else { |
|
|
|
if (romentry) |
|
|
|
command_print(cmd_ctx, "\t\tComponent not present"); |
|
|
|
else |
|
|
|
command_print(cmd_ctx, "\t\tEnd of ROM table"); |
|
|
|
} |
|
|
|
entry_offset += 4; |
|
|
|
} while (romentry > 0); |
|
|
|
dap_rom_display(cmd_ctx, dap, ap, dbgbase, 0); |
|
|
|
} else |
|
|
|
command_print(cmd_ctx, "\tNo ROM table present"); |
|
|
|
dap_ap_select(dap, ap_old); |
|
|
|