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@@ -1428,7 +1428,7 @@ int arm7_9_debug_entry(target_t *target) |
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if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) |
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return ERROR_FAIL; |
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for (i=0; i<=15; i++) |
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for (i=0; i <= 15; i++) |
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{ |
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LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]); |
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buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]); |
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@@ -2362,7 +2362,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, |
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if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) |
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return ERROR_FAIL; |
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for (i=0; i<=last_reg; i++) |
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for (i=0; i <= last_reg; i++) |
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; |
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arm7_9->read_xpsr(target, &cpsr, 0); |
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@@ -2545,7 +2545,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size |
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if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) |
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return ERROR_FAIL; |
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for (i=0; i<=last_reg; i++) |
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for (i=0; i <= last_reg; i++) |
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; |
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arm7_9->read_xpsr(target, &cpsr, 0); |
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