|
|
@@ -104,11 +104,11 @@ proc stm32f3x_default_examine_end {} { |
|
|
|
|
|
|
|
proc stm32f3x_default_reset_init {} { |
|
|
|
# Configure PLL to boost clock to HSI x 8 (64 MHz) |
|
|
|
mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2] |
|
|
|
mwh 0x40021002 0x0100 ;# RCC_CR[31:16] = PLLON |
|
|
|
mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1] |
|
|
|
sleep 10 ;# Wait for PLL to lock |
|
|
|
mww 0x40021004 0x00380402 ;# RCC_CFGR |= SW[1] |
|
|
|
mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2] |
|
|
|
mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON |
|
|
|
mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1] |
|
|
|
sleep 10 ;# Wait for PLL to lock |
|
|
|
mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1] |
|
|
|
|
|
|
|
# Boost JTAG frequency |
|
|
|
adapter_khz 8000 |
|
|
|