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@@ -118,7 +118,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); |
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* S: in priviledged mode: store user-mode registers |
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* W=1: update the base register. W=0: leave the base register untouched |
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*/ |
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#define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | (S << 22) | (W << 21) | (Rn << 16) | (List)) |
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#define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) |
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/* Load multiple increment after |
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* Rn: base register |
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@@ -126,7 +126,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); |
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* S: in priviledged mode: store user-mode registers |
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* W=1: update the base register. W=0: leave the base register untouched |
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*/ |
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#define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | (S << 22) | (W << 21) | (Rn << 16) | (List)) |
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#define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) |
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/* MOV r8, r8 */ |
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#define ARMV4_5_NOP (0xe1a08008) |
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@@ -135,19 +135,19 @@ extern int armv4_5_invalidate_core_regs(target_t *target); |
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* R=1: SPSR R=0: CPSR |
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* Rn: target register |
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*/ |
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#define ARMV4_5_MRS(Rn, R) (0xe10f0000 | (R << 22) | (Rn << 12)) |
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#define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12)) |
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/* Store register |
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* Rd: register to store |
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* Rn: base register |
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*/ |
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#define ARMV4_5_STR(Rd, Rn) (0xe5800000 | (Rd << 12) | (Rn << 16)) |
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#define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16)) |
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/* Load register |
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* Rd: register to load |
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* Rn: base register |
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*/ |
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#define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | (Rd << 12) | (Rn << 16)) |
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#define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16)) |
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/* Move general purpose register to PSR |
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* R=1: SPSR R=0: CPSR |
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@@ -155,43 +155,43 @@ extern int armv4_5_invalidate_core_regs(target_t *target); |
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* 1: control field 2: extension field 4: status field 8: flags field |
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* Rm: source register |
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*/ |
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#define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | Rm | (Field << 16) | (R << 22)) |
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#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | (Rotate << 8) | (Field << 16) | (R << 22)) |
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#define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22)) |
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#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22)) |
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/* Load Register Halfword Immediate Post-Index |
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* Rd: register to load |
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* Rn: base register |
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*/ |
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#define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | (Rd << 12) | (Rn << 16)) |
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#define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16)) |
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/* Load Register Byte Immediate Post-Index |
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* Rd: register to load |
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* Rn: base register |
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*/ |
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#define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | (Rd << 12) | (Rn << 16)) |
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#define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16)) |
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/* Store register Halfword Immediate Post-Index |
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* Rd: register to store |
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* Rn: base register |
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*/ |
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#define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | (Rd << 12) | (Rn << 16)) |
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#define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16)) |
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/* Store register Byte Immediate Post-Index |
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* Rd: register to store |
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* Rn: base register |
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*/ |
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#define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | (Rd << 12) | (Rn << 16)) |
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#define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16)) |
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/* Branch (and Link) |
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* Im: Branch target (left-shifted by 2 bits, added to PC) |
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* L: 1: branch and link 0: branch only |
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*/ |
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#define ARMV4_5_B(Im, L) (0xea000000 | Im | (L << 24)) |
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#define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24)) |
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/* Branch and exchange (ARM state) |
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* Rm: register holding branch target address |
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*/ |
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#define ARMV4_5_BX(Rm) (0xe12fff10 | Rm) |
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#define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm)) |
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/* Move to ARM register from coprocessor |
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* CP: Coprocessor number |
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@@ -201,7 +201,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); |
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* CRm: second coprocessor operand |
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* op2: Second coprocessor opcode |
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*/ |
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#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | CRm | (op2 << 5) | (CP << 8) | (Rd << 12) | (CRn << 16) | (op1 << 21)) |
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#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) |
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/* Move to coprocessor from ARM register |
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* CP: Coprocessor number |
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@@ -211,7 +211,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); |
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* CRm: second coprocessor operand |
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* op2: Second coprocessor opcode |
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*/ |
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#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | CRm | (op2 << 5) | (CP << 8) | (Rd << 12) | (CRn << 16) | (op1 << 21)) |
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#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) |
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/* Thumb mode instructions |
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@@ -221,30 +221,30 @@ extern int armv4_5_invalidate_core_regs(target_t *target); |
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* Rd: source register |
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* Rn: base register |
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*/ |
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#define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16)) |
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#define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16)) |
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/* Load register (Thumb state) |
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* Rd: destination register |
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* Rn: base register |
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*/ |
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#define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16)) |
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#define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16)) |
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/* Load multiple (Thumb state) |
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* Rn: base register |
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* List: for each bit in list: store register |
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*/ |
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#define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16)) |
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#define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16)) |
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/* Load register with PC relative addressing |
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* Rd: register to load |
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*/ |
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#define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16)) |
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#define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16)) |
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/* Move hi register (Thumb mode) |
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* Rd: destination register |
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* Rm: source register |
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*/ |
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#define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16)) |
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#define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16)) |
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/* No operation (Thumb mode) |
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*/ |
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@@ -254,16 +254,16 @@ extern int armv4_5_invalidate_core_regs(target_t *target); |
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* Rd: destination register |
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* Im: 8-bit immediate value |
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*/ |
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#define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16)) |
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#define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16)) |
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/* Branch and Exchange |
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* Rm: register containing branch target |
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*/ |
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#define ARMV4_5_T_BX(Rm) ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16)) |
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#define ARMV4_5_T_BX(Rm) ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16)) |
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/* Branch (Thumb state) |
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* Imm: Branch target |
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*/ |
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#define ARMV4_5_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16)) |
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#define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16)) |
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#endif /* ARMV4_5_H */ |