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@@ -98,22 +98,16 @@ int armv7a_arch_state(struct target *target) |
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return ERROR_INVALID_ARGUMENTS; |
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} |
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LOG_USER("target halted in %s state due to %s, current mode: %s\n" |
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"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" |
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"MMU: %s, D-Cache: %s, I-Cache: %s", |
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armv4_5_state_strings[armv4_5->core_state], |
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Jim_Nvp_value2name_simple(nvp_target_debug_reason, |
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target->debug_reason)->name, |
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arm_mode_name(armv4_5->core_mode), |
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buf_get_u32(armv4_5->cpsr->value, 0, 32), |
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buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), |
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armv4_5_arch_state(target); |
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LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s", |
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state[armv7a->armv4_5_mmu.mmu_enabled], |
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state[armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], |
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state[armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled]); |
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if (armv4_5->core_mode == ARMV4_5_MODE_ABT) |
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armv7a_show_fault_registers(target); |
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else if (target->debug_reason == DBG_REASON_WATCHPOINT) |
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if (target->debug_reason == DBG_REASON_WATCHPOINT) |
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LOG_USER("Watchpoint triggered at PC %#08x", |
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(unsigned) armv7a->dpm.wp_pc); |
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