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/*************************************************************************** |
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* Copyright (C) 2013 Synapse Product Development * |
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* Andrey Smirnov <andrew.smironv@gmail.com> * |
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* * |
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* This program is free software; you can redistribute it and/or modify * |
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* it under the terms of the GNU General Public License as published by * |
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* the Free Software Foundation; either version 2 of the License, or * |
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* (at your option) any later version. * |
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* * |
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* This program is distributed in the hope that it will be useful, * |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of * |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
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* GNU General Public License for more details. * |
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* * |
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* You should have received a copy of the GNU General Public License * |
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* along with this program; if not, write to the * |
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* Free Software Foundation, Inc., * |
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * |
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***************************************************************************/ |
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#ifdef HAVE_CONFIG_H |
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#include "config.h" |
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#endif |
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#include "imp.h" |
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enum { |
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NRF51_FLASH_BASE = 0x00000000, |
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}; |
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enum nrf51_ficr_registers { |
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NRF51_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */ |
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#define NRF51_FICR_REG(offset) (NRF51_FICR_BASE + offset) |
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NRF51_FICR_CODEPAGESIZE = NRF51_FICR_REG(0x010), |
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NRF51_FICR_CODESIZE = NRF51_FICR_REG(0x014), |
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NRF51_FICR_CLENR0 = NRF51_FICR_REG(0x028), |
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NRF51_FICR_PPFC = NRF51_FICR_REG(0x02C), |
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NRF51_FICR_NUMRAMBLOCK = NRF51_FICR_REG(0x034), |
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NRF51_FICR_SIZERAMBLOCK0 = NRF51_FICR_REG(0x038), |
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NRF51_FICR_SIZERAMBLOCK1 = NRF51_FICR_REG(0x03C), |
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NRF51_FICR_SIZERAMBLOCK2 = NRF51_FICR_REG(0x040), |
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NRF51_FICR_SIZERAMBLOCK3 = NRF51_FICR_REG(0x044), |
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NRF51_FICR_CONFIGID = NRF51_FICR_REG(0x05C), |
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NRF51_FICR_DEVICEID0 = NRF51_FICR_REG(0x060), |
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NRF51_FICR_DEVICEID1 = NRF51_FICR_REG(0x064), |
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NRF51_FICR_ER0 = NRF51_FICR_REG(0x080), |
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NRF51_FICR_ER1 = NRF51_FICR_REG(0x084), |
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NRF51_FICR_ER2 = NRF51_FICR_REG(0x088), |
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NRF51_FICR_ER3 = NRF51_FICR_REG(0x08C), |
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NRF51_FICR_IR0 = NRF51_FICR_REG(0x090), |
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NRF51_FICR_IR1 = NRF51_FICR_REG(0x094), |
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NRF51_FICR_IR2 = NRF51_FICR_REG(0x098), |
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NRF51_FICR_IR3 = NRF51_FICR_REG(0x09C), |
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NRF51_FICR_DEVICEADDRTYPE = NRF51_FICR_REG(0x0A0), |
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NRF51_FICR_DEVICEADDR0 = NRF51_FICR_REG(0x0A4), |
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NRF51_FICR_DEVICEADDR1 = NRF51_FICR_REG(0x0A8), |
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NRF51_FICR_OVERRIDEN = NRF51_FICR_REG(0x0AC), |
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NRF51_FICR_NRF_1MBIT0 = NRF51_FICR_REG(0x0B0), |
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NRF51_FICR_NRF_1MBIT1 = NRF51_FICR_REG(0x0B4), |
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NRF51_FICR_NRF_1MBIT2 = NRF51_FICR_REG(0x0B8), |
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NRF51_FICR_NRF_1MBIT3 = NRF51_FICR_REG(0x0BC), |
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NRF51_FICR_NRF_1MBIT4 = NRF51_FICR_REG(0x0C0), |
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NRF51_FICR_BLE_1MBIT0 = NRF51_FICR_REG(0x0EC), |
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NRF51_FICR_BLE_1MBIT1 = NRF51_FICR_REG(0x0F0), |
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NRF51_FICR_BLE_1MBIT2 = NRF51_FICR_REG(0x0F4), |
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NRF51_FICR_BLE_1MBIT3 = NRF51_FICR_REG(0x0F8), |
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NRF51_FICR_BLE_1MBIT4 = NRF51_FICR_REG(0x0FC), |
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}; |
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enum nrf51_uicr_registers { |
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NRF51_UICR_BASE = 0x10001000, /* User Information |
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* Configuration Regsters */ |
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#define NRF51_UICR_REG(offset) (NRF51_UICR_BASE + offset) |
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NRF51_UICR_CLENR0 = NRF51_UICR_REG(0x000), |
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NRF51_UICR_RBPCONF = NRF51_UICR_REG(0x004), |
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NRF51_UICR_XTALFREQ = NRF51_UICR_REG(0x008), |
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NRF51_UICR_FWID = NRF51_UICR_REG(0x010), |
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}; |
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enum nrf51_nvmc_registers { |
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NRF51_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory |
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* Controller Regsters */ |
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#define NRF51_NVMC_REG(offset) (NRF51_NVMC_BASE + offset) |
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NRF51_NVMC_READY = NRF51_NVMC_REG(0x400), |
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NRF51_NVMC_CONFIG = NRF51_NVMC_REG(0x504), |
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NRF51_NVMC_ERASEPAGE = NRF51_NVMC_REG(0x508), |
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NRF51_NVMC_ERASEALL = NRF51_NVMC_REG(0x50C), |
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NRF51_NVMC_ERASEUICR = NRF51_NVMC_REG(0x514), |
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}; |
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enum nrf51_nvmc_config_bits { |
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NRF51_NVMC_CONFIG_REN = 0x00, |
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NRF51_NVMC_CONFIG_WEN = 0x01, |
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NRF51_NVMC_CONFIG_EEN = 0x02, |
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}; |
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struct nrf51_info { |
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uint32_t code_page_size; |
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uint32_t code_memory_size; |
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bool probed; |
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struct target *target; |
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}; |
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static int nrf51_probe(struct flash_bank *bank); |
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static int nrf51_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf51_info **chip) |
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{ |
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if (bank->target->state != TARGET_HALTED) { |
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LOG_ERROR("Target not halted"); |
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return ERROR_TARGET_NOT_HALTED; |
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} |
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*chip = (struct nrf51_info *)bank->driver_priv; |
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if (!(*chip)->probed) |
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return nrf51_probe(bank); |
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return ERROR_OK; |
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} |
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static int nrf51_wait_for_nvmc(struct nrf51_info *chip) |
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{ |
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uint32_t ready; |
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int res; |
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int timeout = 100; |
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do { |
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res = target_read_u32(chip->target, NRF51_NVMC_READY, &ready); |
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if (res != ERROR_OK) { |
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LOG_ERROR("Couldn't read NVMC_READY register"); |
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return res; |
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} |
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if (ready == 0x00000001) |
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return ERROR_OK; |
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alive_sleep(1); |
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} while (timeout--); |
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return ERROR_FLASH_BUSY; |
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} |
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static int nrf51_nvmc_erase_enable(struct nrf51_info *chip) |
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{ |
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int res; |
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res = target_write_u32(chip->target, |
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NRF51_NVMC_CONFIG, |
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NRF51_NVMC_CONFIG_EEN); |
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if (res != ERROR_OK) { |
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LOG_ERROR("Failed to enable erase operation"); |
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return res; |
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} |
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/* |
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According to NVMC examples in Nordic SDK busy status must be |
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checked after writing to NVMC_CONFIG |
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*/ |
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res = nrf51_wait_for_nvmc(chip); |
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if (res != ERROR_OK) |
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LOG_ERROR("Erase enable did not complete"); |
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return res; |
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} |
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static int nrf51_nvmc_write_enable(struct nrf51_info *chip) |
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{ |
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int res; |
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res = target_write_u32(chip->target, |
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NRF51_NVMC_CONFIG, |
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NRF51_NVMC_CONFIG_WEN); |
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if (res != ERROR_OK) { |
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LOG_ERROR("Failed to enable write operation"); |
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return res; |
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} |
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/* |
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According to NVMC examples in Nordic SDK busy status must be |
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checked after writing to NVMC_CONFIG |
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*/ |
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res = nrf51_wait_for_nvmc(chip); |
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if (res != ERROR_OK) |
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LOG_ERROR("Write enable did not complete"); |
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return res; |
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} |
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static int nrf51_nvmc_read_only(struct nrf51_info *chip) |
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{ |
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int res; |
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res = target_write_u32(chip->target, |
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NRF51_NVMC_CONFIG, |
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NRF51_NVMC_CONFIG_REN); |
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if (res != ERROR_OK) { |
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LOG_ERROR("Failed to enable read-only operation"); |
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return res; |
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} |
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/* |
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According to NVMC examples in Nordic SDK busy status must be |
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checked after writing to NVMC_CONFIG |
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*/ |
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res = nrf51_wait_for_nvmc(chip); |
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if (res != ERROR_OK) |
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LOG_ERROR("Read only enable did not complete"); |
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return res; |
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} |
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static int nrf51_nvmc_generic_erase(struct nrf51_info *chip, |
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uint32_t erase_register, uint32_t erase_value) |
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{ |
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int res; |
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res = nrf51_nvmc_erase_enable(chip); |
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if (res != ERROR_OK) |
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goto error; |
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res = target_write_u32(chip->target, |
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erase_register, |
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erase_value); |
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if (res != ERROR_OK) |
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goto set_read_only; |
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res = nrf51_wait_for_nvmc(chip); |
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if (res != ERROR_OK) |
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goto set_read_only; |
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return nrf51_nvmc_read_only(chip); |
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set_read_only: |
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nrf51_nvmc_read_only(chip); |
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error: |
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LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32, |
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erase_register, erase_value); |
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return ERROR_FAIL; |
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} |
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static int nrf51_protect_check(struct flash_bank *bank) |
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{ |
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int res; |
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uint32_t clenr0; |
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struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv; |
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assert(chip != NULL); |
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res = target_read_u32(chip->target, NRF51_FICR_CLENR0, |
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&clenr0); |
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if (res != ERROR_OK) { |
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LOG_ERROR("Couldn't read code region 0 size[FICR]"); |
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return res; |
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} |
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if (clenr0 == 0xFFFFFFFF) { |
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res = target_read_u32(chip->target, NRF51_UICR_CLENR0, |
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&clenr0); |
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if (res != ERROR_OK) { |
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LOG_ERROR("Couldn't read code region 0 size[UICR]"); |
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return res; |
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} |
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} |
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for (int i = 0; i < bank->num_sectors; i++) |
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bank->sectors[i].is_protected = |
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clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0; |
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return ERROR_OK; |
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} |
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static int nrf51_protect(struct flash_bank *bank, int set, int first, int last) |
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{ |
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int res; |
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uint32_t clenr0, ppfc; |
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struct nrf51_info *chip; |
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res = nrf51_get_probed_chip_if_halted(bank, &chip); |
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if (res != ERROR_OK) |
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return res; |
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if (first != 0) { |
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LOG_ERROR("Code region 0 must start at the begining of the bank"); |
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return ERROR_FAIL; |
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} |
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res = target_read_u32(chip->target, NRF51_FICR_PPFC, |
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&ppfc); |
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if (res != ERROR_OK) { |
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LOG_ERROR("Couldn't read PPFC register"); |
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return res; |
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} |
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if ((ppfc & 0xFF) == 0x00) { |
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LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings"); |
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return ERROR_FAIL; |
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}; |
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res = target_read_u32(chip->target, NRF51_UICR_CLENR0, |
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&clenr0); |
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if (res != ERROR_OK) { |
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LOG_ERROR("Couldn't read code region 0 size[UICR]"); |
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return res; |
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} |
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if (clenr0 == 0xFFFFFFFF) { |
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res = target_write_u32(chip->target, NRF51_UICR_CLENR0, |
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clenr0); |
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if (res != ERROR_OK) { |
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LOG_ERROR("Couldn't write code region 0 size[UICR]"); |
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return res; |
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} |
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} else { |
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LOG_ERROR("You need to perform chip erase before changing the protection settings"); |
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} |
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nrf51_protect_check(bank); |
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return ERROR_OK; |
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} |
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static int nrf51_probe(struct flash_bank *bank) |
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{ |
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uint32_t id; |
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int res; |
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struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv; |
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res = target_read_u32(chip->target, NRF51_FICR_DEVICEID0, &id); |
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if (res != ERROR_OK) { |
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LOG_ERROR("Couldn't read Device ID 0 register"); |
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return res; |
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} |
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res = target_read_u32(chip->target, NRF51_FICR_DEVICEID1, &id); |
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if (res != ERROR_OK) { |
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LOG_ERROR("Couldn't read Device ID 1 register"); |
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return res; |
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} |
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res = target_read_u32(chip->target, NRF51_FICR_CODEPAGESIZE, |
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&chip->code_page_size); |
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if (res != ERROR_OK) { |
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LOG_ERROR("Couldn't read code page size"); |
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return res; |
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} |
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res = target_read_u32(chip->target, NRF51_FICR_CODESIZE, |
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&chip->code_memory_size); |
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if (res != ERROR_OK) { |
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LOG_ERROR("Couldn't read code memory size"); |
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return res; |
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} |
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bank->size = chip->code_memory_size * 1024; |
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bank->num_sectors = bank->size / chip->code_page_size; |
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bank->sectors = calloc(bank->num_sectors, |
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sizeof((bank->sectors)[0])); |
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if (!bank->sectors) |
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return ERROR_FLASH_BANK_NOT_PROBED; |
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/* Fill out the sector information: all NRF51 sectors are the same size and |
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* there is always a fixed number of them. */ |
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for (int i = 0; i < bank->num_sectors; i++) { |
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bank->sectors[i].size = chip->code_page_size; |
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bank->sectors[i].offset = i * chip->code_page_size; |
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/* mark as unknown */ |
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bank->sectors[i].is_erased = -1; |
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bank->sectors[i].is_protected = -1; |
|
|
|
} |
|
|
|
|
|
|
|
nrf51_protect_check(bank); |
|
|
|
|
|
|
|
chip->probed = true; |
|
|
|
|
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
static int nrf51_auto_probe(struct flash_bank *bank) |
|
|
|
{ |
|
|
|
struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv; |
|
|
|
|
|
|
|
if (chip->probed) |
|
|
|
return ERROR_OK; |
|
|
|
|
|
|
|
return nrf51_probe(bank); |
|
|
|
} |
|
|
|
|
|
|
|
static struct flash_sector *nrf51_find_sector_by_address(struct flash_bank *bank, uint32_t address) |
|
|
|
{ |
|
|
|
struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv; |
|
|
|
|
|
|
|
for (int i = 0; i < bank->num_sectors; i++) |
|
|
|
if (bank->sectors[i].offset <= address && |
|
|
|
address < (bank->sectors[i].offset + chip->code_page_size)) |
|
|
|
return &bank->sectors[i]; |
|
|
|
return NULL; |
|
|
|
} |
|
|
|
|
|
|
|
static int nrf51_erase_all(struct nrf51_info *chip) |
|
|
|
{ |
|
|
|
return nrf51_nvmc_generic_erase(chip, |
|
|
|
NRF51_NVMC_ERASEALL, |
|
|
|
0x00000001); |
|
|
|
} |
|
|
|
|
|
|
|
static int nrf51_erase_page(struct nrf51_info *chip, struct flash_sector *sector) |
|
|
|
{ |
|
|
|
int res; |
|
|
|
|
|
|
|
if (sector->is_protected) |
|
|
|
return ERROR_FAIL; |
|
|
|
|
|
|
|
res = nrf51_nvmc_generic_erase(chip, |
|
|
|
NRF51_NVMC_ERASEPAGE, |
|
|
|
sector->offset); |
|
|
|
if (res == ERROR_OK) |
|
|
|
sector->is_erased = 1; |
|
|
|
|
|
|
|
return res; |
|
|
|
} |
|
|
|
|
|
|
|
static int nrf51_write_page(struct flash_bank *bank, uint32_t offset, uint8_t *buffer) |
|
|
|
{ |
|
|
|
assert(offset % 4 == 0); |
|
|
|
|
|
|
|
int res = ERROR_FAIL; |
|
|
|
struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv; |
|
|
|
struct flash_sector *sector = nrf51_find_sector_by_address(bank, offset); |
|
|
|
|
|
|
|
if (!sector) |
|
|
|
goto error; |
|
|
|
|
|
|
|
if (sector->is_protected) |
|
|
|
goto error; |
|
|
|
|
|
|
|
if (!sector->is_erased) { |
|
|
|
res = nrf51_erase_page(chip, sector); |
|
|
|
if (res != ERROR_OK) |
|
|
|
goto error; |
|
|
|
} |
|
|
|
|
|
|
|
res = nrf51_nvmc_write_enable(chip); |
|
|
|
if (res != ERROR_OK) |
|
|
|
goto error; |
|
|
|
|
|
|
|
sector->is_erased = 0; |
|
|
|
res = target_write_memory(bank->target, offset, 4, |
|
|
|
chip->code_page_size / 4, buffer); |
|
|
|
if (res != ERROR_OK) |
|
|
|
goto set_read_only; |
|
|
|
|
|
|
|
return nrf51_nvmc_read_only(chip); |
|
|
|
|
|
|
|
set_read_only: |
|
|
|
nrf51_nvmc_read_only(chip); |
|
|
|
error: |
|
|
|
LOG_ERROR("Failed to write sector @ 0x%08"PRIx32, sector->offset); |
|
|
|
return res; |
|
|
|
} |
|
|
|
|
|
|
|
static int nrf51_erase(struct flash_bank *bank, int first, int last) |
|
|
|
{ |
|
|
|
int res; |
|
|
|
struct nrf51_info *chip; |
|
|
|
|
|
|
|
res = nrf51_get_probed_chip_if_halted(bank, &chip); |
|
|
|
if (res != ERROR_OK) |
|
|
|
return res; |
|
|
|
|
|
|
|
/* For each sector to be erased */ |
|
|
|
for (int s = first; s <= last && res == ERROR_OK; s++) |
|
|
|
res = nrf51_erase_page(chip, &bank->sectors[s]); |
|
|
|
|
|
|
|
return res; |
|
|
|
} |
|
|
|
|
|
|
|
static int nrf51_write(struct flash_bank *bank, uint8_t *buffer, |
|
|
|
uint32_t offset, uint32_t count) |
|
|
|
{ |
|
|
|
int res; |
|
|
|
struct { |
|
|
|
uint32_t start, end; |
|
|
|
} region; |
|
|
|
struct nrf51_info *chip; |
|
|
|
|
|
|
|
res = nrf51_get_probed_chip_if_halted(bank, &chip); |
|
|
|
if (res != ERROR_OK) |
|
|
|
return res; |
|
|
|
|
|
|
|
region.start = offset; |
|
|
|
region.end = offset + count; |
|
|
|
|
|
|
|
struct { |
|
|
|
size_t length; |
|
|
|
uint8_t *buffer; |
|
|
|
} start_extra, end_extra; |
|
|
|
|
|
|
|
start_extra.length = region.start % chip->code_page_size; |
|
|
|
start_extra.buffer = buffer; |
|
|
|
end_extra.length = region.end % chip->code_page_size; |
|
|
|
end_extra.buffer = buffer + count - end_extra.length; |
|
|
|
|
|
|
|
if (start_extra.length) { |
|
|
|
uint8_t page[chip->code_page_size]; |
|
|
|
|
|
|
|
res = target_read_memory(bank->target, |
|
|
|
region.start - start_extra.length, |
|
|
|
1, start_extra.length, page); |
|
|
|
if (res != ERROR_OK) |
|
|
|
return res; |
|
|
|
|
|
|
|
memcpy(page + start_extra.length, |
|
|
|
start_extra.buffer, |
|
|
|
chip->code_page_size - start_extra.length); |
|
|
|
|
|
|
|
res = nrf51_write_page(bank, |
|
|
|
region.start - start_extra.length, |
|
|
|
page); |
|
|
|
if (res != ERROR_OK) |
|
|
|
return res; |
|
|
|
} |
|
|
|
|
|
|
|
if (end_extra.length) { |
|
|
|
uint8_t page[chip->code_page_size]; |
|
|
|
|
|
|
|
/* Retrieve the full row contents from Flash */ |
|
|
|
res = target_read_memory(bank->target, |
|
|
|
region.end, |
|
|
|
1, |
|
|
|
(chip->code_page_size - end_extra.length), |
|
|
|
page + end_extra.length); |
|
|
|
if (res != ERROR_OK) |
|
|
|
return res; |
|
|
|
|
|
|
|
memcpy(page, end_extra.buffer, end_extra.length); |
|
|
|
|
|
|
|
res = nrf51_write_page(bank, |
|
|
|
region.end - end_extra.length, |
|
|
|
page); |
|
|
|
if (res != ERROR_OK) |
|
|
|
return res; |
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
region.start += start_extra.length; |
|
|
|
region.end -= end_extra.length; |
|
|
|
|
|
|
|
for (uint32_t address = region.start; address < region.end; |
|
|
|
address += chip->code_page_size) { |
|
|
|
res = nrf51_write_page(bank, address, &buffer[address - region.start]); |
|
|
|
|
|
|
|
if (res != ERROR_OK) |
|
|
|
return res; |
|
|
|
|
|
|
|
} |
|
|
|
|
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
FLASH_BANK_COMMAND_HANDLER(nrf51_flash_bank_command) |
|
|
|
{ |
|
|
|
struct nrf51_info *chip; |
|
|
|
|
|
|
|
/* Create a new chip */ |
|
|
|
chip = calloc(1, sizeof(*chip)); |
|
|
|
if (!chip) |
|
|
|
return ERROR_FAIL; |
|
|
|
|
|
|
|
chip->target = bank->target; |
|
|
|
chip->probed = false; |
|
|
|
|
|
|
|
bank->driver_priv = chip; |
|
|
|
|
|
|
|
if (bank->base != NRF51_FLASH_BASE) { |
|
|
|
LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32 |
|
|
|
"[nrf51 series] )", |
|
|
|
bank->base, NRF51_FLASH_BASE); |
|
|
|
return ERROR_FAIL; |
|
|
|
} |
|
|
|
|
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
COMMAND_HANDLER(nrf51_handle_mass_erase_command) |
|
|
|
{ |
|
|
|
int res; |
|
|
|
struct flash_bank *bank; |
|
|
|
|
|
|
|
res = get_flash_bank_by_num(0, &bank); |
|
|
|
if (res != ERROR_OK) |
|
|
|
return res; |
|
|
|
|
|
|
|
struct nrf51_info *chip; |
|
|
|
|
|
|
|
res = nrf51_get_probed_chip_if_halted(bank, &chip); |
|
|
|
if (res != ERROR_OK) |
|
|
|
return res; |
|
|
|
|
|
|
|
uint32_t ppfc; |
|
|
|
|
|
|
|
res = target_read_u32(chip->target, NRF51_FICR_PPFC, |
|
|
|
&ppfc); |
|
|
|
if (res != ERROR_OK) { |
|
|
|
LOG_ERROR("Couldn't read PPFC register"); |
|
|
|
return res; |
|
|
|
} |
|
|
|
|
|
|
|
if ((ppfc & 0xFF) == 0x00) { |
|
|
|
LOG_ERROR("Code region 0 size was pre-programmed at the factory, " |
|
|
|
"mass erase command won't work."); |
|
|
|
return ERROR_FAIL; |
|
|
|
}; |
|
|
|
|
|
|
|
res = nrf51_erase_all(chip); |
|
|
|
if (res != ERROR_OK) { |
|
|
|
LOG_ERROR("Failed to erase the chip"); |
|
|
|
nrf51_protect_check(bank); |
|
|
|
return res; |
|
|
|
} |
|
|
|
|
|
|
|
for (int i = 0; i < bank->num_sectors; i++) |
|
|
|
bank->sectors[i].is_erased = 1; |
|
|
|
|
|
|
|
return nrf51_protect_check(bank); |
|
|
|
} |
|
|
|
|
|
|
|
static int nrf51_info(struct flash_bank *bank, char *buf, int buf_size) |
|
|
|
{ |
|
|
|
int res; |
|
|
|
|
|
|
|
struct nrf51_info *chip; |
|
|
|
|
|
|
|
res = nrf51_get_probed_chip_if_halted(bank, &chip); |
|
|
|
if (res != ERROR_OK) |
|
|
|
return res; |
|
|
|
|
|
|
|
struct { |
|
|
|
uint32_t address, value; |
|
|
|
} ficr[] = { |
|
|
|
{ .address = NRF51_FICR_CODEPAGESIZE }, |
|
|
|
{ .address = NRF51_FICR_CODESIZE }, |
|
|
|
{ .address = NRF51_FICR_CLENR0 }, |
|
|
|
{ .address = NRF51_FICR_PPFC }, |
|
|
|
{ .address = NRF51_FICR_NUMRAMBLOCK }, |
|
|
|
{ .address = NRF51_FICR_SIZERAMBLOCK0 }, |
|
|
|
{ .address = NRF51_FICR_SIZERAMBLOCK1 }, |
|
|
|
{ .address = NRF51_FICR_SIZERAMBLOCK2 }, |
|
|
|
{ .address = NRF51_FICR_SIZERAMBLOCK3 }, |
|
|
|
{ .address = NRF51_FICR_CONFIGID }, |
|
|
|
{ .address = NRF51_FICR_DEVICEID0 }, |
|
|
|
{ .address = NRF51_FICR_DEVICEID1 }, |
|
|
|
{ .address = NRF51_FICR_ER0 }, |
|
|
|
{ .address = NRF51_FICR_ER1 }, |
|
|
|
{ .address = NRF51_FICR_ER2 }, |
|
|
|
{ .address = NRF51_FICR_ER3 }, |
|
|
|
{ .address = NRF51_FICR_IR0 }, |
|
|
|
{ .address = NRF51_FICR_IR1 }, |
|
|
|
{ .address = NRF51_FICR_IR2 }, |
|
|
|
{ .address = NRF51_FICR_IR3 }, |
|
|
|
{ .address = NRF51_FICR_DEVICEADDRTYPE }, |
|
|
|
{ .address = NRF51_FICR_DEVICEADDR0 }, |
|
|
|
{ .address = NRF51_FICR_DEVICEADDR1 }, |
|
|
|
{ .address = NRF51_FICR_OVERRIDEN }, |
|
|
|
{ .address = NRF51_FICR_NRF_1MBIT0 }, |
|
|
|
{ .address = NRF51_FICR_NRF_1MBIT1 }, |
|
|
|
{ .address = NRF51_FICR_NRF_1MBIT2 }, |
|
|
|
{ .address = NRF51_FICR_NRF_1MBIT3 }, |
|
|
|
{ .address = NRF51_FICR_NRF_1MBIT4 }, |
|
|
|
{ .address = NRF51_FICR_BLE_1MBIT0 }, |
|
|
|
{ .address = NRF51_FICR_BLE_1MBIT1 }, |
|
|
|
{ .address = NRF51_FICR_BLE_1MBIT2 }, |
|
|
|
{ .address = NRF51_FICR_BLE_1MBIT3 }, |
|
|
|
{ .address = NRF51_FICR_BLE_1MBIT4 }, |
|
|
|
}, uicr[] = { |
|
|
|
{ .address = NRF51_UICR_CLENR0, }, |
|
|
|
{ .address = NRF51_UICR_RBPCONF }, |
|
|
|
{ .address = NRF51_UICR_XTALFREQ }, |
|
|
|
{ .address = NRF51_UICR_FWID }, |
|
|
|
}; |
|
|
|
|
|
|
|
for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) { |
|
|
|
res = target_read_u32(chip->target, ficr[i].address, |
|
|
|
&ficr[i].value); |
|
|
|
if (res != ERROR_OK) { |
|
|
|
LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address); |
|
|
|
return res; |
|
|
|
} |
|
|
|
} |
|
|
|
|
|
|
|
for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) { |
|
|
|
res = target_read_u32(chip->target, uicr[i].address, |
|
|
|
&uicr[i].value); |
|
|
|
if (res != ERROR_OK) { |
|
|
|
LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address); |
|
|
|
return res; |
|
|
|
} |
|
|
|
} |
|
|
|
|
|
|
|
snprintf(buf, buf_size, |
|
|
|
"\n[factory information control block]\n\n" |
|
|
|
"code page size: %"PRIu32"B\n" |
|
|
|
"code memory size: %"PRIu32"kB\n" |
|
|
|
"code region 0 size: %"PRIu32"kB\n" |
|
|
|
"pre-programmed code: %s\n" |
|
|
|
"number of ram blocks: %"PRIu32"\n" |
|
|
|
"ram block 0 size: %"PRIu32"B\n" |
|
|
|
"ram block 1 size: %"PRIu32"B\n" |
|
|
|
"ram block 2 size: %"PRIu32"B\n" |
|
|
|
"ram block 3 size: %"PRIu32 "B\n" |
|
|
|
"encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n" |
|
|
|
"identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n" |
|
|
|
"device address type: 0x%"PRIx32"\n" |
|
|
|
"device address: 0x%"PRIx32"%08"PRIx32"\n" |
|
|
|
"override enable: %"PRIu32"\n" |
|
|
|
"NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n" |
|
|
|
"BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n" |
|
|
|
"\n[user information control block]\n\n" |
|
|
|
"code region 0 size: %"PRIu32"kB\n" |
|
|
|
"read back protection configuration: %"PRIx32"\n" |
|
|
|
"reset value for XTALFREQ: %"PRIx32"\n" |
|
|
|
"firmware id: 0x%04"PRIx32, |
|
|
|
ficr[0].value, |
|
|
|
ficr[1].value, |
|
|
|
(ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024, |
|
|
|
((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present", |
|
|
|
ficr[4].value, |
|
|
|
ficr[5].value, |
|
|
|
(ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value, |
|
|
|
(ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value, |
|
|
|
(ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value, |
|
|
|
ficr[9].value, ficr[9].value, ficr[9].value, ficr[9].value, |
|
|
|
ficr[10].value, ficr[11].value, ficr[12].value, ficr[13].value, |
|
|
|
ficr[14].value, |
|
|
|
ficr[15].value, ficr[16].value, |
|
|
|
ficr[17].value, |
|
|
|
ficr[18].value, ficr[19].value, ficr[20].value, ficr[21].value, ficr[22].value, |
|
|
|
ficr[23].value, ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, |
|
|
|
(uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024, |
|
|
|
uicr[1].value & 0xFFFF, |
|
|
|
uicr[2].value & 0xFF, |
|
|
|
uicr[3].value & 0xFFFF); |
|
|
|
|
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
static const struct command_registration nrf51_exec_command_handlers[] = { |
|
|
|
{ |
|
|
|
.name = "mass_erase", |
|
|
|
.handler = nrf51_handle_mass_erase_command, |
|
|
|
.mode = COMMAND_EXEC, |
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.help = "Erase all flash contents of the chip.", |
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}, |
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COMMAND_REGISTRATION_DONE |
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|
|
}; |
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|
|
|
|
|
|
static const struct command_registration nrf51_command_handlers[] = { |
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|
|
{ |
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|
.name = "nrf51", |
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|
|
.mode = COMMAND_ANY, |
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|
|
.help = "nrf51 flash command group", |
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|
|
.usage = "", |
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|
|
.chain = nrf51_exec_command_handlers, |
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|
|
}, |
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|
|
COMMAND_REGISTRATION_DONE |
|
|
|
}; |
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|
|
|
|
|
|
struct flash_driver nrf51_flash = { |
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|
|
.name = "nrf51", |
|
|
|
.commands = nrf51_command_handlers, |
|
|
|
.flash_bank_command = nrf51_flash_bank_command, |
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|
|
.info = nrf51_info, |
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|
|
.erase = nrf51_erase, |
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|
|
.protect = nrf51_protect, |
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|
|
.write = nrf51_write, |
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|
|
.read = default_flash_read, |
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|
|
.probe = nrf51_probe, |
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|
|
.auto_probe = nrf51_auto_probe, |
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|
|
.erase_check = default_flash_blank_check, |
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|
|
.protect_check = nrf51_protect_check, |
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|
|
}; |