Voila! This get rids of mysteries about what what state the TAP is in. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>tags/v0.5.0-rc1
@@ -86,7 +86,6 @@ static struct jtag_tap *__jtag_all_taps = NULL; | |||
static unsigned jtag_num_taps = 0; | |||
static enum reset_types jtag_reset_config = RESET_NONE; | |||
static tap_state_t cmd_queue_end_state = TAP_RESET; | |||
tap_state_t cmd_queue_cur_state = TAP_RESET; | |||
static bool jtag_verify_capture_ir = true; | |||
@@ -717,7 +716,6 @@ void jtag_add_reset(int req_tlr_or_trst, int req_srst) | |||
*/ | |||
if (trst_with_tlr) { | |||
LOG_DEBUG("JTAG reset with TLR instead of TRST"); | |||
jtag_set_end_state(TAP_RESET); | |||
jtag_add_tlr(); | |||
} else if (jtag_trst != new_trst) { | |||
@@ -743,24 +741,6 @@ void jtag_add_reset(int req_tlr_or_trst, int req_srst) | |||
} | |||
} | |||
/* DEPRECATED! store such global state outside JTAG layer */ | |||
void jtag_set_end_state(tap_state_t state) | |||
{ | |||
if ((state == TAP_DRSHIFT)||(state == TAP_IRSHIFT)) | |||
{ | |||
LOG_ERROR("BUG: TAP_DRSHIFT/IRSHIFT can't be end state. Calling code should use a larger scan field"); | |||
} | |||
if (state != TAP_INVALID) | |||
cmd_queue_end_state = state; | |||
} | |||
/* DEPRECATED! store such global state outside JTAG layer */ | |||
tap_state_t jtag_get_end_state(void) | |||
{ | |||
return cmd_queue_end_state; | |||
} | |||
void jtag_add_sleep(uint32_t us) | |||
{ | |||
/// @todo Here, keep_alive() appears to be a layering violation!!! | |||
@@ -550,26 +550,6 @@ void jtag_add_runtest(int num_cycles, tap_state_t endstate); | |||
*/ | |||
void jtag_add_reset(int req_tlr_or_trst, int srst); | |||
/** | |||
* DEPRECATED! store such global state outside JTAG layer | |||
* | |||
* Function jtag_set_end_state | |||
* | |||
* Set a global variable to \a state if \a state != TAP_INVALID. | |||
* | |||
*/ | |||
void jtag_set_end_state(tap_state_t state); | |||
/** | |||
* DEPRECATED! store such global state outside JTAG layer | |||
* | |||
* Function jtag_get_end_state | |||
* | |||
* Return the value of the global variable for end state | |||
*/ | |||
tap_state_t jtag_get_end_state(void); | |||
void jtag_add_sleep(uint32_t us); | |||
int jtag_add_tms_seq(unsigned nbits, const uint8_t *seq, enum tap_state t); | |||
@@ -141,7 +141,6 @@ static int virtex2_load(struct pld_device *pld_device, const char *filename) | |||
if ((retval = xilinx_read_bit_file(&bit_file, filename)) != ERROR_OK) | |||
return retval; | |||
jtag_set_end_state(TAP_IDLE); | |||
virtex2_set_instr(virtex2_info->tap, 0xb); /* JPROG_B */ | |||
jtag_execute_queue(); | |||
jtag_add_sleep(1000); | |||
@@ -160,7 +159,6 @@ static int virtex2_load(struct pld_device *pld_device, const char *filename) | |||
jtag_add_tlr(); | |||
jtag_set_end_state(TAP_IDLE); | |||
virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */ | |||
jtag_add_runtest(13, TAP_IDLE); | |||
virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */ | |||
@@ -87,7 +87,6 @@ int adi_jtag_dp_scan(struct adiv5_dap *dap, | |||
struct scan_field fields[2]; | |||
uint8_t out_addr_buf; | |||
jtag_set_end_state(TAP_IDLE); | |||
arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE); | |||
/* Scan out a read or write operation using some DP or AP register. | |||
@@ -331,7 +330,6 @@ static int jtag_idcode_q_read(struct adiv5_dap *dap, | |||
struct scan_field fields[1]; | |||
/* This is a standard JTAG operation -- no DAP tweakage */ | |||
jtag_set_end_state(TAP_IDLE); | |||
retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL, TAP_IDLE); | |||
if (retval != ERROR_OK) | |||
return retval; | |||
@@ -54,7 +54,6 @@ static int arm720t_scan_cp15(struct target *target, | |||
buf_set_u32(out_buf, 0, 32, flip_u32(out, 32)); | |||
jtag_set_end_state(TAP_DRPAUSE); | |||
if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK) | |||
{ | |||
return retval; | |||
@@ -687,7 +687,6 @@ int arm7_9_execute_sys_speed(struct target *target) | |||
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; | |||
/* set RESTART instruction */ | |||
jtag_set_end_state(TAP_IDLE); | |||
if (arm7_9->need_bypass_before_restart) { | |||
arm7_9->need_bypass_before_restart = 0; | |||
arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE); | |||
@@ -740,7 +739,6 @@ int arm7_9_execute_fast_sys_speed(struct target *target) | |||
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; | |||
/* set RESTART instruction */ | |||
jtag_set_end_state(TAP_IDLE); | |||
if (arm7_9->need_bypass_before_restart) { | |||
arm7_9->need_bypass_before_restart = 0; | |||
arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE); | |||
@@ -1743,7 +1741,6 @@ int arm7_9_restart_core(struct target *target) | |||
struct arm_jtag *jtag_info = &arm7_9->jtag_info; | |||
/* set RESTART instruction */ | |||
jtag_set_end_state(TAP_IDLE); | |||
if (arm7_9->need_bypass_before_restart) { | |||
arm7_9->need_bypass_before_restart = 0; | |||
arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE); | |||
@@ -56,8 +56,6 @@ static int arm7tdmi_examine_debug_reason(struct target *target) | |||
uint8_t databus[4]; | |||
uint8_t breakpoint; | |||
jtag_set_end_state(TAP_DRPAUSE); | |||
fields[0].num_bits = 1; | |||
fields[0].out_value = NULL; | |||
fields[0].in_value = &breakpoint; | |||
@@ -119,7 +117,6 @@ static __inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_ | |||
static __inline int arm7tdmi_clock_out(struct arm_jtag *jtag_info, | |||
uint32_t out, uint32_t *deprecated, int breakpoint) | |||
{ | |||
jtag_set_end_state(TAP_DRPAUSE); | |||
arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE); | |||
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE); | |||
@@ -132,7 +129,6 @@ static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in) | |||
int retval = ERROR_OK; | |||
struct scan_field fields[2]; | |||
jtag_set_end_state(TAP_DRPAUSE); | |||
if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK) | |||
{ | |||
return retval; | |||
@@ -217,7 +213,6 @@ static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info, | |||
int retval = ERROR_OK; | |||
struct scan_field fields[2]; | |||
jtag_set_end_state(TAP_DRPAUSE); | |||
if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK) | |||
{ | |||
return retval; | |||
@@ -91,7 +91,6 @@ static int arm920t_read_cp15_physical(struct target *target, | |||
jtag_info = &arm920t->arm7_9_common.jtag_info; | |||
jtag_set_end_state(TAP_IDLE); | |||
arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); | |||
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); | |||
@@ -142,7 +141,6 @@ static int arm920t_write_cp15_physical(struct target *target, | |||
buf_set_u32(value_buf, 0, 32, value); | |||
jtag_set_end_state(TAP_IDLE); | |||
arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); | |||
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); | |||
@@ -192,7 +190,6 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode, | |||
jtag_info = &arm920t->arm7_9_common.jtag_info; | |||
jtag_set_end_state(TAP_IDLE); | |||
arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); | |||
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); | |||
@@ -63,7 +63,6 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2 | |||
buf_set_u32(address_buf, 0, 14, address); | |||
jtag_set_end_state(TAP_IDLE); | |||
if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK) | |||
{ | |||
return retval; | |||
@@ -152,7 +151,6 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op | |||
buf_set_u32(address_buf, 0, 14, address); | |||
buf_set_u32(value_buf, 0, 32, value); | |||
jtag_set_end_state(TAP_IDLE); | |||
if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK) | |||
{ | |||
return retval; | |||
@@ -84,7 +84,6 @@ static int arm966e_read_cp15(struct target *target, int reg_addr, uint32_t *valu | |||
uint8_t reg_addr_buf = reg_addr & 0x3f; | |||
uint8_t nr_w_buf = 0; | |||
jtag_set_end_state(TAP_IDLE); | |||
if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK) | |||
{ | |||
return retval; | |||
@@ -139,7 +138,6 @@ int arm966e_write_cp15(struct target *target, int reg_addr, uint32_t value) | |||
buf_set_u32(value_buf, 0, 32, value); | |||
jtag_set_end_state(TAP_IDLE); | |||
if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK) | |||
{ | |||
return retval; | |||
@@ -87,8 +87,6 @@ int arm9tdmi_examine_debug_reason(struct target *target) | |||
uint8_t instructionbus[4]; | |||
uint8_t debug_reason; | |||
jtag_set_end_state(TAP_DRPAUSE); | |||
fields[0].num_bits = 32; | |||
fields[0].out_value = NULL; | |||
fields[0].in_value = databus; | |||
@@ -154,7 +152,6 @@ int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr, | |||
if (sysspeed) | |||
buf_set_u32(&sysspeed_buf, 2, 1, 1); | |||
jtag_set_end_state(TAP_DRPAUSE); | |||
if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK) | |||
{ | |||
return retval; | |||
@@ -213,7 +210,6 @@ int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in) | |||
int retval = ERROR_OK;; | |||
struct scan_field fields[3]; | |||
jtag_set_end_state(TAP_DRPAUSE); | |||
if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK) | |||
{ | |||
return retval; | |||
@@ -280,7 +276,6 @@ int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info, | |||
int retval = ERROR_OK; | |||
struct scan_field fields[3]; | |||
jtag_set_end_state(TAP_DRPAUSE); | |||
if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK) | |||
{ | |||
return retval; | |||
@@ -343,7 +343,6 @@ int embeddedice_read_reg_w_check(struct reg *reg, | |||
uint8_t field1_out[1]; | |||
uint8_t field2_out[1]; | |||
jtag_set_end_state(TAP_IDLE); | |||
arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE); | |||
arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE); | |||
@@ -405,7 +404,6 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz | |||
uint8_t field1_out[1]; | |||
uint8_t field2_out[1]; | |||
jtag_set_end_state(TAP_IDLE); | |||
arm_jtag_scann(jtag_info, 0x2, TAP_IDLE); | |||
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); | |||
@@ -490,7 +488,6 @@ void embeddedice_write_reg(struct reg *reg, uint32_t value) | |||
LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value); | |||
jtag_set_end_state(TAP_IDLE); | |||
arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE); | |||
arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE); | |||
@@ -523,7 +520,6 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size) | |||
uint8_t field1_out[1]; | |||
uint8_t field2_out[1]; | |||
jtag_set_end_state(TAP_IDLE); | |||
arm_jtag_scann(jtag_info, 0x2, TAP_IDLE); | |||
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); | |||
@@ -576,7 +572,6 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou | |||
else | |||
return ERROR_INVALID_ARGUMENTS; | |||
jtag_set_end_state(TAP_IDLE); | |||
arm_jtag_scann(jtag_info, 0x2, TAP_IDLE); | |||
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); | |||
@@ -173,7 +173,6 @@ static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames) | |||
struct scan_field fields[3]; | |||
int i; | |||
jtag_set_end_state(TAP_IDLE); | |||
etb_scann(etb, 0x0); | |||
etb_set_instr(etb, 0xc); | |||
@@ -227,7 +226,6 @@ static int etb_read_reg_w_check(struct reg *reg, | |||
LOG_DEBUG("%i", (int)(etb_reg->addr)); | |||
jtag_set_end_state(TAP_IDLE); | |||
etb_scann(etb_reg->etb, 0x0); | |||
etb_set_instr(etb_reg->etb, 0xc); | |||
@@ -310,7 +308,6 @@ static int etb_write_reg(struct reg *reg, uint32_t value) | |||
LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value); | |||
jtag_set_end_state(TAP_IDLE); | |||
etb_scann(etb_reg->etb, 0x0); | |||
etb_set_instr(etb_reg->etb, 0xc); | |||
@@ -504,7 +504,6 @@ static int etm_read_reg_w_check(struct reg *reg, | |||
LOG_DEBUG("%s (%u)", r->name, reg_addr); | |||
jtag_set_end_state(TAP_IDLE); | |||
arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE); | |||
arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE); | |||
@@ -587,7 +586,6 @@ static int etm_write_reg(struct reg *reg, uint32_t value) | |||
LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value); | |||
jtag_set_end_state(TAP_IDLE); | |||
arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE); | |||
arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE); | |||
@@ -84,7 +84,6 @@ int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr) | |||
buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32)); | |||
jtag_set_end_state(TAP_DRPAUSE); | |||
arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE); | |||
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE); | |||
@@ -56,8 +56,6 @@ int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode) | |||
{ | |||
struct scan_field field; | |||
jtag_set_end_state(TAP_IDLE); | |||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE); | |||
field.num_bits = 32; | |||
@@ -78,8 +76,6 @@ int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode) | |||
{ | |||
struct scan_field field; | |||
jtag_set_end_state(TAP_IDLE); | |||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE); | |||
field.num_bits = 32; | |||
@@ -209,7 +205,6 @@ int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step) | |||
int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info) | |||
{ | |||
uint32_t ejtag_ctrl; | |||
jtag_set_end_state(TAP_IDLE); | |||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||
/* set debug break bit */ | |||
@@ -112,7 +112,6 @@ int mips_m4k_poll(struct target *target) | |||
uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl; | |||
/* read ejtag control reg */ | |||
jtag_set_end_state(TAP_IDLE); | |||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); | |||
@@ -122,7 +121,6 @@ int mips_m4k_poll(struct target *target) | |||
{ | |||
/* we have detected a reset, clear flag | |||
* otherwise ejtag will not work */ | |||
jtag_set_end_state(TAP_IDLE); | |||
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC; | |||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); | |||
@@ -135,7 +133,6 @@ int mips_m4k_poll(struct target *target) | |||
{ | |||
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) | |||
{ | |||
jtag_set_end_state(TAP_IDLE); | |||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT); | |||
target->state = TARGET_HALTED; | |||
@@ -227,12 +224,10 @@ int mips_m4k_assert_reset(struct target *target) | |||
if (target->reset_halt) | |||
{ | |||
/* use hardware to catch reset */ | |||
jtag_set_end_state(TAP_IDLE); | |||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT); | |||
} | |||
else | |||
{ | |||
jtag_set_end_state(TAP_IDLE); | |||
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT); | |||
} | |||
@@ -191,7 +191,6 @@ static int xscale_read_dcsr(struct target *target) | |||
uint8_t field2_check_value = 0x0; | |||
uint8_t field2_check_mask = 0x1; | |||
jtag_set_end_state(TAP_DRPAUSE); | |||
xscale_jtag_set_instr(target->tap, | |||
XSCALE_SELDCSR << xscale->xscale_variant, | |||
TAP_DRPAUSE); | |||
@@ -235,8 +234,6 @@ static int xscale_read_dcsr(struct target *target) | |||
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value; | |||
fields[1].in_value = NULL; | |||
jtag_set_end_state(TAP_IDLE); | |||
jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE); | |||
/* DANGER!!! this must be here. It will make sure that the arguments | |||
@@ -286,7 +283,6 @@ static int xscale_receive(struct target *target, uint32_t *buffer, int num_words | |||
fields[2].check_value = &field2_check_value; | |||
fields[2].check_mask = &field2_check_mask; | |||
jtag_set_end_state(TAP_IDLE); | |||
xscale_jtag_set_instr(target->tap, | |||
XSCALE_DBGTX << xscale->xscale_variant, | |||
TAP_IDLE); | |||
@@ -369,8 +365,6 @@ static int xscale_read_tx(struct target *target, int consume) | |||
uint8_t field2_check_value = 0x0; | |||
uint8_t field2_check_mask = 0x1; | |||
jtag_set_end_state(TAP_IDLE); | |||
xscale_jtag_set_instr(target->tap, | |||
XSCALE_DBGTX << xscale->xscale_variant, | |||
TAP_IDLE); | |||
@@ -466,8 +460,6 @@ static int xscale_write_rx(struct target *target) | |||
uint8_t field2_check_value = 0x0; | |||
uint8_t field2_check_mask = 0x1; | |||
jtag_set_end_state(TAP_IDLE); | |||
xscale_jtag_set_instr(target->tap, | |||
XSCALE_DBGRX << xscale->xscale_variant, | |||
TAP_IDLE); | |||
@@ -545,8 +537,6 @@ static int xscale_send(struct target *target, uint8_t *buffer, int count, int si | |||
int retval; | |||
int done_count = 0; | |||
jtag_set_end_state(TAP_IDLE); | |||
xscale_jtag_set_instr(target->tap, | |||
XSCALE_DBGRX << xscale->xscale_variant, | |||
TAP_IDLE); | |||
@@ -629,7 +619,6 @@ static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_br | |||
if (ext_dbg_brk != -1) | |||
xscale->external_debug_break = ext_dbg_brk; | |||
jtag_set_end_state(TAP_IDLE); | |||
xscale_jtag_set_instr(target->tap, | |||
XSCALE_SELDCSR << xscale->xscale_variant, | |||
TAP_IDLE); | |||
@@ -692,7 +681,6 @@ static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8] | |||
LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va); | |||
/* LDIC into IR */ | |||
jtag_set_end_state(TAP_IDLE); | |||
xscale_jtag_set_instr(target->tap, | |||
XSCALE_LDIC << xscale->xscale_variant, | |||
TAP_IDLE); | |||
@@ -744,7 +732,6 @@ static int xscale_invalidate_ic_line(struct target *target, uint32_t va) | |||
uint8_t cmd; | |||
struct scan_field fields[2]; | |||
jtag_set_end_state(TAP_IDLE); | |||
xscale_jtag_set_instr(target->tap, | |||
XSCALE_LDIC << xscale->xscale_variant, | |||
TAP_IDLE); | |||
@@ -1484,7 +1471,6 @@ static int xscale_assert_reset(struct target *target) | |||
/* select DCSR instruction (set endstate to R-T-I to ensure we don't | |||
* end up in T-L-R, which would reset JTAG | |||
*/ | |||
jtag_set_end_state(TAP_IDLE); | |||
xscale_jtag_set_instr(target->tap, | |||
XSCALE_SELDCSR << xscale->xscale_variant, | |||
TAP_IDLE); | |||