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/*************************************************************************** |
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* Copyright (C) 2007 by Dominic Rath * |
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* Dominic.Rath@gmx.de * |
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* * |
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* This program is free software; you can redistribute it and/or modify * |
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* it under the terms of the GNU General Public License as published by * |
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* the Free Software Foundation; either version 2 of the License, or * |
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* (at your option) any later version. * |
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* * |
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* This program is distributed in the hope that it will be useful, * |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of * |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
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* GNU General Public License for more details. * |
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* * |
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* You should have received a copy of the GNU General Public License * |
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* along with this program; if not, write to the * |
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* Free Software Foundation, Inc., * |
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * |
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***************************************************************************/ |
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#ifdef HAVE_CONFIG_H |
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#include "config.h" |
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#endif |
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#include "arm926ejs.h" |
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#include "jtag.h" |
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#include "log.h" |
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#include <stdlib.h> |
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#include <string.h> |
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#if 0 |
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#define _DEBUG_INSTRUCTION_EXECUTION_ |
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#endif |
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/* cli handling */ |
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int arm926ejs_register_commands(struct command_context_s *cmd_ctx); |
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int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); |
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int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); |
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int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); |
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int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); |
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int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); |
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int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); |
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int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); |
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int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); |
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/* forward declarations */ |
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int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target); |
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int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target); |
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int arm926ejs_quit(); |
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int arm926ejs_arch_state(struct target_s *target, char *buf, int buf_size); |
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int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); |
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int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); |
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int arm926ejs_soft_reset_halt(struct target_s *target); |
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#define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0)) |
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target_type_t arm926ejs_target = |
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{ |
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.name = "arm926ejs", |
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.poll = arm7_9_poll, |
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.arch_state = arm926ejs_arch_state, |
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.halt = arm7_9_halt, |
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.resume = arm7_9_resume, |
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.step = arm7_9_step, |
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.assert_reset = arm7_9_assert_reset, |
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.deassert_reset = arm7_9_deassert_reset, |
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.soft_reset_halt = arm926ejs_soft_reset_halt, |
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.get_gdb_reg_list = armv4_5_get_gdb_reg_list, |
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.read_memory = arm7_9_read_memory, |
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.write_memory = arm926ejs_write_memory, |
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.bulk_write_memory = arm7_9_bulk_write_memory, |
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.run_algorithm = armv4_5_run_algorithm, |
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.add_breakpoint = arm7_9_add_breakpoint, |
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.remove_breakpoint = arm7_9_remove_breakpoint, |
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.add_watchpoint = arm7_9_add_watchpoint, |
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.remove_watchpoint = arm7_9_remove_watchpoint, |
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.register_commands = arm926ejs_register_commands, |
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.target_command = arm926ejs_target_command, |
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.init_target = arm926ejs_init_target, |
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.quit = arm926ejs_quit |
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}; |
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int arm926ejs_read_cp15(target_t *target, u32 address, u32 *value) |
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{ |
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armv4_5_common_t *armv4_5 = target->arch_info; |
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arm7_9_common_t *arm7_9 = armv4_5->arch_info; |
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arm_jtag_t *jtag_info = &arm7_9->jtag_info; |
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scan_field_t fields[4]; |
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u8 address_buf[2]; |
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u8 nr_w_buf = 0; |
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u8 access = 1; |
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buf_set_u32(address_buf, 0, 14, address); |
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jtag_add_end_state(TAP_RTI); |
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arm_jtag_scann(jtag_info, 0xf); |
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arm_jtag_set_instr(jtag_info, jtag_info->intest_instr); |
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fields[0].device = jtag_info->chain_pos; |
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fields[0].num_bits = 32; |
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fields[0].out_value = NULL; |
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fields[0].out_mask = NULL; |
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fields[0].in_value = NULL; |
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fields[0].in_check_value = NULL; |
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fields[0].in_check_mask = NULL; |
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fields[0].in_handler = NULL; |
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fields[0].in_handler_priv = NULL; |
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fields[1].device = jtag_info->chain_pos; |
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fields[1].num_bits = 1; |
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fields[1].out_value = &access; |
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fields[1].out_mask = NULL; |
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fields[1].in_value = &access; |
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fields[1].in_check_value = NULL; |
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fields[1].in_check_mask = NULL; |
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fields[1].in_handler = NULL; |
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fields[1].in_handler_priv = NULL; |
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fields[2].device = jtag_info->chain_pos; |
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fields[2].num_bits = 14; |
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fields[2].out_value = address_buf; |
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fields[2].out_mask = NULL; |
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fields[2].in_value = NULL; |
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fields[2].in_check_value = NULL; |
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fields[2].in_check_mask = NULL; |
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fields[2].in_handler = NULL; |
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fields[2].in_handler_priv = NULL; |
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fields[3].device = jtag_info->chain_pos; |
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fields[3].num_bits = 1; |
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fields[3].out_value = &nr_w_buf; |
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fields[3].out_mask = NULL; |
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fields[3].in_value = NULL; |
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fields[3].in_check_value = NULL; |
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fields[3].in_check_mask = NULL; |
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fields[3].in_handler = NULL; |
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fields[3].in_handler_priv = NULL; |
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jtag_add_dr_scan(4, fields, -1); |
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/* rescan with NOP, to wait for the access to complete */ |
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access = 0; |
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fields[0].in_handler_priv = value; |
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fields[0].in_handler = arm_jtag_buf_to_u32; |
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do |
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{ |
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jtag_add_dr_scan(4, fields, -1); |
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jtag_execute_queue(); |
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} while ((access & 1) != 1); |
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#ifdef _DEBUG_INSTRUCTION_EXECUTION_ |
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DEBUG("addr: 0x%x value: %8.8x", address, *value); |
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#endif |
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return ERROR_OK; |
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} |
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int arm926ejs_write_cp15(target_t *target, u32 address, u32 value) |
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{ |
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armv4_5_common_t *armv4_5 = target->arch_info; |
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arm7_9_common_t *arm7_9 = armv4_5->arch_info; |
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arm_jtag_t *jtag_info = &arm7_9->jtag_info; |
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scan_field_t fields[4]; |
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u8 value_buf[4]; |
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u8 address_buf[2]; |
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u8 nr_w_buf = 1; |
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u8 access = 1; |
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buf_set_u32(address_buf, 0, 14, address); |
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buf_set_u32(value_buf, 0, 32, value); |
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jtag_add_end_state(TAP_RTI); |
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arm_jtag_scann(jtag_info, 0xf); |
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arm_jtag_set_instr(jtag_info, jtag_info->intest_instr); |
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fields[0].device = jtag_info->chain_pos; |
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fields[0].num_bits = 32; |
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fields[0].out_value = value_buf; |
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fields[0].out_mask = NULL; |
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fields[0].in_value = NULL; |
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fields[0].in_check_value = NULL; |
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fields[0].in_check_mask = NULL; |
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fields[0].in_handler = NULL; |
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fields[0].in_handler_priv = NULL; |
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fields[1].device = jtag_info->chain_pos; |
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fields[1].num_bits = 1; |
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fields[1].out_value = &access; |
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fields[1].out_mask = NULL; |
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fields[1].in_value = &access; |
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fields[1].in_check_value = NULL; |
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fields[1].in_check_mask = NULL; |
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fields[1].in_handler = NULL; |
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fields[1].in_handler_priv = NULL; |
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fields[2].device = jtag_info->chain_pos; |
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fields[2].num_bits = 14; |
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fields[2].out_value = address_buf; |
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fields[2].out_mask = NULL; |
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fields[2].in_value = NULL; |
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fields[2].in_check_value = NULL; |
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fields[2].in_check_mask = NULL; |
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fields[2].in_handler = NULL; |
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fields[2].in_handler_priv = NULL; |
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fields[3].device = jtag_info->chain_pos; |
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fields[3].num_bits = 1; |
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fields[3].out_value = &nr_w_buf; |
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fields[3].out_mask = NULL; |
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fields[3].in_value = NULL; |
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fields[3].in_check_value = NULL; |
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fields[3].in_check_mask = NULL; |
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fields[3].in_handler = NULL; |
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fields[3].in_handler_priv = NULL; |
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jtag_add_dr_scan(4, fields, -1); |
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/* rescan with NOP, to wait for the access to complete */ |
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access = 0; |
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do |
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{ |
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jtag_add_dr_scan(4, fields, -1); |
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jtag_execute_queue(); |
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} while (access != 1); |
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#ifdef _DEBUG_INSTRUCTION_EXECUTION_ |
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DEBUG("addr: 0x%x value: %8.8x", address, value); |
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#endif |
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return ERROR_OK; |
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} |
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int arm926ejs_examine_debug_reason(target_t *target) |
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{ |
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armv4_5_common_t *armv4_5 = target->arch_info; |
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arm7_9_common_t *arm7_9 = armv4_5->arch_info; |
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reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; |
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int debug_reason; |
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int retval; |
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embeddedice_read_reg(dbg_stat); |
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if ((retval = jtag_execute_queue()) != ERROR_OK) |
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return retval; |
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debug_reason = buf_get_u32(dbg_stat->value, 6, 4); |
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switch (debug_reason) |
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{ |
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case 1: |
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DEBUG("breakpoint from EICE unit 0"); |
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target->debug_reason = DBG_REASON_BREAKPOINT; |
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break; |
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case 2: |
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DEBUG("breakpoint from EICE unit 1"); |
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target->debug_reason = DBG_REASON_BREAKPOINT; |
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break; |
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case 3: |
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DEBUG("soft breakpoint (BKPT instruction)"); |
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target->debug_reason = DBG_REASON_BREAKPOINT; |
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break; |
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case 4: |
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DEBUG("vector catch breakpoint"); |
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target->debug_reason = DBG_REASON_BREAKPOINT; |
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break; |
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case 5: |
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DEBUG("external breakpoint"); |
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target->debug_reason = DBG_REASON_BREAKPOINT; |
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break; |
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case 6: |
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DEBUG("watchpoint from EICE unit 0"); |
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target->debug_reason = DBG_REASON_WATCHPOINT; |
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break; |
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case 7: |
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DEBUG("watchpoint from EICE unit 1"); |
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target->debug_reason = DBG_REASON_WATCHPOINT; |
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break; |
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case 8: |
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DEBUG("external watchpoint"); |
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target->debug_reason = DBG_REASON_WATCHPOINT; |
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break; |
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case 9: |
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DEBUG("internal debug request"); |
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target->debug_reason = DBG_REASON_DBGRQ; |
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break; |
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case 10: |
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DEBUG("external debug request"); |
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target->debug_reason = DBG_REASON_DBGRQ; |
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break; |
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case 11: |
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ERROR("BUG: debug re-entry from system speed access shouldn't be handled here"); |
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break; |
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default: |
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ERROR("BUG: unknown debug reason: 0x%x", debug_reason); |
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target->debug_reason = DBG_REASON_DBGRQ; |
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} |
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return ERROR_OK; |
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} |
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u32 arm926ejs_get_ttb(target_t *target) |
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{ |
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int retval; |
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u32 ttb = 0x0; |
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if ((retval = arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 2, 0), &ttb)) != ERROR_OK) |
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return retval; |
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return ttb; |
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} |
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void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) |
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{ |
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u32 cp15_control; |
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/* read cp15 control register */ |
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arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &cp15_control); |
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jtag_execute_queue(); |
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if (mmu) |
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{ |
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/* invalidate TLB */ |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 8, 7), 0x0); |
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cp15_control &= ~0x1U; |
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} |
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if (d_u_cache) |
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{ |
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u32 debug_override; |
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/* read-modify-write CP15 debug override register |
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* to enable "test and clean all" */ |
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arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), &debug_override); |
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debug_override |= 0x80000; |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), debug_override); |
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/* clean and invalidate DCache */ |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), 0x0); |
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/* write CP15 debug override register |
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* to disable "test and clean all" */ |
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debug_override &= ~0x80000; |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), debug_override); |
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cp15_control &= ~0x4U; |
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} |
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if (i_cache) |
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{ |
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/* invalidate ICache */ |
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arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), 0x0); |
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cp15_control &= ~0x1000U; |
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} |
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|
|
|
|
|
|
arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), cp15_control); |
|
|
|
} |
|
|
|
|
|
|
|
void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) |
|
|
|
{ |
|
|
|
u32 cp15_control; |
|
|
|
|
|
|
|
/* read cp15 control register */ |
|
|
|
arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &cp15_control); |
|
|
|
jtag_execute_queue(); |
|
|
|
|
|
|
|
if (mmu) |
|
|
|
cp15_control |= 0x1U; |
|
|
|
|
|
|
|
if (d_u_cache) |
|
|
|
cp15_control |= 0x4U; |
|
|
|
|
|
|
|
if (i_cache) |
|
|
|
cp15_control |= 0x1000U; |
|
|
|
|
|
|
|
arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), cp15_control); |
|
|
|
} |
|
|
|
|
|
|
|
void arm926ejs_post_debug_entry(target_t *target) |
|
|
|
{ |
|
|
|
armv4_5_common_t *armv4_5 = target->arch_info; |
|
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info; |
|
|
|
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; |
|
|
|
arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; |
|
|
|
|
|
|
|
/* examine cp15 control reg */ |
|
|
|
arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &arm926ejs->cp15_control_reg); |
|
|
|
jtag_execute_queue(); |
|
|
|
DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg); |
|
|
|
|
|
|
|
if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1) |
|
|
|
{ |
|
|
|
u32 cache_type_reg; |
|
|
|
/* identify caches */ |
|
|
|
arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 0, 0), &cache_type_reg); |
|
|
|
jtag_execute_queue(); |
|
|
|
armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache); |
|
|
|
} |
|
|
|
|
|
|
|
arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0; |
|
|
|
arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0; |
|
|
|
arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0; |
|
|
|
|
|
|
|
/* save i/d fault status and address register */ |
|
|
|
arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 5, 0), &arm926ejs->d_fsr); |
|
|
|
arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 5, 0), &arm926ejs->i_fsr); |
|
|
|
arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 6, 0), &arm926ejs->d_far); |
|
|
|
|
|
|
|
DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x", |
|
|
|
arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr); |
|
|
|
|
|
|
|
|
|
|
|
u32 cache_dbg_ctrl; |
|
|
|
|
|
|
|
/* read-modify-write CP15 cache debug control register |
|
|
|
* to disable I/D-cache linefills and force WT */ |
|
|
|
arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl); |
|
|
|
cache_dbg_ctrl |= 0x7; |
|
|
|
arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl); |
|
|
|
|
|
|
|
} |
|
|
|
|
|
|
|
void arm926ejs_pre_restore_context(target_t *target) |
|
|
|
{ |
|
|
|
armv4_5_common_t *armv4_5 = target->arch_info; |
|
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info; |
|
|
|
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; |
|
|
|
arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; |
|
|
|
|
|
|
|
/* restore i/d fault status and address register */ |
|
|
|
arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 5, 0), arm926ejs->d_fsr); |
|
|
|
arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 5, 0), arm926ejs->i_fsr); |
|
|
|
arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 6, 0), arm926ejs->d_far); |
|
|
|
|
|
|
|
u32 cache_dbg_ctrl; |
|
|
|
|
|
|
|
/* read-modify-write CP15 cache debug control register |
|
|
|
* to reenable I/D-cache linefills and disable WT */ |
|
|
|
arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl); |
|
|
|
cache_dbg_ctrl |= 0x7; |
|
|
|
arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl); |
|
|
|
} |
|
|
|
|
|
|
|
int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p) |
|
|
|
{ |
|
|
|
armv4_5_common_t *armv4_5 = target->arch_info; |
|
|
|
arm7_9_common_t *arm7_9; |
|
|
|
arm9tdmi_common_t *arm9tdmi; |
|
|
|
arm926ejs_common_t *arm926ejs; |
|
|
|
|
|
|
|
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) |
|
|
|
{ |
|
|
|
return -1; |
|
|
|
} |
|
|
|
|
|
|
|
arm7_9 = armv4_5->arch_info; |
|
|
|
if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) |
|
|
|
{ |
|
|
|
return -1; |
|
|
|
} |
|
|
|
|
|
|
|
arm9tdmi = arm7_9->arch_info; |
|
|
|
if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC) |
|
|
|
{ |
|
|
|
return -1; |
|
|
|
} |
|
|
|
|
|
|
|
arm926ejs = arm9tdmi->arch_info; |
|
|
|
if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC) |
|
|
|
{ |
|
|
|
return -1; |
|
|
|
} |
|
|
|
|
|
|
|
*armv4_5_p = armv4_5; |
|
|
|
*arm7_9_p = arm7_9; |
|
|
|
*arm9tdmi_p = arm9tdmi; |
|
|
|
*arm926ejs_p = arm926ejs; |
|
|
|
|
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
int arm926ejs_arch_state(struct target_s *target, char *buf, int buf_size) |
|
|
|
{ |
|
|
|
armv4_5_common_t *armv4_5 = target->arch_info; |
|
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info; |
|
|
|
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; |
|
|
|
arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; |
|
|
|
|
|
|
|
char *state[] = |
|
|
|
{ |
|
|
|
"disabled", "enabled" |
|
|
|
}; |
|
|
|
|
|
|
|
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) |
|
|
|
{ |
|
|
|
ERROR("BUG: called for a non-ARMv4/5 target"); |
|
|
|
exit(-1); |
|
|
|
} |
|
|
|
|
|
|
|
snprintf(buf, buf_size, |
|
|
|
"target halted in %s state due to %s, current mode: %s\n" |
|
|
|
"cpsr: 0x%8.8x pc: 0x%8.8x\n" |
|
|
|
"MMU: %s, D-Cache: %s, I-Cache: %s", |
|
|
|
armv4_5_state_strings[armv4_5->core_state], |
|
|
|
target_debug_reason_strings[target->debug_reason], |
|
|
|
armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], |
|
|
|
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), |
|
|
|
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), |
|
|
|
state[arm926ejs->armv4_5_mmu.mmu_enabled], |
|
|
|
state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], |
|
|
|
state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]); |
|
|
|
|
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
int arm926ejs_soft_reset_halt(struct target_s *target) |
|
|
|
{ |
|
|
|
armv4_5_common_t *armv4_5 = target->arch_info; |
|
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info; |
|
|
|
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; |
|
|
|
arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; |
|
|
|
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; |
|
|
|
|
|
|
|
if (target->state == TARGET_RUNNING) |
|
|
|
{ |
|
|
|
target->type->halt(target); |
|
|
|
} |
|
|
|
|
|
|
|
while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0) |
|
|
|
{ |
|
|
|
embeddedice_read_reg(dbg_stat); |
|
|
|
jtag_execute_queue(); |
|
|
|
} |
|
|
|
|
|
|
|
target->state = TARGET_HALTED; |
|
|
|
|
|
|
|
/* SVC, ARM state, IRQ and FIQ disabled */ |
|
|
|
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); |
|
|
|
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; |
|
|
|
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; |
|
|
|
|
|
|
|
/* start fetching from 0x0 */ |
|
|
|
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); |
|
|
|
armv4_5->core_cache->reg_list[15].dirty = 1; |
|
|
|
armv4_5->core_cache->reg_list[15].valid = 1; |
|
|
|
|
|
|
|
armv4_5->core_mode = ARMV4_5_MODE_SVC; |
|
|
|
armv4_5->core_state = ARMV4_5_STATE_ARM; |
|
|
|
|
|
|
|
arm926ejs_disable_mmu_caches(target, 1, 1, 1); |
|
|
|
arm926ejs->armv4_5_mmu.mmu_enabled = 0; |
|
|
|
arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; |
|
|
|
arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; |
|
|
|
|
|
|
|
target_call_event_callbacks(target, TARGET_EVENT_HALTED); |
|
|
|
|
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) |
|
|
|
{ |
|
|
|
int retval; |
|
|
|
armv4_5_common_t *armv4_5 = target->arch_info; |
|
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info; |
|
|
|
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; |
|
|
|
arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; |
|
|
|
|
|
|
|
if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK) |
|
|
|
return retval; |
|
|
|
|
|
|
|
/* If ICache is enabled, we have to invalidate affected ICache lines |
|
|
|
* the DCache is forced to write-through, so we don't have to clean it here |
|
|
|
*/ |
|
|
|
if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled) |
|
|
|
{ |
|
|
|
if (count <= 1) |
|
|
|
{ |
|
|
|
/* invalidate ICache single entry with MVA */ |
|
|
|
arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 7, 5), address); |
|
|
|
} |
|
|
|
else |
|
|
|
{ |
|
|
|
/* invalidate ICache */ |
|
|
|
arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), address); |
|
|
|
} |
|
|
|
} |
|
|
|
|
|
|
|
return retval; |
|
|
|
} |
|
|
|
|
|
|
|
int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target) |
|
|
|
{ |
|
|
|
arm9tdmi_init_target(cmd_ctx, target); |
|
|
|
|
|
|
|
return ERROR_OK; |
|
|
|
|
|
|
|
} |
|
|
|
|
|
|
|
int arm926ejs_quit() |
|
|
|
{ |
|
|
|
|
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, char *variant) |
|
|
|
{ |
|
|
|
arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common; |
|
|
|
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common; |
|
|
|
|
|
|
|
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5) |
|
|
|
*/ |
|
|
|
arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant); |
|
|
|
|
|
|
|
arm9tdmi->arch_info = arm926ejs; |
|
|
|
arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC; |
|
|
|
|
|
|
|
arm7_9->post_debug_entry = arm926ejs_post_debug_entry; |
|
|
|
arm7_9->pre_restore_context = arm926ejs_pre_restore_context; |
|
|
|
|
|
|
|
arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1; |
|
|
|
arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb; |
|
|
|
arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory; |
|
|
|
arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory; |
|
|
|
arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches; |
|
|
|
arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches; |
|
|
|
arm926ejs->armv4_5_mmu.has_tiny_pages = 1; |
|
|
|
arm926ejs->armv4_5_mmu.mmu_enabled = 0; |
|
|
|
|
|
|
|
arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason; |
|
|
|
|
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target) |
|
|
|
{ |
|
|
|
int chain_pos; |
|
|
|
char *variant = NULL; |
|
|
|
arm926ejs_common_t *arm926ejs = malloc(sizeof(arm926ejs_common_t)); |
|
|
|
|
|
|
|
if (argc < 4) |
|
|
|
{ |
|
|
|
ERROR("'target arm926ejs' requires at least one additional argument"); |
|
|
|
exit(-1); |
|
|
|
} |
|
|
|
|
|
|
|
chain_pos = strtoul(args[3], NULL, 0); |
|
|
|
|
|
|
|
if (argc >= 5) |
|
|
|
variant = args[4]; |
|
|
|
|
|
|
|
DEBUG("chain_pos: %i, variant: %s", chain_pos, variant); |
|
|
|
|
|
|
|
arm926ejs_init_arch_info(target, arm926ejs, chain_pos, variant); |
|
|
|
|
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
int arm926ejs_register_commands(struct command_context_s *cmd_ctx) |
|
|
|
{ |
|
|
|
int retval; |
|
|
|
command_t *arm926ejs_cmd; |
|
|
|
|
|
|
|
|
|
|
|
retval = arm9tdmi_register_commands(cmd_ctx); |
|
|
|
|
|
|
|
arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands"); |
|
|
|
|
|
|
|
register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]"); |
|
|
|
|
|
|
|
register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches"); |
|
|
|
register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>"); |
|
|
|
|
|
|
|
register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]"); |
|
|
|
register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]"); |
|
|
|
register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]"); |
|
|
|
|
|
|
|
register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>"); |
|
|
|
register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>"); |
|
|
|
register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>"); |
|
|
|
|
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) |
|
|
|
{ |
|
|
|
int retval; |
|
|
|
target_t *target = get_current_target(cmd_ctx); |
|
|
|
armv4_5_common_t *armv4_5; |
|
|
|
arm7_9_common_t *arm7_9; |
|
|
|
arm9tdmi_common_t *arm9tdmi; |
|
|
|
arm926ejs_common_t *arm926ejs; |
|
|
|
int opcode_1 = strtoul(args[0], NULL, 0); |
|
|
|
int opcode_2 = strtoul(args[1], NULL, 0); |
|
|
|
int CRn = strtoul(args[2], NULL, 0); |
|
|
|
int CRm = strtoul(args[3], NULL, 0); |
|
|
|
|
|
|
|
if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK) |
|
|
|
{ |
|
|
|
command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
if (target->state != TARGET_HALTED) |
|
|
|
{ |
|
|
|
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
if ((argc < 4) || (argc > 5)) |
|
|
|
{ |
|
|
|
command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]"); |
|
|
|
} |
|
|
|
|
|
|
|
if (argc == 4) |
|
|
|
{ |
|
|
|
u32 value; |
|
|
|
if ((retval = arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm), &value)) != ERROR_OK) |
|
|
|
{ |
|
|
|
command_print(cmd_ctx, "couldn't access register"); |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
jtag_execute_queue(); |
|
|
|
|
|
|
|
command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value); |
|
|
|
} |
|
|
|
else |
|
|
|
{ |
|
|
|
u32 value = strtoul(args[4], NULL, 0); |
|
|
|
if ((retval = arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm), value)) != ERROR_OK) |
|
|
|
{ |
|
|
|
command_print(cmd_ctx, "couldn't access register"); |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value); |
|
|
|
} |
|
|
|
|
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) |
|
|
|
{ |
|
|
|
target_t *target = get_current_target(cmd_ctx); |
|
|
|
armv4_5_common_t *armv4_5; |
|
|
|
arm7_9_common_t *arm7_9; |
|
|
|
arm9tdmi_common_t *arm9tdmi; |
|
|
|
arm926ejs_common_t *arm926ejs; |
|
|
|
|
|
|
|
if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK) |
|
|
|
{ |
|
|
|
command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache); |
|
|
|
} |
|
|
|
|
|
|
|
int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) |
|
|
|
{ |
|
|
|
target_t *target = get_current_target(cmd_ctx); |
|
|
|
armv4_5_common_t *armv4_5; |
|
|
|
arm7_9_common_t *arm7_9; |
|
|
|
arm9tdmi_common_t *arm9tdmi; |
|
|
|
arm926ejs_common_t *arm926ejs; |
|
|
|
arm_jtag_t *jtag_info; |
|
|
|
|
|
|
|
if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK) |
|
|
|
{ |
|
|
|
command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
jtag_info = &arm7_9->jtag_info; |
|
|
|
|
|
|
|
if (target->state != TARGET_HALTED) |
|
|
|
{ |
|
|
|
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu); |
|
|
|
} |
|
|
|
|
|
|
|
int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) |
|
|
|
{ |
|
|
|
target_t *target = get_current_target(cmd_ctx); |
|
|
|
armv4_5_common_t *armv4_5; |
|
|
|
arm7_9_common_t *arm7_9; |
|
|
|
arm9tdmi_common_t *arm9tdmi; |
|
|
|
arm926ejs_common_t *arm926ejs; |
|
|
|
arm_jtag_t *jtag_info; |
|
|
|
|
|
|
|
if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK) |
|
|
|
{ |
|
|
|
command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
jtag_info = &arm7_9->jtag_info; |
|
|
|
|
|
|
|
if (target->state != TARGET_HALTED) |
|
|
|
{ |
|
|
|
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu); |
|
|
|
} |
|
|
|
|
|
|
|
int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) |
|
|
|
{ |
|
|
|
target_t *target = get_current_target(cmd_ctx); |
|
|
|
armv4_5_common_t *armv4_5; |
|
|
|
arm7_9_common_t *arm7_9; |
|
|
|
arm9tdmi_common_t *arm9tdmi; |
|
|
|
arm926ejs_common_t *arm926ejs; |
|
|
|
arm_jtag_t *jtag_info; |
|
|
|
|
|
|
|
if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK) |
|
|
|
{ |
|
|
|
command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
jtag_info = &arm7_9->jtag_info; |
|
|
|
|
|
|
|
if (target->state != TARGET_HALTED) |
|
|
|
{ |
|
|
|
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu); |
|
|
|
} |