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@@ -491,7 +491,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) |
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{ |
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struct arm_reg *armv4_5 = reg->arch_info; |
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struct target *target = armv4_5->target; |
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struct arm *armv4_5_target = target_to_armv4_5(target); |
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struct arm *armv4_5_target = target_to_arm(target); |
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uint32_t value = buf_get_u32(buf, 0, 32); |
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if (target->state != TARGET_HALTED) |
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@@ -583,7 +583,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm |
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int armv4_5_arch_state(struct target *target) |
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{ |
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struct arm *armv4_5 = target_to_armv4_5(target); |
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struct arm *armv4_5 = target_to_arm(target); |
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if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) |
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{ |
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@@ -611,7 +611,7 @@ int armv4_5_arch_state(struct target *target) |
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COMMAND_HANDLER(handle_armv4_5_reg_command) |
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{ |
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struct target *target = get_current_target(CMD_CTX); |
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struct arm *armv4_5 = target_to_armv4_5(target); |
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struct arm *armv4_5 = target_to_arm(target); |
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unsigned num_regs; |
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struct reg *regs; |
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@@ -698,7 +698,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) |
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COMMAND_HANDLER(handle_armv4_5_core_state_command) |
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{ |
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struct target *target = get_current_target(CMD_CTX); |
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struct arm *armv4_5 = target_to_armv4_5(target); |
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struct arm *armv4_5 = target_to_arm(target); |
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if (!is_arm(armv4_5)) |
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{ |
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@@ -974,7 +974,7 @@ const struct command_registration arm_command_handlers[] = { |
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int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size) |
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{ |
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struct arm *armv4_5 = target_to_armv4_5(target); |
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struct arm *armv4_5 = target_to_arm(target); |
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int i; |
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if (!is_arm_mode(armv4_5->core_mode)) |
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@@ -999,7 +999,7 @@ int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int |
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static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info) |
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{ |
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int retval; |
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struct arm *armv4_5 = target_to_armv4_5(target); |
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struct arm *armv4_5 = target_to_arm(target); |
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if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK) |
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{ |
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@@ -1036,7 +1036,7 @@ int armv4_5_run_algorithm_inner(struct target *target, |
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int (*run_it)(struct target *target, uint32_t exit_point, |
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int timeout_ms, void *arch_info)) |
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{ |
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struct arm *armv4_5 = target_to_armv4_5(target); |
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struct arm *armv4_5 = target_to_arm(target); |
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struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info; |
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enum arm_state core_state = armv4_5->core_state; |
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uint32_t context[17]; |
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@@ -1388,7 +1388,7 @@ int arm_blank_check_memory(struct target *target, |
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static int arm_full_context(struct target *target) |
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{ |
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struct arm *armv4_5 = target_to_armv4_5(target); |
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struct arm *armv4_5 = target_to_arm(target); |
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unsigned num_regs = armv4_5->core_cache->num_regs; |
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struct reg *reg = armv4_5->core_cache->reg_list; |
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int retval = ERROR_OK; |
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