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@@ -818,7 +818,7 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction) |
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} |
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/* CLZ */ |
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if ((opcode & 0x0060000f0) == 0x00300010) |
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if ((opcode & 0x006000f0) == 0x00600010) |
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{ |
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u8 Rm, Rd; |
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instruction->type = ARM_CLZ; |
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@@ -829,8 +829,8 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction) |
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address, opcode, COND(opcode), Rd, Rm); |
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} |
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/* BLX */ |
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if ((opcode & 0x0060000f0) == 0x00200030) |
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/* BLX(2) */ |
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if ((opcode & 0x006000f0) == 0x00200030) |
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{ |
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u8 Rm; |
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instruction->type = ARM_BLX; |
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