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@@ -425,7 +425,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) |
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if (attempts++==1000) |
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{ |
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ERROR("Failed to receiving data from debug handler after 1000 attempts"); |
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retval=ERROR_JTAG_QUEUE_FAILED; |
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retval=ERROR_TARGET_TIMEOUT; |
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break; |
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} |
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} |
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@@ -505,7 +505,7 @@ int xscale_read_tx(target_t *target, int consume) |
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gettimeofday(&timeout, NULL); |
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timeval_add_time(&timeout, 5, 0); |
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do |
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for (;;) |
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{ |
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/* if we want to consume the register content (i.e. clear TX_READY), |
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* we have to go straight from Capture-DR to Shift-DR |
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@@ -530,7 +530,12 @@ int xscale_read_tx(target_t *target, int consume) |
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ERROR("time out reading TX register"); |
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return ERROR_TARGET_TIMEOUT; |
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} |
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} while ((!(field0_in & 1)) && consume); |
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if (!((!(field0_in & 1)) && consume)) |
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{ |
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break; |
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} |
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usleep(500*1000); /* avoid flooding the logs */ |
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} |
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if (!(field0_in & 1)) |
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; |
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@@ -590,7 +595,7 @@ int xscale_write_rx(target_t *target) |
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/* poll until rx_read is low */ |
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DEBUG("polling RX"); |
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do |
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for (;;) |
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{ |
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jtag_add_dr_scan(3, fields, TAP_RTI); |
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@@ -606,7 +611,10 @@ int xscale_write_rx(target_t *target) |
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ERROR("time out writing RX register"); |
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return ERROR_TARGET_TIMEOUT; |
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} |
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} while (field0_in & 1); |
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if (!(field0_in & 1)) |
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break; |
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usleep(500*1000); /* wait 500ms to avoid flooding the logs */ |
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} |
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/* set rx_valid */ |
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field2 = 0x1; |
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@@ -937,6 +945,7 @@ int xscale_update_vectors(target_t *target) |
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armv4_5_common_t *armv4_5 = target->arch_info; |
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xscale_common_t *xscale = armv4_5->arch_info; |
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int i; |
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int retval; |
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u32 low_reset_branch, high_reset_branch; |
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@@ -949,8 +958,12 @@ int xscale_update_vectors(target_t *target) |
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} |
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else |
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{ |
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if (target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]) != ERROR_OK) |
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retval=target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]); |
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if (retval == ERROR_TARGET_TIMEOUT) |
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return retval; |
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if (retval!=ERROR_OK) |
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{ |
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/* Some of these reads will fail as part of normal execution */ |
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xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0); |
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} |
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} |
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@@ -964,8 +977,12 @@ int xscale_update_vectors(target_t *target) |
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} |
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else |
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{ |
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if (target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]) != ERROR_OK) |
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retval=target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]); |
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if (retval == ERROR_TARGET_TIMEOUT) |
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return retval; |
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if (retval!=ERROR_OK) |
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{ |
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/* Some of these reads will fail as part of normal execution */ |
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xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0); |
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} |
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} |
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@@ -1077,15 +1094,18 @@ int xscale_debug_entry(target_t *target) |
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u32 pc; |
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u32 buffer[10]; |
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int i; |
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int retval; |
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u32 moe; |
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/* clear external dbg break (will be written on next DCSR read) */ |
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xscale->external_debug_break = 0; |
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xscale_read_dcsr(target); |
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if ((retval=xscale_read_dcsr(target))!=ERROR_OK) |
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return retval; |
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/* get r0, pc, r1 to r7 and cpsr */ |
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xscale_receive(target, buffer, 10); |
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if ((retval=xscale_receive(target, buffer, 10))!=ERROR_OK) |
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return retval; |
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/* move r0 from buffer to register cache */ |
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buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]); |
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@@ -1340,7 +1360,8 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ |
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} |
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/* update vector tables */ |
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xscale_update_vectors(target); |
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if ((retval=xscale_update_vectors(target))!=ERROR_OK) |
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return retval; |
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/* current = 1: continue on current pc, otherwise continue at <address> */ |
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if (!current) |
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@@ -1929,6 +1950,7 @@ int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count |
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xscale_common_t *xscale = armv4_5->arch_info; |
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u32 *buf32; |
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int i; |
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int retval; |
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DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); |
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@@ -1946,17 +1968,21 @@ int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count |
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return ERROR_TARGET_UNALIGNED_ACCESS; |
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/* send memory read request (command 0x1n, n: access size) */ |
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xscale_send_u32(target, 0x10 | size); |
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if ((retval=xscale_send_u32(target, 0x10 | size))!=ERROR_OK) |
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return retval; |
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/* send base address for read request */ |
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xscale_send_u32(target, address); |
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if ((retval=xscale_send_u32(target, address))!=ERROR_OK) |
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return retval; |
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/* send number of requested data words */ |
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xscale_send_u32(target, count); |
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if ((retval=xscale_send_u32(target, count))!=ERROR_OK) |
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return retval; |
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/* receive data from target (count times 32-bit words in host endianness) */ |
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buf32 = malloc(4 * count); |
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xscale_receive(target, buf32, count); |
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if ((retval=xscale_receive(target, buf32, count))!=ERROR_OK) |
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return retval; |
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/* extract data from host-endian buffer into byte stream */ |
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for (i = 0; i < count; i++) |
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@@ -1983,11 +2009,13 @@ int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count |
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free(buf32); |
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/* examine DCSR, to see if Sticky Abort (SA) got set */ |
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xscale_read_dcsr(target); |
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if ((retval=xscale_read_dcsr(target))!=ERROR_OK) |
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return retval; |
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if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) |
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{ |
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/* clear SA bit */ |
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xscale_send_u32(target, 0x60); |
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if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK) |
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return retval; |
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return ERROR_TARGET_DATA_ABORT; |
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} |
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@@ -1999,6 +2027,7 @@ int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 coun |
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{ |
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armv4_5_common_t *armv4_5 = target->arch_info; |
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xscale_common_t *xscale = armv4_5->arch_info; |
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int retval; |
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DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); |
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@@ -2016,13 +2045,16 @@ int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 coun |
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return ERROR_TARGET_UNALIGNED_ACCESS; |
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/* send memory write request (command 0x2n, n: access size) */ |
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xscale_send_u32(target, 0x20 | size); |
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if ((retval=xscale_send_u32(target, 0x20 | size))!=ERROR_OK) |
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return retval; |
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/* send base address for read request */ |
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xscale_send_u32(target, address); |
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if ((retval=xscale_send_u32(target, address))!=ERROR_OK) |
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return retval; |
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/* send number of requested data words to be written*/ |
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xscale_send_u32(target, count); |
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if ((retval=xscale_send_u32(target, count))!=ERROR_OK) |
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return retval; |
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/* extract data from host-endian buffer into byte stream */ |
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#if 0 |
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@@ -2051,14 +2083,17 @@ int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 coun |
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} |
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} |
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#endif |
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xscale_send(target, buffer, count, size); |
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if ((retval=xscale_send(target, buffer, count, size))!=ERROR_OK) |
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return retval; |
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/* examine DCSR, to see if Sticky Abort (SA) got set */ |
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xscale_read_dcsr(target); |
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if ((retval=xscale_read_dcsr(target))!=ERROR_OK) |
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return retval; |
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if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) |
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{ |
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/* clear SA bit */ |
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xscale_send_u32(target, 0x60); |
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if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK) |
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return retval; |
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return ERROR_TARGET_DATA_ABORT; |
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} |
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