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@@ -45,40 +45,42 @@ static int ejtag_dma_read(mips_ejtag_t *ejtag_info, u32 addr, u32 *data) |
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{ |
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u32 v; |
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u32 ejtag_ctrl; |
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int retries = RETRY_ATTEMPTS; |
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int retries = RETRY_ATTEMPTS; |
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begin_ejtag_dma_read: |
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// Setup Address |
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/* Setup Address */ |
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v = addr; |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); |
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mips_ejtag_drscan_32(ejtag_info, &v); |
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// Initiate DMA Read & set DSTRT |
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/* Initiate DMA Read & set DSTRT */ |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); |
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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// Wait for DSTRT to Clear |
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/* Wait for DSTRT to Clear */ |
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do { |
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ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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} while(ejtag_ctrl & EJTAG_CTRL_DSTRT); |
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// Read Data |
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/* Read Data */ |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); |
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mips_ejtag_drscan_32(ejtag_info, data); |
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// Clear DMA & Check DERR |
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/* Clear DMA & Check DERR */ |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); |
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ejtag_ctrl = ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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if (ejtag_ctrl & EJTAG_CTRL_DERR) |
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{ |
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if (retries--) { |
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printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr); |
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LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr); |
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goto begin_ejtag_dma_read; |
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} else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr); |
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} |
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else |
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LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr); |
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return ERROR_JTAG_DEVICE_ERROR; |
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} |
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@@ -89,46 +91,50 @@ static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data) |
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{ |
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u32 v; |
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u32 ejtag_ctrl; |
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int retries = RETRY_ATTEMPTS; |
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int retries = RETRY_ATTEMPTS; |
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begin_ejtag_dma_read_h: |
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// Setup Address |
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/* Setup Address */ |
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v = addr; |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); |
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mips_ejtag_drscan_32(ejtag_info, &v); |
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// Initiate DMA Read & set DSTRT |
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/* Initiate DMA Read & set DSTRT */ |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); |
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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// Wait for DSTRT to Clear |
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/* Wait for DSTRT to Clear */ |
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do { |
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ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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} while(ejtag_ctrl & EJTAG_CTRL_DSTRT); |
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// Read Data |
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/* Read Data */ |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); |
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mips_ejtag_drscan_32(ejtag_info, &v); |
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// Clear DMA & Check DERR |
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/* Clear DMA & Check DERR */ |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); |
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ejtag_ctrl = ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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if (ejtag_ctrl & EJTAG_CTRL_DERR) |
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{ |
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if (retries--) { |
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printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr); |
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LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr); |
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goto begin_ejtag_dma_read_h; |
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} else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr); |
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} |
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else |
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LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr); |
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return ERROR_JTAG_DEVICE_ERROR; |
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} |
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// Handle the bigendian/littleendian |
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if ( addr & 0x2 ) *data = (v>>16)&0xffff ; |
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else *data = (v&0x0000ffff) ; |
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/* Handle the bigendian/littleendian */ |
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if (addr & 0x2) |
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*data = (v >> 16) & 0xffff; |
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else |
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*data = (v & 0x0000ffff); |
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return ERROR_OK; |
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} |
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@@ -137,49 +143,59 @@ static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, u8 *data) |
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{ |
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u32 v; |
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u32 ejtag_ctrl; |
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int retries = RETRY_ATTEMPTS; |
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int retries = RETRY_ATTEMPTS; |
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begin_ejtag_dma_read_b: |
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// Setup Address |
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/* Setup Address */ |
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v = addr; |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); |
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mips_ejtag_drscan_32(ejtag_info, &v); |
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// Initiate DMA Read & set DSTRT |
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/* Initiate DMA Read & set DSTRT */ |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); |
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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// Wait for DSTRT to Clear |
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/* Wait for DSTRT to Clear */ |
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do { |
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ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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} while(ejtag_ctrl & EJTAG_CTRL_DSTRT); |
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// Read Data |
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/* Read Data */ |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); |
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mips_ejtag_drscan_32(ejtag_info, &v); |
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// Clear DMA & Check DERR |
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/* Clear DMA & Check DERR */ |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); |
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ejtag_ctrl = ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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if (ejtag_ctrl & EJTAG_CTRL_DERR) |
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{ |
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if (retries--) { |
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printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr); |
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LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr); |
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goto begin_ejtag_dma_read_b; |
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} else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr); |
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} |
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else |
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LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr); |
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return ERROR_JTAG_DEVICE_ERROR; |
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} |
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// Handle the bigendian/littleendian |
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switch(addr & 0x3) { |
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case 0: *data = v & 0xff; break; |
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case 1: *data = (v>>8) & 0xff; break; |
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case 2: *data = (v>>16) & 0xff; break; |
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case 3: *data = (v>>24) & 0xff; break; |
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switch (addr & 0x3) { |
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case 0: |
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*data = v & 0xff; |
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break; |
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case 1: |
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*data = (v >> 8) & 0xff; |
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break; |
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case 2: |
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*data = (v >> 16) & 0xff; |
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break; |
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case 3: |
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*data = (v >> 24) & 0xff; |
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break; |
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} |
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return ERROR_OK; |
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@@ -189,41 +205,43 @@ static int ejtag_dma_write(mips_ejtag_t *ejtag_info, u32 addr, u32 data) |
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{ |
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u32 v; |
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u32 ejtag_ctrl; |
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int retries = RETRY_ATTEMPTS; |
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int retries = RETRY_ATTEMPTS; |
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begin_ejtag_dma_write: |
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// Setup Address |
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/* Setup Address */ |
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v = addr; |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); |
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mips_ejtag_drscan_32(ejtag_info, &v); |
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// Setup Data |
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/* Setup Data */ |
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v = data; |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); |
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mips_ejtag_drscan_32(ejtag_info, &v); |
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// Initiate DMA Write & set DSTRT |
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/* Initiate DMA Write & set DSTRT */ |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); |
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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// Wait for DSTRT to Clear |
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/* Wait for DSTRT to Clear */ |
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do { |
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ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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} while(ejtag_ctrl & EJTAG_CTRL_DSTRT); |
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// Clear DMA & Check DERR |
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/* Clear DMA & Check DERR */ |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); |
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ejtag_ctrl = ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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if (ejtag_ctrl & EJTAG_CTRL_DERR) |
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{ |
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if (retries--) { |
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printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr); |
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LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr); |
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goto begin_ejtag_dma_write; |
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} else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr); |
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} |
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else |
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LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr); |
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return ERROR_JTAG_DEVICE_ERROR; |
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} |
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@@ -234,46 +252,47 @@ static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, u32 addr, u32 data) |
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{ |
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u32 v; |
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u32 ejtag_ctrl; |
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int retries = RETRY_ATTEMPTS; |
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int retries = RETRY_ATTEMPTS; |
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// Handle the bigendian/littleendian |
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/* Handle the bigendian/littleendian */ |
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data &= 0xffff; |
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data |= data<<16; |
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data |= data << 16; |
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begin_ejtag_dma_write_h: |
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// Setup Address |
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/* Setup Address */ |
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v = addr; |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); |
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mips_ejtag_drscan_32(ejtag_info, &v); |
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// Setup Data |
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/* Setup Data */ |
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v = data; |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); |
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mips_ejtag_drscan_32(ejtag_info, &v); |
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// Initiate DMA Write & set DSTRT |
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/* Initiate DMA Write & set DSTRT */ |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); |
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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// Wait for DSTRT to Clear |
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/* Wait for DSTRT to Clear */ |
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do { |
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ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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} while(ejtag_ctrl & EJTAG_CTRL_DSTRT); |
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// Clear DMA & Check DERR |
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/* Clear DMA & Check DERR */ |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); |
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ejtag_ctrl = ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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if (ejtag_ctrl & EJTAG_CTRL_DERR) |
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{ |
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if (retries--) { |
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printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr); |
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LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr); |
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goto begin_ejtag_dma_write_h; |
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} else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr); |
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} |
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else |
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LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr); |
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return ERROR_JTAG_DEVICE_ERROR; |
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} |
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@@ -284,47 +303,48 @@ static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, u32 addr, u32 data) |
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{ |
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u32 v; |
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u32 ejtag_ctrl; |
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int retries = RETRY_ATTEMPTS; |
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int retries = RETRY_ATTEMPTS; |
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// Handle the bigendian/littleendian |
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/* Handle the bigendian/littleendian */ |
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data &= 0xff; |
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data |= data<<8; |
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data |= data<<16; |
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data |= data << 8; |
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data |= data << 16; |
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begin_ejtag_dma_write_b: |
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// Setup Address |
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/* Setup Address*/ |
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v = addr; |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); |
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mips_ejtag_drscan_32(ejtag_info, &v); |
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// Setup Data |
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/* Setup Data */ |
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v = data; |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); |
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mips_ejtag_drscan_32(ejtag_info, &v); |
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// Initiate DMA Write & set DSTRT |
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/* Initiate DMA Write & set DSTRT */ |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); |
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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// Wait for DSTRT to Clear |
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/* Wait for DSTRT to Clear */ |
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do { |
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ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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} while(ejtag_ctrl & EJTAG_CTRL_DSTRT); |
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// Clear DMA & Check DERR |
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/* Clear DMA & Check DERR */ |
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); |
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ejtag_ctrl = ejtag_info->ejtag_ctrl; |
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); |
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if (ejtag_ctrl & EJTAG_CTRL_DERR) |
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if (ejtag_ctrl & EJTAG_CTRL_DERR) |
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{ |
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if (retries--) { |
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printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr); |
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LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr); |
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goto begin_ejtag_dma_write_b; |
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} else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr); |
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} |
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else |
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LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr); |
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return ERROR_JTAG_DEVICE_ERROR; |
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} |
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@@ -351,8 +371,8 @@ int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 |
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int i; |
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int retval; |
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for(i=0; i<count; i++) { |
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if((retval=ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK) |
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for (i=0; i<count; i++) { |
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if ((retval = ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK) |
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return retval; |
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} |
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@@ -364,8 +384,8 @@ int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 |
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int i; |
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int retval; |
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for(i=0; i<count; i++) { |
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if((retval=ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK) |
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for (i=0; i<count; i++) { |
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if ((retval = ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK) |
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return retval; |
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} |
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@@ -377,8 +397,8 @@ int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *b |
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int i; |
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int retval; |
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for(i=0; i<count; i++) { |
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if((retval=ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK) |
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for (i=0; i<count; i++) { |
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if ((retval = ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK) |
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return retval; |
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} |
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@@ -405,8 +425,8 @@ int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 |
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|
int i; |
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|
|
int retval; |
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|
|
|
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|
for(i=0; i<count; i++) { |
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if((retval=ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK) |
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|
for (i=0; i<count; i++) { |
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|
if ((retval = ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK) |
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|
|
return retval; |
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|
} |
|
|
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|
@@ -418,8 +438,8 @@ int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 |
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|
|
int i; |
|
|
|
int retval; |
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|
|
|
|
|
|
for(i=0; i<count; i++) { |
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|
|
if((retval=ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK) |
|
|
|
for (i=0; i<count; i++) { |
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|
|
if ((retval = ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK) |
|
|
|
return retval; |
|
|
|
} |
|
|
|
|
|
|
@@ -431,8 +451,8 @@ int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 * |
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|
|
int i; |
|
|
|
int retval; |
|
|
|
|
|
|
|
for(i=0; i<count; i++) { |
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|
|
if((retval=ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK) |
|
|
|
for (i=0; i<count; i++) { |
|
|
|
if ((retval = ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK) |
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|
|
return retval; |
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|
|
} |
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|