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/*************************************************************************** |
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* Copyright (C) 2009 by Alexei Babich * |
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* Rezonans plc., Chelyabinsk, Russia * |
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* impatt@mail.ru * |
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* * |
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* This program is free software; you can redistribute it and/or modify * |
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* it under the terms of the GNU General Public License as published by * |
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* the Free Software Foundation; either version 2 of the License, or * |
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* (at your option) any later version. * |
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* * |
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* This program is distributed in the hope that it will be useful, * |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of * |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
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* GNU General Public License for more details. * |
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* * |
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* You should have received a copy of the GNU General Public License * |
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* along with this program; if not, write to the * |
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* Free Software Foundation, Inc., * |
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * |
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***************************************************************************/ |
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/* |
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* Freescale iMX3* OpenOCD NAND Flash controller support. |
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* |
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* Many thanks to Ben Dooks for writing s3c24xx driver. |
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*/ |
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/* |
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driver tested with STMicro NAND512W3A @imx31 |
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tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0" |
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get_next_halfword_from_sram_buffer() not tested |
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*/ |
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#ifdef HAVE_CONFIG_H |
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#include "config.h" |
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#endif |
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#include "mx3_nand.h" |
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static const char target_not_halted_err_msg[] = |
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"target must be halted to use mx3 NAND flash controller"; |
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static const char data_block_size_err_msg[] = |
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"minimal granularity is one half-word, %d is incorrect"; |
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static const char sram_buffer_bounds_err_msg[] = |
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"trying to access out of SRAM buffer bound (addr=0x%x)"; |
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static const char invalid_command_sequense_err_msg[] = |
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"invalid command sequence in %s"; |
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static const char get_status_register_err_msg[] = "can't get NAND status"; |
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static uint32_t in_sram_address; |
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unsigned char sign_of_sequental_byte_read; |
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static int test_iomux_settings (target_t * target, uint32_t value, |
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uint32_t mask, const char *text); |
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static int initialize_nf_controller (struct nand_device_s *device); |
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static int get_next_byte_from_sram_buffer (target_t * target, uint8_t * value); |
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static int get_next_halfword_from_sram_buffer (target_t * target, |
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uint16_t * value); |
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static int poll_for_complete_op (target_t * target, const char *text); |
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static int validate_target_state (struct nand_device_s *device); |
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static int do_data_output (struct nand_device_s *device); |
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static int imx31_nand_device_command (struct command_context_s *cmd_ctx, |
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char *cmd, char **args, int argc, |
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struct nand_device_s *device); |
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static int imx31_init (struct nand_device_s *device); |
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static int imx31_read_data (struct nand_device_s *device, void *data); |
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static int imx31_write_data (struct nand_device_s *device, uint16_t data); |
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static int imx31_nand_ready (struct nand_device_s *device, int timeout); |
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static int imx31_register_commands (struct command_context_s *cmd_ctx); |
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static int imx31_reset (struct nand_device_s *device); |
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static int imx31_command (struct nand_device_s *device, uint8_t command); |
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static int imx31_address (struct nand_device_s *device, uint8_t address); |
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static int imx31_controller_ready (struct nand_device_s *device, int tout); |
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static int imx31_write_page (struct nand_device_s *device, uint32_t page, |
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uint8_t * data, uint32_t data_size, uint8_t * oob, |
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uint32_t oob_size); |
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static int imx31_read_page (struct nand_device_s *device, uint32_t page, |
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uint8_t * data, uint32_t data_size, uint8_t * oob, |
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uint32_t oob_size); |
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nand_flash_controller_t imx31_nand_flash_controller = { |
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.name = "imx31", |
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.nand_device_command = imx31_nand_device_command, |
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.register_commands = imx31_register_commands, |
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.init = imx31_init, |
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.reset = imx31_reset, |
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.command = imx31_command, |
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.address = imx31_address, |
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.write_data = imx31_write_data, |
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.read_data = imx31_read_data, |
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.write_page = imx31_write_page, |
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.read_page = imx31_read_page, |
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.controller_ready = imx31_controller_ready, |
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.nand_ready = imx31_nand_ready, |
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}; |
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static int imx31_nand_device_command (struct command_context_s *cmd_ctx, |
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char *cmd, char **args, int argc, |
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struct nand_device_s *device) |
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{ |
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mx3_nf_controller_t *mx3_nf_info; |
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mx3_nf_info = malloc (sizeof (mx3_nf_controller_t)); |
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if (mx3_nf_info == NULL) |
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{ |
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LOG_ERROR ("no memory for nand controller"); |
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return ERROR_FAIL; |
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} |
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device->controller_priv = mx3_nf_info; |
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mx3_nf_info->target = get_target (args[1]); |
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if (mx3_nf_info->target == NULL) |
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{ |
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LOG_ERROR ("target '%s' not defined", args[1]); |
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return ERROR_FAIL; |
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} |
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if (argc < 3) |
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{ |
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LOG_ERROR ("use \"nand device imx31 target noecc|hwecc\""); |
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return ERROR_FAIL; |
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} |
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/* |
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* check hwecc requirements |
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*/ |
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{ |
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int hwecc_needed; |
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hwecc_needed = strcmp (args[2], "hwecc"); |
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if (hwecc_needed == 0) |
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{ |
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mx3_nf_info->flags.hw_ecc_enabled = 1; |
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} |
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else |
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{ |
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mx3_nf_info->flags.hw_ecc_enabled = 0; |
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} |
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} |
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mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE; |
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mx3_nf_info->fin = MX3_NF_FIN_NONE; |
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mx3_nf_info->flags.target_little_endian = |
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(mx3_nf_info->target->endianness == TARGET_LITTLE_ENDIAN); |
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/* |
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* testing host endianess |
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*/ |
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{ |
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int x = 1; |
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if (*(char *) &x == 1) |
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{ |
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mx3_nf_info->flags.host_little_endian = 1; |
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} |
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else |
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{ |
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mx3_nf_info->flags.host_little_endian = 0; |
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} |
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} |
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return ERROR_OK; |
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} |
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static int imx31_init (struct nand_device_s *device) |
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{ |
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mx3_nf_controller_t *mx3_nf_info = device->controller_priv; |
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target_t *target = mx3_nf_info->target; |
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{ |
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/* |
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* validate target state |
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*/ |
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int validate_target_result; |
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validate_target_result = validate_target_state (device); |
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if (validate_target_result != ERROR_OK) |
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{ |
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return validate_target_result; |
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} |
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} |
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{ |
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uint16_t buffsize_register_content; |
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target_read_u16 (target, MX3_NF_BUFSIZ, &buffsize_register_content); |
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mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f); |
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} |
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{ |
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uint32_t pcsr_register_content; |
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target_read_u32 (target, MX3_PCSR, &pcsr_register_content); |
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if (!device->bus_width) |
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{ |
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device->bus_width = |
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(pcsr_register_content & 0x80000000) ? 16 : 8; |
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} |
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else |
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{ |
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pcsr_register_content |= |
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((device->bus_width == 16) ? 0x80000000 : 0x00000000); |
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target_write_u32 (target, MX3_PCSR, pcsr_register_content); |
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} |
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if (!device->page_size) |
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{ |
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device->page_size = |
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(pcsr_register_content & 0x40000000) ? 2048 : 512; |
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} |
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else |
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{ |
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pcsr_register_content |= |
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((device->page_size == 2048) ? 0x40000000 : 0x00000000); |
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target_write_u32 (target, MX3_PCSR, pcsr_register_content); |
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} |
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if (mx3_nf_info->flags.one_kb_sram && (device->page_size == 2048)) |
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{ |
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LOG_ERROR |
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("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it"); |
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} |
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} |
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{ |
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uint32_t cgr_register_content; |
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target_read_u32 (target, MX3_CCM_CGR2, &cgr_register_content); |
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if (!(cgr_register_content & 0x00000300)) |
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{ |
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LOG_ERROR ("clock gating to EMI disabled"); |
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return ERROR_FAIL; |
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} |
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} |
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{ |
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uint32_t gpr_register_content; |
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target_read_u32 (target, MX3_GPR, &gpr_register_content); |
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if (gpr_register_content & 0x00000060) |
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{ |
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LOG_ERROR ("pins mode overrided by GPR"); |
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return ERROR_FAIL; |
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} |
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} |
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{ |
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/* |
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* testing IOMUX settings; must be in "functional-mode output and |
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* functional-mode input" mode |
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*/ |
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uint8_t test_iomux; |
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test_iomux = ERROR_OK; |
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test_iomux |= |
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test_iomux_settings (target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2"); |
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test_iomux |= |
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test_iomux_settings (target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6"); |
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test_iomux |= |
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test_iomux_settings (target, 0x43fac0c8, 0x0000007f, "d7"); |
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if (device->bus_width == 16) |
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{ |
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test_iomux |= |
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test_iomux_settings (target, 0x43fac0c8, 0x7f7f7f00, |
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"d8,d9,d10"); |
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test_iomux |= |
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test_iomux_settings (target, 0x43fac0cc, 0x7f7f7f7f, |
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"d11,d12,d13,d14"); |
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test_iomux |= |
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test_iomux_settings (target, 0x43fac0d0, 0x0000007f, "d15"); |
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} |
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test_iomux |= |
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test_iomux_settings (target, 0x43fac0d0, 0x7f7f7f00, |
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"nfwp,nfce,nfrb"); |
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test_iomux |= |
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test_iomux_settings (target, 0x43fac0d4, 0x7f7f7f7f, |
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"nfwe,nfre,nfale,nfcle"); |
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if (test_iomux != ERROR_OK) |
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{ |
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return ERROR_FAIL; |
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} |
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} |
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initialize_nf_controller (device); |
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{ |
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int retval; |
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uint16_t nand_status_content; |
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retval = ERROR_OK; |
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retval |= imx31_command (device, NAND_CMD_STATUS); |
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retval |= imx31_address (device, 0x00); |
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retval |= do_data_output (device); |
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if (retval != ERROR_OK) |
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{ |
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LOG_ERROR (get_status_register_err_msg); |
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return ERROR_FAIL; |
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} |
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target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content); |
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if (!(nand_status_content & 0x0080)) |
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{ |
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/* |
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* is host-big-endian correctly ?? |
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*/ |
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LOG_INFO ("NAND read-only"); |
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mx3_nf_info->flags.nand_readonly = 1; |
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} |
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else |
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{ |
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mx3_nf_info->flags.nand_readonly = 0; |
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} |
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} |
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return ERROR_OK; |
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} |
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static int imx31_read_data (struct nand_device_s *device, void *data) |
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{ |
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mx3_nf_controller_t *mx3_nf_info = device->controller_priv; |
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target_t *target = mx3_nf_info->target; |
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{ |
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/* |
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* validate target state |
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*/ |
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int validate_target_result; |
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validate_target_result = validate_target_state (device); |
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if (validate_target_result != ERROR_OK) |
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{ |
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return validate_target_result; |
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} |
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} |
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{ |
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/* |
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* get data from nand chip |
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*/ |
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int try_data_output_from_nand_chip; |
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try_data_output_from_nand_chip = do_data_output (device); |
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if (try_data_output_from_nand_chip != ERROR_OK) |
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{ |
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return try_data_output_from_nand_chip; |
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} |
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} |
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if (device->bus_width == 16) |
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{ |
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get_next_halfword_from_sram_buffer (target, data); |
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} |
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else |
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{ |
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get_next_byte_from_sram_buffer (target, data); |
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} |
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return ERROR_OK; |
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} |
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static int imx31_write_data (struct nand_device_s *device, uint16_t data) |
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{ |
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LOG_ERROR ("write_data() not implemented"); |
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return ERROR_NAND_OPERATION_FAILED; |
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} |
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static int imx31_nand_ready (struct nand_device_s *device, int timeout) |
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{ |
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return imx31_controller_ready (device, timeout); |
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} |
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static int imx31_register_commands (struct command_context_s *cmd_ctx) |
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{ |
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return ERROR_OK; |
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} |
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static int imx31_reset (struct nand_device_s *device) |
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{ |
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/* |
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* validate target state |
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*/ |
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int validate_target_result; |
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validate_target_result = validate_target_state (device); |
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if (validate_target_result != ERROR_OK) |
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{ |
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return validate_target_result; |
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} |
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initialize_nf_controller (device); |
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return ERROR_OK; |
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} |
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static int imx31_command (struct nand_device_s *device, uint8_t command) |
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{ |
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mx3_nf_controller_t *mx3_nf_info = device->controller_priv; |
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target_t *target = mx3_nf_info->target; |
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{ |
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/* |
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* validate target state |
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*/ |
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int validate_target_result; |
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validate_target_result = validate_target_state (device); |
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if (validate_target_result != ERROR_OK) |
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{ |
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return validate_target_result; |
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} |
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} |
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switch (command) |
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{ |
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case NAND_CMD_READOOB: |
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command = NAND_CMD_READ0; |
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in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for |
|
|
|
* data_read() and |
|
|
|
* read_block_data() to |
|
|
|
* spare area in SRAM |
|
|
|
* buffer */ |
|
|
|
break; |
|
|
|
case NAND_CMD_READ1: |
|
|
|
command = NAND_CMD_READ0; |
|
|
|
/* |
|
|
|
* offset == one half of page size |
|
|
|
*/ |
|
|
|
in_sram_address = |
|
|
|
MX3_NF_MAIN_BUFFER0 + (device->page_size >> 1); |
|
|
|
default: |
|
|
|
in_sram_address = MX3_NF_MAIN_BUFFER0; |
|
|
|
} |
|
|
|
|
|
|
|
target_write_u16 (target, MX3_NF_FCMD, command); |
|
|
|
/* |
|
|
|
* start command input operation (set MX3_NF_BIT_OP_DONE==0) |
|
|
|
*/ |
|
|
|
target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI); |
|
|
|
{ |
|
|
|
int poll_result; |
|
|
|
poll_result = poll_for_complete_op (target, "command"); |
|
|
|
if (poll_result != ERROR_OK) |
|
|
|
{ |
|
|
|
return poll_result; |
|
|
|
} |
|
|
|
} |
|
|
|
/* |
|
|
|
* reset cursor to begin of the buffer |
|
|
|
*/ |
|
|
|
sign_of_sequental_byte_read = 0; |
|
|
|
switch (command) |
|
|
|
{ |
|
|
|
case NAND_CMD_READID: |
|
|
|
mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID; |
|
|
|
mx3_nf_info->fin = MX3_NF_FIN_DATAOUT; |
|
|
|
break; |
|
|
|
case NAND_CMD_STATUS: |
|
|
|
mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS; |
|
|
|
mx3_nf_info->fin = MX3_NF_FIN_DATAOUT; |
|
|
|
break; |
|
|
|
case NAND_CMD_READ0: |
|
|
|
mx3_nf_info->fin = MX3_NF_FIN_DATAOUT; |
|
|
|
mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE; |
|
|
|
break; |
|
|
|
case NAND_CMD_SEQIN: |
|
|
|
LOG_ERROR ("aaa"); |
|
|
|
return ERROR_FAIL; |
|
|
|
break; |
|
|
|
default: |
|
|
|
mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE; |
|
|
|
} |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
static int imx31_address (struct nand_device_s *device, uint8_t address) |
|
|
|
{ |
|
|
|
mx3_nf_controller_t *mx3_nf_info = device->controller_priv; |
|
|
|
target_t *target = mx3_nf_info->target; |
|
|
|
{ |
|
|
|
/* |
|
|
|
* validate target state |
|
|
|
*/ |
|
|
|
int validate_target_result; |
|
|
|
validate_target_result = validate_target_state (device); |
|
|
|
if (validate_target_result != ERROR_OK) |
|
|
|
{ |
|
|
|
return validate_target_result; |
|
|
|
} |
|
|
|
} |
|
|
|
|
|
|
|
target_write_u16 (target, MX3_NF_FADDR, address); |
|
|
|
/* |
|
|
|
* start address input operation (set MX3_NF_BIT_OP_DONE==0) |
|
|
|
*/ |
|
|
|
target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI); |
|
|
|
{ |
|
|
|
int poll_result; |
|
|
|
poll_result = poll_for_complete_op (target, "address"); |
|
|
|
if (poll_result != ERROR_OK) |
|
|
|
{ |
|
|
|
return poll_result; |
|
|
|
} |
|
|
|
} |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
static int imx31_controller_ready (struct nand_device_s *device, int tout) |
|
|
|
{ |
|
|
|
uint16_t poll_complete_status; |
|
|
|
mx3_nf_controller_t *mx3_nf_info = device->controller_priv; |
|
|
|
target_t *target = mx3_nf_info->target; |
|
|
|
|
|
|
|
{ |
|
|
|
/* |
|
|
|
* validate target state |
|
|
|
*/ |
|
|
|
int validate_target_result; |
|
|
|
validate_target_result = validate_target_state (device); |
|
|
|
if (validate_target_result != ERROR_OK) |
|
|
|
{ |
|
|
|
return validate_target_result; |
|
|
|
} |
|
|
|
} |
|
|
|
|
|
|
|
do |
|
|
|
{ |
|
|
|
target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status); |
|
|
|
if (poll_complete_status & MX3_NF_BIT_OP_DONE) |
|
|
|
{ |
|
|
|
return tout; |
|
|
|
} |
|
|
|
alive_sleep (1); |
|
|
|
} |
|
|
|
while (tout-- > 0); |
|
|
|
return tout; |
|
|
|
} |
|
|
|
|
|
|
|
static int imx31_write_page (struct nand_device_s *device, uint32_t page, |
|
|
|
uint8_t * data, uint32_t data_size, uint8_t * oob, |
|
|
|
uint32_t oob_size) |
|
|
|
{ |
|
|
|
mx3_nf_controller_t *mx3_nf_info = device->controller_priv; |
|
|
|
target_t *target = mx3_nf_info->target; |
|
|
|
|
|
|
|
if (data_size % 2) |
|
|
|
{ |
|
|
|
LOG_ERROR (data_block_size_err_msg, data_size); |
|
|
|
return ERROR_NAND_OPERATION_FAILED; |
|
|
|
} |
|
|
|
if (oob_size % 2) |
|
|
|
{ |
|
|
|
LOG_ERROR (data_block_size_err_msg, oob_size); |
|
|
|
return ERROR_NAND_OPERATION_FAILED; |
|
|
|
} |
|
|
|
if (!data) |
|
|
|
{ |
|
|
|
LOG_ERROR ("nothing to program"); |
|
|
|
return ERROR_NAND_OPERATION_FAILED; |
|
|
|
} |
|
|
|
{ |
|
|
|
/* |
|
|
|
* validate target state |
|
|
|
*/ |
|
|
|
int retval; |
|
|
|
retval = validate_target_state (device); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
{ |
|
|
|
return retval; |
|
|
|
} |
|
|
|
} |
|
|
|
{ |
|
|
|
int retval = ERROR_OK; |
|
|
|
retval |= imx31_command (device, NAND_CMD_SEQIN); |
|
|
|
retval |= imx31_address (device, 0x00); |
|
|
|
retval |= imx31_address (device, page & 0xff); |
|
|
|
retval |= imx31_address (device, (page >> 8) & 0xff); |
|
|
|
if (device->address_cycles >= 4) |
|
|
|
{ |
|
|
|
retval |= imx31_address (device, (page >> 16) & 0xff); |
|
|
|
if (device->address_cycles >= 5) |
|
|
|
{ |
|
|
|
retval |= imx31_address (device, (page >> 24) & 0xff); |
|
|
|
} |
|
|
|
} |
|
|
|
target_write_buffer (target, MX3_NF_MAIN_BUFFER0, data_size, data); |
|
|
|
if (oob) |
|
|
|
{ |
|
|
|
if (mx3_nf_info->flags.hw_ecc_enabled) |
|
|
|
{ |
|
|
|
/* |
|
|
|
* part of spare block will be overrided by hardware |
|
|
|
* ECC generator |
|
|
|
*/ |
|
|
|
LOG_DEBUG |
|
|
|
("part of spare block will be overrided by hardware ECC generator"); |
|
|
|
} |
|
|
|
target_write_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size, |
|
|
|
oob); |
|
|
|
} |
|
|
|
/* |
|
|
|
* start data input operation (set MX3_NF_BIT_OP_DONE==0) |
|
|
|
*/ |
|
|
|
target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI); |
|
|
|
{ |
|
|
|
int poll_result; |
|
|
|
poll_result = poll_for_complete_op (target, "data input"); |
|
|
|
if (poll_result != ERROR_OK) |
|
|
|
{ |
|
|
|
return poll_result; |
|
|
|
} |
|
|
|
} |
|
|
|
retval |= imx31_command (device, NAND_CMD_PAGEPROG); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
{ |
|
|
|
return retval; |
|
|
|
} |
|
|
|
|
|
|
|
/* |
|
|
|
* check status register |
|
|
|
*/ |
|
|
|
{ |
|
|
|
uint16_t nand_status_content; |
|
|
|
retval = ERROR_OK; |
|
|
|
retval |= imx31_command (device, NAND_CMD_STATUS); |
|
|
|
retval |= imx31_address (device, 0x00); |
|
|
|
retval |= do_data_output (device); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
{ |
|
|
|
LOG_ERROR (get_status_register_err_msg); |
|
|
|
return retval; |
|
|
|
} |
|
|
|
target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content); |
|
|
|
if (nand_status_content & 0x0001) |
|
|
|
{ |
|
|
|
/* |
|
|
|
* is host-big-endian correctly ?? |
|
|
|
*/ |
|
|
|
return ERROR_NAND_OPERATION_FAILED; |
|
|
|
} |
|
|
|
} |
|
|
|
} |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
static int imx31_read_page (struct nand_device_s *device, uint32_t page, |
|
|
|
uint8_t * data, uint32_t data_size, uint8_t * oob, |
|
|
|
uint32_t oob_size) |
|
|
|
{ |
|
|
|
mx3_nf_controller_t *mx3_nf_info = device->controller_priv; |
|
|
|
target_t *target = mx3_nf_info->target; |
|
|
|
|
|
|
|
if (data_size % 2) |
|
|
|
{ |
|
|
|
LOG_ERROR (data_block_size_err_msg, data_size); |
|
|
|
return ERROR_NAND_OPERATION_FAILED; |
|
|
|
} |
|
|
|
if (oob_size % 2) |
|
|
|
{ |
|
|
|
LOG_ERROR (data_block_size_err_msg, oob_size); |
|
|
|
return ERROR_NAND_OPERATION_FAILED; |
|
|
|
} |
|
|
|
|
|
|
|
{ |
|
|
|
/* |
|
|
|
* validate target state |
|
|
|
*/ |
|
|
|
int retval; |
|
|
|
retval = validate_target_state (device); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
{ |
|
|
|
return retval; |
|
|
|
} |
|
|
|
} |
|
|
|
{ |
|
|
|
int retval = ERROR_OK; |
|
|
|
retval |= imx31_command (device, NAND_CMD_READ0); |
|
|
|
retval |= imx31_address (device, 0x00); |
|
|
|
retval |= imx31_address (device, page & 0xff); |
|
|
|
retval |= imx31_address (device, (page >> 8) & 0xff); |
|
|
|
if (device->address_cycles >= 4) |
|
|
|
{ |
|
|
|
retval |= imx31_address (device, (page >> 16) & 0xff); |
|
|
|
if (device->address_cycles >= 5) |
|
|
|
{ |
|
|
|
retval |= imx31_address (device, (page >> 24) & 0xff); |
|
|
|
retval |= imx31_command (device, NAND_CMD_READSTART); |
|
|
|
} |
|
|
|
} |
|
|
|
retval |= do_data_output (device); |
|
|
|
if (retval != ERROR_OK) |
|
|
|
{ |
|
|
|
return retval; |
|
|
|
} |
|
|
|
|
|
|
|
if (data) |
|
|
|
{ |
|
|
|
target_read_buffer (target, MX3_NF_MAIN_BUFFER0, data_size, |
|
|
|
data); |
|
|
|
} |
|
|
|
if (oob) |
|
|
|
{ |
|
|
|
target_read_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size, |
|
|
|
oob); |
|
|
|
} |
|
|
|
} |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
static int test_iomux_settings (target_t * target, uint32_t address, |
|
|
|
uint32_t mask, const char *text) |
|
|
|
{ |
|
|
|
uint32_t register_content; |
|
|
|
target_read_u32 (target, address, ®ister_content); |
|
|
|
if ((register_content & mask) != (0x12121212 & mask)) |
|
|
|
{ |
|
|
|
LOG_ERROR ("IOMUX for {%s} is bad", text); |
|
|
|
return ERROR_FAIL; |
|
|
|
} |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
static int initialize_nf_controller (struct nand_device_s *device) |
|
|
|
{ |
|
|
|
mx3_nf_controller_t *mx3_nf_info = device->controller_priv; |
|
|
|
target_t *target = mx3_nf_info->target; |
|
|
|
/* |
|
|
|
* resets NAND flash controller in zero time ? I dont know. |
|
|
|
*/ |
|
|
|
target_write_u16 (target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN); |
|
|
|
{ |
|
|
|
uint16_t work_mode; |
|
|
|
work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */ |
|
|
|
if (target->endianness == TARGET_BIG_ENDIAN) |
|
|
|
{ |
|
|
|
work_mode |= MX3_NF_BIT_BE_EN; |
|
|
|
} |
|
|
|
if (mx3_nf_info->flags.hw_ecc_enabled) |
|
|
|
{ |
|
|
|
work_mode |= MX3_NF_BIT_ECC_EN; |
|
|
|
} |
|
|
|
target_write_u16 (target, MX3_NF_CFG1, work_mode); |
|
|
|
} |
|
|
|
/* |
|
|
|
* unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock" |
|
|
|
*/ |
|
|
|
target_write_u16 (target, MX3_NF_BUFCFG, 2); |
|
|
|
{ |
|
|
|
uint16_t temp; |
|
|
|
target_read_u16 (target, MX3_NF_FWP, &temp); |
|
|
|
if ((temp & 0x0007) == 1) |
|
|
|
{ |
|
|
|
LOG_ERROR ("NAND flash is tight-locked, reset needed"); |
|
|
|
return ERROR_FAIL; |
|
|
|
} |
|
|
|
|
|
|
|
} |
|
|
|
/* |
|
|
|
* unlock NAND flash for write |
|
|
|
*/ |
|
|
|
target_write_u16 (target, MX3_NF_FWP, 4); |
|
|
|
target_write_u16 (target, MX3_NF_LOCKSTART, 0x0000); |
|
|
|
target_write_u16 (target, MX3_NF_LOCKEND, 0xFFFF); |
|
|
|
/* |
|
|
|
* 0x0000 means that first SRAM buffer @0xB800_0000 will be used |
|
|
|
*/ |
|
|
|
target_write_u16 (target, MX3_NF_BUFADDR, 0x0000); |
|
|
|
/* |
|
|
|
* address of SRAM buffer |
|
|
|
*/ |
|
|
|
in_sram_address = MX3_NF_MAIN_BUFFER0; |
|
|
|
sign_of_sequental_byte_read = 0; |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
static int get_next_byte_from_sram_buffer (target_t * target, uint8_t * value) |
|
|
|
{ |
|
|
|
static uint8_t even_byte = 0; |
|
|
|
/* |
|
|
|
* host-big_endian ?? |
|
|
|
*/ |
|
|
|
if (sign_of_sequental_byte_read == 0) |
|
|
|
{ |
|
|
|
even_byte = 0; |
|
|
|
} |
|
|
|
if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR) |
|
|
|
{ |
|
|
|
LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address); |
|
|
|
*value = 0; |
|
|
|
sign_of_sequental_byte_read = 0; |
|
|
|
even_byte = 0; |
|
|
|
return ERROR_NAND_OPERATION_FAILED; |
|
|
|
} |
|
|
|
else |
|
|
|
{ |
|
|
|
uint16_t temp; |
|
|
|
target_read_u16 (target, in_sram_address, &temp); |
|
|
|
if (even_byte) |
|
|
|
{ |
|
|
|
*value = temp >> 8; |
|
|
|
even_byte = 0; |
|
|
|
in_sram_address += 2; |
|
|
|
} |
|
|
|
else |
|
|
|
{ |
|
|
|
*value = temp & 0xff; |
|
|
|
even_byte = 1; |
|
|
|
} |
|
|
|
} |
|
|
|
sign_of_sequental_byte_read = 1; |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
static int get_next_halfword_from_sram_buffer (target_t * target, |
|
|
|
uint16_t * value) |
|
|
|
{ |
|
|
|
if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR) |
|
|
|
{ |
|
|
|
LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address); |
|
|
|
*value = 0; |
|
|
|
return ERROR_NAND_OPERATION_FAILED; |
|
|
|
} |
|
|
|
else |
|
|
|
{ |
|
|
|
target_read_u16 (target, in_sram_address, value); |
|
|
|
in_sram_address += 2; |
|
|
|
} |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
static int poll_for_complete_op (target_t * target, const char *text) |
|
|
|
{ |
|
|
|
uint16_t poll_complete_status; |
|
|
|
for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) |
|
|
|
{ |
|
|
|
usleep (25); |
|
|
|
target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status); |
|
|
|
if (poll_complete_status & MX3_NF_BIT_OP_DONE) |
|
|
|
{ |
|
|
|
break; |
|
|
|
} |
|
|
|
} |
|
|
|
if (!(poll_complete_status & MX3_NF_BIT_OP_DONE)) |
|
|
|
{ |
|
|
|
LOG_ERROR ("%s sending timeout", text); |
|
|
|
return ERROR_NAND_OPERATION_FAILED; |
|
|
|
} |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
static int validate_target_state (struct nand_device_s *device) |
|
|
|
{ |
|
|
|
mx3_nf_controller_t *mx3_nf_info = device->controller_priv; |
|
|
|
target_t *target = mx3_nf_info->target; |
|
|
|
|
|
|
|
if (target->state != TARGET_HALTED) |
|
|
|
{ |
|
|
|
LOG_ERROR (target_not_halted_err_msg); |
|
|
|
return ERROR_NAND_OPERATION_FAILED; |
|
|
|
} |
|
|
|
|
|
|
|
if (mx3_nf_info->flags.target_little_endian != |
|
|
|
(target->endianness == TARGET_LITTLE_ENDIAN)) |
|
|
|
{ |
|
|
|
/* |
|
|
|
* endianness changed after NAND controller probed |
|
|
|
*/ |
|
|
|
return ERROR_NAND_OPERATION_FAILED; |
|
|
|
} |
|
|
|
return ERROR_OK; |
|
|
|
} |
|
|
|
|
|
|
|
static int do_data_output (struct nand_device_s *device) |
|
|
|
{ |
|
|
|
mx3_nf_controller_t *mx3_nf_info = device->controller_priv; |
|
|
|
target_t *target = mx3_nf_info->target; |
|
|
|
switch (mx3_nf_info->fin) |
|
|
|
{ |
|
|
|
case MX3_NF_FIN_DATAOUT: |
|
|
|
/* |
|
|
|
* start data output operation (set MX3_NF_BIT_OP_DONE==0) |
|
|
|
*/ |
|
|
|
target_write_u16 (target, MX3_NF_CFG2, |
|
|
|
MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info-> |
|
|
|
optype)); |
|
|
|
{ |
|
|
|
int poll_result; |
|
|
|
poll_result = poll_for_complete_op (target, "data output"); |
|
|
|
if (poll_result != ERROR_OK) |
|
|
|
{ |
|
|
|
return poll_result; |
|
|
|
} |
|
|
|
} |
|
|
|
mx3_nf_info->fin = MX3_NF_FIN_NONE; |
|
|
|
/* |
|
|
|
* ECC stuff |
|
|
|
*/ |
|
|
|
if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE) |
|
|
|
&& mx3_nf_info->flags.hw_ecc_enabled) |
|
|
|
{ |
|
|
|
uint16_t ecc_status; |
|
|
|
target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status); |
|
|
|
switch (ecc_status & 0x000c) |
|
|
|
{ |
|
|
|
case 1 << 2: |
|
|
|
LOG_DEBUG |
|
|
|
("main area readed with 1 (correctable) error"); |
|
|
|
break; |
|
|
|
case 2 << 2: |
|
|
|
LOG_DEBUG |
|
|
|
("main area readed with more than 1 (incorrectable) error"); |
|
|
|
return ERROR_NAND_OPERATION_FAILED; |
|
|
|
break; |
|
|
|
} |
|
|
|
switch (ecc_status & 0x0003) |
|
|
|
{ |
|
|
|
case 1: |
|
|
|
LOG_DEBUG |
|
|
|
("spare area readed with 1 (correctable) error"); |
|
|
|
break; |
|
|
|
case 2: |
|
|
|
LOG_DEBUG |
|
|
|
("main area readed with more than 1 (incorrectable) error"); |
|
|
|
return ERROR_NAND_OPERATION_FAILED; |
|
|
|
break; |
|
|
|
} |
|
|
|
} |
|
|
|
break; |
|
|
|
case MX3_NF_FIN_NONE: |
|
|
|
break; |
|
|
|
} |
|
|
|
return ERROR_OK; |
|
|
|
} |